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| official product documentation 5/3/06 product data sheet copyright ? 2003-2006 sigmatel, inc. all rights reserved. sigmatel, inc. makes no warranty for the use of its products, a ssumes no responsibility for any errors which may appear in this document, and makes no commitment to update the information contained herein. sigmatel reserves the right to change or discontinue this product at any time, without no- tice. there are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on inform ation in this document. the following are trademarks of sigmatel, inc., and may be used to id entify sigmatel products only : sigmatel, the sigmatel logo , c major, d major and go-chip. windows media and the windows logo are trademarks or registered trademarks of microsoft corporation in the united states and/or other countries. other product and company names containe d herein may be trademarks of their respective owners. 5-36xx-d1-1.02-050306 STMP36XX audio system on chip with usb otg, lcd, hard drive, and battery charger fourth-generation audio decoder version 1.02 may 3, 2006 host processor (optional) fm tuner microphone voice record nand flash buttons/switches hard drive headphones sd/sdio/ms sdram/nor spdif rechargeable battery led/lcd/color display hi-speed usb on-the-go iso9001:2000 certified iec qc 080000:2005 (iecq hspm) certified free datasheet http:///
2 5-36xx-d1-1.02-050306 STMP36XX official product documentation 5/3/06 the product shown in this data sheet is not designed fo r use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. any use or distribution of this product in such applications is at your own risk. sigmatel, inc. does not assume any lia- bility arising out of the application or use of any product or circuit sh own herein, and specifically disclaims any and all liability, including without limitation special, conse quential, or incidental damages. supply of this implementation of aac technology does not convey a license nor imply any right to use this implementa- tion in any finished end-user or re ady-to-use final product. an independent license for such use is required. customer support additional product and company information can be obtained by going to the sigmatel website at: http://www.sigmatel.com additional product and design information is available for authorized customers at: http://extranet.sigmatel.com free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 contents 3 contents revision history............................................................................................................... ...... 21 1. product overview ............................................................................................................ ..... 23 1.1. hardware features ........................................................................................................ ................. 23 1.2. application capability ................................................................................................... ................... 24 1.3. design support ........................................................................................................... .................... 25 1.4. additional documentation .. ............................................................................................... .............. 25 1.5. STMP36XX system block diagram ............................................................................................ ..... 26 1.6. STMP36XX product features ................................................................................................ .......... 27 1.6.1. arm 926 processor core ................................................................................................. 27 1.6.2. on-chip ram and rom ................................................................................................... 2 9 1.6.3. interrupt collector ................................ .................................................................... .......... 30 1.6.4. default first-level page table .................. ....................................................................... .30 1.6.5. external memory interface (sdram/nor fl ash controller) ............................................ 30 1.6.6. dma controller ......................................................................................................... ......... 31 1.6.7. clock generation subsystem ............................................................................................ 3 1 1.6.8. power management unit .... .............. .............. .............. .............. .............. .............. .......... .32 1.6.9. usb interface .......................................................................................................... .......... 33 1.6.10. general-purpose media interface (gpmi) ... ................................................................... 33 1.6.11. hardware acceleration for ecc for robust external storage ......................................... 34 1.6.12. memory copy unit ...................................................................................................... .... 34 1.6.13. mixed signal audio subsystem ............ .............. .............. .............. .............. ........... ........ 35 1.6.14. master digital control unit (digctl) .............................................................................. 35 1.6.15. synchronous serial port (ssp) ......... .............. .............. .............. .............. .............. ........ 35 1.6.16. i 2 c interface ................................................................................................................... .35 1.6.17. general-purpose input/output (gpio) ............................................................................ 36 1.6.18. lcd controller ........................................................................................................ ........ 37 1.6.19. spdif transmitter ..................................................................................................... ..... 37 1.6.20. rotary decoder ........................................................................................................ ....... 37 1.6.21. dual uarts ............................................................................................................ ........ 37 1.6.22. infrared interface .................................................................................................... ......... 37 1.6.23. low-resolution adc and touc h-screen interface ......................................................... 37 1.6.24. pulse width modulator (pwm) controller ....................................................................... 37 1.6.25. camera interface ...................................................................................................... ...... 38 2. characteristics and specifications ............................................................................ 39 2.1. absolute maximum ratings .. ............................................................................................... ........... 39 2.2. recommended operating conditions ............ .............. .............. .............. .............. ............ ......... .... 40 2.2.1. recommended operating conditions for spec ific clock targets ..................................... 41 2.3. dc characteristics ....................................................................................................... ................... 42 3. arm cpu complex ............................................................................................................. ...... 43 3.1. arm 926 processor core ................................................................................................... ............ 43 3.2. jtag debugger ......... .............. .............. .............. .............. ........... ........... ........... .......... .................. 45 3.2.1. jtag read id ........................................................................................................... ...... 45 3.2.2. jtag hardware reset .... ................................................................................................ .. 45 3.2.3. jtag interaction with cpuclk ........................................................................................ 45 3.3. embedded trace macrocell (etm) interface .......... .............. .............. ........... ........... ........... .......... .46 4. clock generation and control ..................................................................................... 47 4.1. overview ................................................................................................................. ........................ 47 4.2. crystal oscillators ...................................................................................................... ..................... 47 4.3. clock domains ............................................................................................................ .................... 47 4.4. power saving features of the clock architecture .......................................................................... .49 4.5. clock dividers ........................................................................................................... ...................... 49 4.5.1. automatic hclk divider ................................................................................................. .. 49 4.6. phase-locked loop (pll) .................................................................................................. ............ 51 4.6.1. frequency program ...................................................................................................... .... 52 4.6.2. pll use in usb and spdif modes .................................................................................. 52 4.6.3. vco and phase followers .... .............. .............. .............. .............. .............. ........... ........... 53 4.6.4. pfd and charge pump ......... .............. .............. .............. .............. .............. ........... .......... .53 free datasheet http:/// STMP36XX official product documentation 5/3/06 4 contents 5-36xx-d1-1.02-050306 4.7. integrated usb 2.0 phy initiali zation flow charts ........................................................................ .54 4.8. clocking during reset .................................................................................................... ................ 55 4.9. programmable registers ................................................................................................... ............. 56 4.9.1. pll control register 0 desc ription ................................................................................... 56 4.9.2. pll control register 1 desc ription ................................................................................... 58 4.9.3. cpu clock control register description ........................................................................... 58 4.9.4. ahb, apbh bus clock control register descr iption ........................................................ 59 4.9.5. apbx clock control register de scription ......... .............. .............. .............. .............. ........ 61 4.9.6. xtal clock control register description ......................................................................... 62 4.9.7. on-chip sram clock control register description .......................................................... 63 4.9.8. utmi clock control register description .......................................................................... 63 4.9.9. synchronous serial port clock control regi ster description ............................................ 64 4.9.10. general-purpose media inte rface clock control register de scription ........................... 65 4.9.11. spdif clock control register description ... ................................................................... 66 4.9.12. emi clock control register description ....... ................................................................... 67 4.9.13. ir clock control register description ............................................................................. 67 5. interrupt collector ......................................................................................................... .. 69 5.1. overview ................................................................................................................. ........................ 69 5.2. nesting of multi-level irq in terrupts .................................................................................... .......... 72 5.3. fiq generation ........................................................................................................... .................... 73 5.4. interrupt sources ................................... ..................................................................... .................... 75 5.5. cpu wait-for-interrupt mode .............................................................................................. ............ 77 5.6. behavior during reset .................................................................................................... ................ 77 5.7. programmable registers ................................................................................................... ............. 78 5.7.1. interrupt collector interrupt vector addre ss register description ... ................................. 78 5.7.2. interrupt collector level acknowledge regist er description ............................................ 78 5.7.3. interrupt collector control register description ................................................................ 79 5.7.4. interrupt collector status register description ................................................................. 81 5.7.5. interrupt collector raw inte rrupt input register 0 description .......................................... 82 5.7.6. interrupt collector raw inte rrupt input register 1 description .......................................... 83 5.7.7. interrupt collector priority register 0 description ............................................................. 83 5.7.8. interrupt collector priority register 1 description ............................................................. 85 5.7.9. interrupt collector priority register 2 description ............................................................. 86 5.7.10. interrupt collector priority register 3 description ........................................................... 88 5.7.11. interrupt collector priority register 4 description ........................................................... 90 5.7.12. interrupt collector priority register 5 description ........................................................... 91 5.7.13. interrupt collector priority register 6 description ........................................................... 93 5.7.14. interrupt collector priority register 7 description ........................................................... 95 5.7.15. interrupt collector priority register 8 description ........................................................... 96 5.7.16. interrupt collector priority register 9 description ........................................................... 98 5.7.17. interrupt collector priority register 10 description ....................................................... 100 5.7.18. interrupt collector priority register 11 description ....................................................... 101 5.7.19. interrupt collector priority register 12 description ....................................................... 103 5.7.20. interrupt collector priority register 13 description ....................................................... 105 5.7.21. interrupt collector priority register 14 description ....................................................... 106 5.7.22. interrupt collector priority register 15 description ....................................................... 108 5.7.23. interrupt collector interr upt vector base address register description ....................... 110 5.7.24. interrupt collector debug r egister 0 description .......................................................... 110 5.7.25. interrupt collector debug read register 0 description ...... .......................................... 112 5.7.26. interrupt collector debug read register 1 description ...... .......................................... 112 5.7.27. interrupt collector debug fl ag register description ........... .......................................... 113 5.7.28. interrupt collector debug read request register 0 description .................................. 113 5.7.29. interrupt collector debug read request register 1 description .................................. 114 6. default first-level page table for arm926 mmu .................................................. 115 6.1. overview ................................................................................................................. ...................... 115 6.2. 16-megabyte page-mapped virtual memory (0xffx xxxxx) ............ .............. ........... ........... ...... 117 6.2.1. default first-level page table entry 4095 . .................................................................... 118 6.2.2. default first-level page table entries 409 4?4080 ................ ............ ........... ........... ...... 119 6.2.3. default first-level page table pio regist er map entry 2048 ............ ........... ........... ...... 120 6.2.4. default first-level page table entry 0000 v==r sram access ................................... 121 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 contents 5 7. digital control and on-chip ram ................................................................................. 123 7.1. overview ................................................................................................................. ...................... 123 7.2. sram controls ............................................................................................................ ................. 124 7.2.1. sram bist control ...................................................................................................... .. 126 7.3. rom controls ............................................................................................................. .................. 127 7.4. miscellaneous controls ...... .............. .............. .............. .............. .............. ........... ............ .............. 127 7.4.1. performance monitoring .. ............................................................................................... .127 7.4.2. high-entropy prn seed ................................................................................................. 1 27 7.4.3. write-once register .................................................................................................... .... 128 7.4.4. microseconds counter .............................. ..................................................................... .128 7.5. behavior during reset .................................................................................................... .............. 128 7.6. programmable registers ................................................................................................... ........... 128 7.6.1. digctl control register description ......... .................................................................... 128 7.6.2. digctl status regi ster description .............................................................................. 130 7.6.3. free-running hclk counter register descripti on ......................................................... 131 7.6.4. on-chip ram control regist er description .................................................................... 131 7.6.5. on-chip ram repair data 0 register descript ion ......................................................... 133 7.6.6. on-chip ram repair data 1 register descript ion ......................................................... 134 7.6.7. software write-once register description .. .................................................................... 135 7.6.8. ahb transfer count register description ...................... ................................................ 136 7.6.9. ahb performance metric for stalled bus cycl es register description ........................... 136 7.6.10. entropy register description .................. ...................................................................... 13 7 7.6.11. digital control rom shield read enable r egister description ........ ............................ 138 7.6.12. digital control microsecon ds counter register description ............. ........... ........... ...... 138 7.6.13. digital control debug read test register description ....... .......................................... 139 7.6.14. digital control debug register description ................................................................... 139 7.6.15. sram bist contro l and status register description ................................................... 140 7.6.16. sram bist repair register 0 description ................... ................................................ 140 7.6.17. sram bist repair register 1 description ................... ................................................ 141 7.6.18. sram status regi ster 0 description ............................................................................ 142 7.6.19. sram status regi ster 1 description ............................................................................ 142 7.6.20. sram status regi ster 2 description ............................................................................ 143 7.6.21. sram status regi ster 3 description ............................................................................ 143 7.6.22. sram status regi ster 4 description ............................................................................ 144 7.6.23. sram status regi ster 5 description ............................................................................ 144 7.6.24. sram status regi ster 6 description ............................................................................ 145 7.6.25. sram status regi ster 7 description ............................................................................ 145 7.6.26. sram status regi ster 8 description ............................................................................ 146 7.6.27. sram status regi ster 9 description ............................................................................ 146 7.6.28. sram status register 10 description .......................................................................... 147 7.6.29. sram status register 11 description .......................................................................... 147 7.6.30. sram status register 12 description .......................................................................... 148 7.6.31. sram status register 13 description .......................................................................... 149 7.6.32. digital control sc ratch register 0 description .............. ................................................ 150 7.6.33. digital control sc ratch register 1 description .............. ................................................ 150 7.6.34. digital control arm cache register descript ion .......................................................... 151 7.6.35. sigmatel copyright identifi er register description ............. .......................................... 151 7.6.36. digital control chip revisi on register description ............. .......................................... 152 8. usb high-speed on-the-go (host/device) controller .......................................... 155 8.1. overview ................................................................................................................. ...................... 155 8.2. usb controller core ................................. ..................................................................... ............... 155 8.3. usb programmed i/o (pio) target interface ......... ...................................................................... 1 57 8.4. usb dma interface ........................................................................................................ ............... 157 8.5. usb utmi interface ....................................................................................................... ............... 157 8.5.1. exporting the phy ...................................................................................................... ..... 157 8.5.2. digital/analog loopback test mode ........... .............. .............. ............ ........... ........... ...... 157 8.6. usb controller flowcharts ................................................................................................ ............ 158 9. integrated usb 2.0 phy ...................................................................................................... 161 9.1. overview ................................................................................................................. ...................... 161 9.2. external signals ...... .............. .............. .............. .............. ........... ........... ............ ......... ................... 161 9.3. utmi and digital circuits ................................................................................................ .............. 162 free datasheet http:/// STMP36XX official product documentation 5/3/06 6 contents 5-36xx-d1-1.02-050306 9.3.1. utmi block ............................................................................................................. ......... 162 9.3.2. digital transmitter block .............................................................................................. ... 162 9.3.3. digital receiver block ................................................................................................. .... 162 9.3.4. programmable registers block ................... .................................................................... 162 9.4. analog transceiver ....................................................................................................... ................ 163 9.4.1. analog receiver ........................................................................................................ ...... 163 9.4.2. analog transmitter ..................................................................................................... ..... 164 9.5. behavior during reset .................................................................................................... .............. 169 9.6. programmable registers ................................................................................................... ........... 169 9.6.1. usb phy power-down register description . ................................................................. 169 9.6.2. usb phy transmitter contro l register description ............... ........................................ 170 9.6.3. usb phy receiver control register descripti on ........................................................... 172 9.6.4. usb phy general control register description ............................................................. 173 9.6.5. usb phy status register de scription ............................................................................ 175 9.6.6. usb phy debug register de scription ........................................................................... 176 9.6.7. utmi debug status register 0 description .................................................................... 177 9.6.8. utmi debug status register 1 description .................................................................... 178 9.6.9. utmi debug status register 2 description .................................................................... 179 9.6.10. utmi debug status register 3 description .................................................................. 180 9.6.11. utmi debug status register 4 description .................................................................. 181 9.6.12. utmi debug status register 5 description .................................................................. 181 9.6.13. utmi debug status register 6 description .................................................................. 182 9.6.14. utmi debug status register 7 description .................................................................. 183 9.6.15. utmi debug status register 8 description .................................................................. 184 10. ahb-to-apbh bridge with dma ......................................................................................... 185 10.1. overview ................................................................................................................ ..................... 185 10.2. ahbh dma ................................................................................................................ ................. 186 10.3. implementation examples ................................................................................................. .......... 190 10.3.1. hwecc example command chain ................ .............................................................. 190 10.3.2. nand read status polling example ............................................................................ 191 10.3.3. apbh dma and pio bus impl ementation example .. .............. .............. .............. ......... 193 10.4. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 194 10.5. programmable registers .................................................................................................. .......... 195 10.5.1. ahb-to-apbh bridge control and status register 0 description .. .............. ........... ...... 195 10.5.2. ahb-to-apbh bridge control and status register 1 description .. .............. ........... ...... 196 10.5.3. ahb-to-apbh dma device assignment register de scription .... .............. .............. ...... 198 10.5.4. apbh dma channel 0 current command a ddress register description .................... 199 10.5.5. apbh dma channel 0 next command addre ss register description ......................... 199 10.5.6. apbh dma channel 0 command register de scription ............................................... 200 10.5.7. apbh dma channel 0 buffer address regist er description ............ ............................ 202 10.5.8. apbh dma channel 0 semaphore register description ............................................. 202 10.5.9. ahb-to-apbh dma channel 0 debug register 1 description .............. .............. ......... 203 10.5.10. ahb-to-apbh dma channel 0 debug register 2 description ................................... 205 10.5.11. apbh dma channel 1 current command a ddress register descrip tion ......... ......... 206 10.5.12. apbh dma channel 1 next command addre ss register description .............. ......... 207 10.5.13. apbh dma channel 1 command register de scription ........ .............. .............. ......... 207 10.5.14. apbh dma channel 1 buffer address regist er description ............ ............ .............. 209 10.5.15. apbh dma channel 1 semaphore register de scription ...... .............. .............. ......... 210 10.5.16. ahb-to-apbh dma channel 1 debug register 1 description ................................... 211 10.5.17. ahb-to-apbh dma channel 1 debug register 2 description ................................... 212 10.5.18. apbh dma channel 2 current command a ddress register descrip tion ......... ......... 213 10.5.19. apbh dma channel 2 next command addre ss register description .............. ......... 214 10.5.20. apbh dma channel 2 command register de scription ........ .............. .............. ......... 214 10.5.21. apbh dma channel 2 buffer address regist er description ............ ............ .............. 216 10.5.22. apbh dma channel 2 semaphore register de scription ...... .............. .............. ......... 217 10.5.23. ahb-to-apbh dma channel 2 debug register 1 description ................................... 218 10.5.24. ahb-to-apbh dma channel 2 debug register 2 description ................................... 219 10.5.25. apbh dma channel 3 current command a ddress register descrip tion ......... ......... 220 10.5.26. apbh dma channel 3 next command addre ss register description .............. ......... 221 10.5.27. apbh dma channel 3 command register de scription ........ .............. .............. ......... 221 10.5.28. apbh dma channel 3 buffer address regist er description ............ ............ .............. 223 10.5.29. apbh dma channel 3 semaphore register de scription ...... .............. .............. ......... 224 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 contents 7 10.5.30. ahb-to-apbh dma channel 3 debug register 1 description ................................... 225 10.5.31. ahb-to-apbh dma channel 3 debug register 2 description ................................... 226 10.5.32. apbh dma channel 4 current command a ddress register descrip tion ......... ......... 227 10.5.33. apbh dma channel 4 next command addre ss register description .............. ......... 228 10.5.34. apbh dma channel 4 command register de scription ........ .............. .............. ......... 228 10.5.35. apbh dma channel 4 buffer address regist er description ............ ............ .............. 230 10.5.36. apbh dma channel 4 semaphore register de scription ...... .............. .............. ......... 231 10.5.37. ahb-to-apbh dma channel 4 debug register 1 description ................................... 232 10.5.38. ahb-to-apbh dma channel 4 debug register 2 description ................................... 233 10.5.39. apbh dma channel 5 current command a ddress register descrip tion ......... ......... 234 10.5.40. apbh dma channel 5 next command addre ss register description .............. ......... 235 10.5.41. apbh dma channel 5 command register de scription ........ .............. .............. ......... 235 10.5.42. apbh dma channel 5 buffer address regist er description ............ ............ .............. 237 10.5.43. apbh dma channel 5 semaphore register de scription ...... .............. .............. ......... 238 10.5.44. ahb-to-apbh dma channel 5 debug register 1 description ................................... 239 10.5.45. ahb-to-apbh dma channel 5 debug register 2 description ................................... 240 10.5.46. apbh dma channel 6 current command a ddress register descrip tion ......... ......... 241 10.5.47. apbh dma channel 6 next command addre ss register description .............. ......... 242 10.5.48. apbh dma channel 6 command register de scription ........ .............. .............. ......... 242 10.5.49. apbh dma channel 6 buffer address regist er description ............ ............ .............. 244 10.5.50. apbh dma channel 6 semaphore register de scription ...... .............. .............. ......... 245 10.5.51. ahb-to-apbh dma channel 6 debug register 1 description ................................... 246 10.5.52. ahb-to-apbh dma channel 6 debug register 2 description ................................... 247 10.5.53. apbh dma channel 7 current command a ddress register descrip tion ......... ......... 248 10.5.54. apbh dma channel 7 next command addre ss register description .............. ......... 249 10.5.55. apbh dma channel 7 command register de scription ........ .............. .............. ......... 249 10.5.56. apbh dma channel 7 buffer address regist er description ............ ............ .............. 251 10.5.57. apbh dma channel 7 semaphore register de scription ...... .............. .............. ......... 252 10.5.58. ahb-to-apbh dma channel 7 debug register 1 description ................................... 253 10.5.59. ahb-to-apbh dma channel 7 debug register 2 description ................................... 254 11. ahb-to-apbx bridge with dma ......................................................................................... 257 11.1. overview ................................................................................................................ ..................... 257 11.2. apbx dma ................................................................................................................ ................. 258 11.3. dma chain example ....................................................................................................... ............ 261 11.4. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 262 11.5. programmable registers .................................................................................................. .......... 263 11.5.1. ahb-to-apbx bridge control and status register 0 description .......... .............. ......... 263 11.5.2. ahb-to-apbx bridge control and status register 1 description .......... .............. ......... 264 11.5.3. ahb-to-apbx dma device a ssignment register de scription ....... .............. ........... ...... 266 11.5.4. apbx dma channel 0 current command addr ess register descripti on ........... ......... 267 11.5.5. apbx dma channel 0 next command addres s register description ........... .............. 267 11.5.6. apbx dma channel 0 command register descr iption .......... .............. .............. ......... 268 11.5.7. apbx dma channel 0 buffer address regist er description ............ ........... ........... ...... 270 11.5.8. apbx dma channel 0 semaphore register de scription ........ .............. .............. ......... 270 11.5.9. ahb-to-apbx dma channel 0 debug register 1 description . .............. .............. ......... 271 11.5.10. ahb-to-apbx dma ch annel 0 debug register 2 description .......... ............ ........... ... 273 11.5.11. apbx dma channel 1 current command addr ess register descript ion ......... ......... 274 11.5.12. apbx dma channel 1 next command address register description ...... ........... ...... 275 11.5.13. apbx dma channel 1 command register description ..... ............ ........... ........... ...... 275 11.5.14. apbx dma channel 1 buffer ad dress register description . .............. .............. ......... 277 11.5.15. apbx dma channel 1 semap hore register description ...... .............. .............. ......... 277 11.5.16. ahb-to-apbx dma ch annel 1 debug register 1 description .......... ............ ........... ... 278 11.5.17. ahb-to-apbx dma ch annel 1 debug register 2 description .......... ............ ........... ... 280 11.5.18. apbx dma channel 2 current command addr ess register descript ion ......... ......... 281 11.5.19. apbx dma channel 2 next command address register description ...... ........... ...... 282 11.5.20. apbx dma channel 2 command register description ..... ............ ........... ........... ...... 282 11.5.21. apbx dma channel 2 buffer ad dress register description . .............. .............. ......... 284 11.5.22. apbx dma channel 2 semap hore register description ...... .............. .............. ......... 284 11.5.23. ahb-to-apbx dma ch annel 2 debug register 1 description .......... ............ ........... ... 285 11.5.24. ahb-to-apbx dma ch annel 2 debug register 2 description .......... ............ ........... ... 287 11.5.25. apbx dma channel 3 current command addr ess register descript ion ......... ......... 288 11.5.26. apbx dma channel 3 next command address register description ...... ........... ...... 289 free datasheet http:/// STMP36XX official product documentation 5/3/06 8 contents 5-36xx-d1-1.02-050306 11.5.27. apbx dma channel 3 command register description ..... ............ ........... ........... ...... 289 11.5.28. apbx dma channel 3 buffer ad dress register description . .............. .............. ......... 291 11.5.29. apbx dma channel 3 semap hore register description ...... .............. .............. ......... 291 11.5.30. ahb-to-apbx dma ch annel 3 debug register 1 description .......... ............ ........... ... 292 11.5.31. ahb-to-apbx dma ch annel 3 debug register 2 description .......... ............ ........... ... 294 11.5.32. apbx dma channel 4 current command addr ess register descript ion ......... ......... 295 11.5.33. apbx dma channel 4 next command address register description ...... ........... ...... 296 11.5.34. apbx dma channel 4 command register description ..... ............ ........... ........... ...... 296 11.5.35. apbx dma channel 4 buffer ad dress register description . .............. .............. ......... 298 11.5.36. apbx dma channel 4 semap hore register description ...... .............. .............. ......... 298 11.5.37. ahb-to-apbx dma ch annel 4 debug register 1 description .......... ............ ........... ... 299 11.5.38. ahb-to-apbx dma ch annel 4 debug register 2 description .......... ............ ........... ... 301 11.5.39. apbx dma channel 5 current command addr ess register descript ion ......... ......... 302 11.5.40. apbx dma channel 5 next command address register description ...... ........... ...... 303 11.5.41. apbx dma channel 5 command register description ..... ............ ........... ........... ...... 303 11.5.42. apbx dma channel 5 buffer ad dress register description . .............. .............. ......... 305 11.5.43. apbx dma channel 5 semap hore register description ...... .............. .............. ......... 305 11.5.44. ahb-to-apbx dma ch annel 5 debug register 1 description .......... ............ ........... ... 306 11.5.45. ahb-to-apbx dma ch annel 5 debug register 2 description .......... ............ ........... ... 308 11.5.46. apbx dma channel 6 current command addr ess register descript ion ......... ......... 309 11.5.47. apbx dma channel 6 next command address register description ...... ........... ...... 310 11.5.48. apbx dma channel 6 command register description ..... ............ ........... ........... ...... 310 11.5.49. apbx dma channel 6 buffer ad dress register description . .............. .............. ......... 312 11.5.50. apbx dma channel 6 semap hore register description ...... .............. .............. ......... 312 11.5.51. ahb-to-apbx dma ch annel 6 debug register 1 description .......... ............ ........... ... 313 11.5.52. ahb-to-apbx dma ch annel 6 debug register 2 description .......... ............ ........... ... 315 11.5.53. apbx dma channel 7 current command addr ess register descript ion ......... ......... 316 11.5.54. apbx dma channel 7 next command address register description ...... ........... ...... 317 11.5.55. apbx dma channel 7 command register description ..... ............ ........... ........... ...... 317 11.5.56. apbx dma channel 7 buffer ad dress register description . .............. .............. ......... 319 11.5.57. apbx dma channel 7 semap hore register description ...... .............. .............. ......... 319 11.5.58. ahb-to-apbx dma ch annel 7 debug register 1 description .......... ............ ........... ... 320 11.5.59. ahb-to-apbx dma ch annel 7 debug register 2 description .......... ............ ........... ... 322 12. external memory interface (emi) ................................................................................. 325 12.1. overview ................................................................................................................ ..................... 325 12.2. dynamic memory controller ............................................................................................... ......... 326 12.2.1. dram timing ........................................................................................................... ..... 327 12.3. static memory controller (smc) .................. ........................................................................ ....... 327 12.4. emi operation example ................................................................................................... ........... 328 12.5. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 329 12.6. programmable registers .................................................................................................. .......... 329 12.6.1. emi control register description ................. ................................................................. 329 12.6.2. emi status register description ................................................................................... 330 12.6.3. emi debug register description ............... .................................................................... 331 12.6.4. emi dram status register description ........................................................................ 332 12.6.5. emi dram control register description ...................................................................... 333 12.6.6. emi dram address configuration register de scription .............................................. 334 12.6.7. emi dram mode configuration register de scription ................................................... 335 12.6.8. emi dram timing control r egister 1 description ........................................................ 336 12.6.9. emi dram timing control r egister 2 description ........................................................ 338 12.6.10. emi static memory contro l register description .............. .......................................... 338 12.6.11. emi static memory timing control register description ............................................ 339 13. general-purpose media interface (gpmi) .................................................................. 341 13.1. overview ................................................................................................................ ..................... 341 13.2. gpmi ata mode ........................................................................................................... .............. 341 13.2.1. basic ata operation ................................................................................................... .. 341 13.2.2. gpmi ata clocking and timing .................. ................................................................. 341 13.2.3. gpmi ata pin sharing ................................................................................................. 3 42 13.2.4. ata pio mode timing .................................................................................................. 3 43 13.2.5. ata udma mode ......................................................................................................... .343 13.2.6. udma timings .......................................................................................................... .... 344 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 contents 9 13.2.7. ata command/irq/check stat us example ................................................................. 344 13.3. gpmi nand mode .......................................................................................................... ............ 345 13.3.1. multiple nand support ................................................................................................. 345 13.3.2. gpmi nand timing and clocking ............... ................................................................. 345 13.3.3. basic nand timing ..................................................................................................... .346 13.3.4. nand command and address timing example ... .............. .............. ........... ........... ...... 346 13.3.5. nand read timing ...................................................................................................... .346 13.4. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 348 13.5. programmable registers .................................................................................................. .......... 348 13.5.1. gpmi control register 0 description ........ .................................................................... 348 13.5.2. gpmi compare register description ............................................................................ 351 13.5.3. gpmi control register 1 description ........ .................................................................... 351 13.5.4. gpmi timing register 0 description ......... .................................................................... 353 13.5.5. gpmi timing register 1 description ......... .................................................................... 354 13.5.6. gpmi timing register 2 description ......... .................................................................... 355 13.5.7. gpmi dma data transfer register descripti on ............................................................ 356 13.5.8. gpmi status regist er description ................................ ................................................ 356 13.5.9. gpmi debug information register description ............. .............. .............. .............. ...... 357 14. hardware ecc accelerator (hwecc) ......................................................................... 361 14.1. overview ................................................................................................................ ..................... 361 14.2. reed-solomon ecc accelerator ....................... ..................................................................... .... 362 14.2.1. reed-solomon encoding .......................... .................................................................... 364 14.2.2. reed-solomon decoding .......................... .................................................................... 366 14.2.3. reed-solomon decoding using pio debug mode ............... ............ ........... ........... ...... 371 14.3. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 372 14.4. programmable registers .................................................................................................. .......... 373 14.4.1. hardware ecc accelerator control register description ............................................. 373 14.4.2. hardware ecc accelerator status register description .............................................. 374 14.4.3. hardware ecc accelerator debug register 0 description ... ............ ........... ........... ...... 375 14.4.4. hardware ecc accelerator debug register 1 description ... ............ ........... ........... ...... 377 14.4.5. hardware ecc accelerator debug register 2 description ... ............ ........... ........... ...... 378 14.4.6. hardware ecc accelerator debug register 3 description ... ............ ........... ........... ...... 378 14.4.7. hardware ecc accelerator debug register 4 description ... ............ ........... ........... ...... 379 14.4.8. hardware ecc accelerator debug register 5 description ... ............ ........... ........... ...... 380 14.4.9. hardware ecc accelerator debug register 6 description ... ............ ........... ........... ...... 380 14.4.10. hardware ecc accelerator dma read/write data register descripti on ................... 381 15. synchronous serial port (ssp) ..................................................................................... 383 15.1. overview ................................................................................................................ ..................... 383 15.2. external pins ........................................................................................................... .................... 384 15.3. bit rate generation ......... .............. .............. .............. .............. .............. ........... ........... ............... 384 15.4. frame format for spi, ssi, and microwire ................................................................................ .384 15.5. motorola spi mode ....................................................................................................... .............. 385 15.5.1. spi dma mode .......................................................................................................... ... 385 15.5.2. motorola spi frame format .......................................................................................... 385 15.5.3. motorola spi format with polarity=0, phase= 0 ............................................................ 386 15.5.4. motorola spi format with polarity=0, phase= 1 ............................................................ 387 15.5.5. motorola spi format with polarity=1, phase= 0 ............................................................ 388 15.5.6. motorola spi format with polarity=1, phase= 1 ............................................................ 389 15.6. texas instruments synchronous se rial interface (ssi) mode .......... .............. ........... ........... ...... 390 15.7. national semiconductor microwire mode ........... ........................................................................ .391 15.8. sd/sdio/mmc mode ........................................................................................................ .......... 393 15.8.1. sd/mmc command/response transfer ......... .............................................................. 393 15.8.2. sd/mmc data block transfer ................... .................................................................... 394 15.8.3. sdio interrupts ....................................................................................................... ...... 397 15.8.4. sd/mmc mode error handling ............... .............. .............. .............. ........... ........... ...... 397 15.8.5. sd/mmc clock control ................................................................................................. 3 98 15.9. ms mode ................................................................................................................. .................... 398 15.9.1. ms mode i/o pins ...................................................................................................... ... 398 15.9.2. basic ms mode protocol .. .............. .............. .............. .............. .............. .............. ......... 3 98 15.9.3. ms mode high-level operation .................................................................................... 399 15.9.4. ms mode four-state bus protocol ........... .................................................................... 399 free datasheet http:/// STMP36XX official product documentation 5/3/06 10 contents 5-36xx-d1-1.02-050306 15.9.5. wait for card irq ..................................................................................................... ..... 401 15.9.6. checking card status ... ............................................................................................... .401 15.9.7. ms mode error conditions ............................................................................................ 40 2 15.9.8. ms mode details ....................................................................................................... .... 402 15.10. behavior during reset ...... ............................................................................................ ............ 402 15.11. programmable registers .............................. ................................................................... ......... 403 15.11.1. ssp cont rol register 0 description ... .............. .............. .............. .............. ........... ...... 403 15.11.2. sd/mmc and ms command register 0 descr iption .................................................. 405 15.11.3. sd/mmc command register 1 description .. .............................................................. 407 15.11.4. sd/mmc and ms compare reference regist er description ...................................... 407 15.11.5. sd/mmc and ms compare mask register de scription .............................................. 408 15.11.6. ssp timing register description ....... .............. .............. .............. .............. ........... ...... 408 15.11.7. ssp cont rol register 1 description ... .............. .............. .............. .............. ........... ...... 409 15.11.8. ssp data register description ....... .............. .............. .............. .............. .............. ...... 412 15.11.9. sd/mmc card response register 0 descripti on .......... .............. .............. ........... ...... 413 15.11.10. sd/mmc card response register 1 descr iption ..................................................... 413 15.11.11. sd/mmc card response register 2 descr iption ..................................................... 414 15.11.12. sd/mmc card response register 3 descr iption ..................................................... 414 15.11.13. ssp status regist er description ..... .............. .............. .............. .............. ........... ...... 414 15.11.14. ssp debug r egister description ............. .............. .............. .............. .............. ......... 416 16. lcd interface (lcdif) ...................................................................................................... .... 419 16.1. overview ................................................................................................................ ..................... 419 16.2. lcd interface operation example ......................................................................................... ..... 420 16.2.1. initialization steps .................................................................................................. ....... 421 16.2.2. run time steps ........................................................................................................ .... 421 16.3. lcdif pin timing diagrams ............................................................................................... ........ 422 16.4. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 422 16.5. programmable registers .................................................................................................. .......... 423 16.5.1. lcd interface control and status register description ................................................ 423 16.5.2. lcd interface timing register description ................................................................... 425 16.5.3. lcd interface data register description .. .................................................................... 425 16.5.4. lcd interface debug register description .. ................................................................. 426 17. pin control and gpio ....................................................................................................... .. 429 17.1. overview ................................................................................................................ ..................... 429 17.2. pin interface multiplexing ........................ ...................................................................... .............. 429 17.3. pin drive strength selection ............................................................................................ ........... 434 17.4. gpio interface .......................................................................................................... .................. 434 17.4.1. output operation ...................................................................................................... ..... 434 17.4.2. input operation ....................................................................................................... ...... 435 17.4.3. input interrupt operation ............................................................................................. .. 436 17.5. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 438 17.6. programmable registers .................................................................................................. .......... 439 17.6.1. pinctrl block control register description ............................................................... 439 17.6.2. pinctrl bank 0 lower pin mux select regi ster description ...................................... 440 17.6.3. pinctrl bank 0 upper pin mux select regi ster description ...................................... 441 17.6.4. pinctrl bank 0 drive str ength register description ......... ............ ........... ........... ...... 441 17.6.5. pinctrl bank 0 data outp ut register description ........... .......................................... 442 17.6.6. pinctrl bank 0 data input register descri ption ........................................................ 443 17.6.7. pinctrl bank 0 output en able register description ......... ........................................ 443 17.6.8. pinctrl bank 0 interrupt select register description ...... .......................................... 444 17.6.9. pinctrl bank 0 interrupt mask register description ......... ........................................ 445 17.6.10. pinctrl bank 0 interrupt level/edge regist er description ...................................... 446 17.6.11. pinctrl bank 0 interrupt polarity register description ............................................ 446 17.6.12. pinctrl bank 0 interrupt status register description .............................................. 447 17.6.13. pinctrl bank 1 lower pin mux select regi ster description ........ ............................ 448 17.6.14. pinctrl bank 1 upper pin mux select regi ster description ........ ............................ 448 17.6.15. pinctrl bank 1 drive str ength register description ....... ........................................ 449 17.6.16. pinctrl bank 1 data output register de scription ................................................... 450 17.6.17. pinctrl bank 1 data input register descr iption ...................................................... 451 17.6.18. pinctrl bank 1 output e nable register description ....... ............ ........... ........... ...... 452 17.6.19. pinctrl bank 1 interrupt select register description .............................................. 452 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 contents 11 17.6.20. pinctrl bank 1 interrupt mask register de scription ............................................... 453 17.6.21. pinctrl bank 1 interrupt level/edge regist er description ...................................... 454 17.6.22. pinctrl bank 1 interrupt polarity register description ............................................ 455 17.6.23. pinctrl bank 1 interrupt status register description .............................................. 456 17.6.24. pinctrl bank 2 lower pin mux select regi ster description ........ ............................ 456 17.6.25. pinctrl bank 2 upper pin mux select regi ster description ........ ............................ 457 17.6.26. pinctrl bank 2 drive str ength register description ....... ........................................ 458 17.6.27. pinctrl bank 2 data output register de scription ................................................... 459 17.6.28. pinctrl bank 2 data input register descr iption ...................................................... 459 17.6.29. pinctrl bank 2 output e nable register description ....... ............ ........... ........... ...... 460 17.6.30. pinctrl bank 2 interrupt select register description .............................................. 461 17.6.31. pinctrl bank 2 interrupt mask register de scription ............................................... 461 17.6.32. pinctrl bank 2 interrupt level/edge regist er description ...................................... 462 17.6.33. pinctrl bank 2 interrupt polarity register description ............................................ 463 17.6.34. pinctrl bank 2 interrupt status register description .............................................. 463 17.6.35. pinctrl bank 3 lower pin mux select regi ster description ........ ............................ 464 17.6.36. pinctrl bank 3 upper pin mux select regi ster description ........ ............................ 465 17.6.37. pinctrl bank 3 drive str ength register description ....... ........................................ 466 17.6.38. pinctrl bank 3 data output register de scription ................................................... 467 17.6.39. pinctrl bank 3 data input register descr iption ...................................................... 468 17.6.40. pinctrl bank 3 output e nable register description ....... ............ ........... ........... ...... 469 17.6.41. pinctrl bank 3 interrupt select register description .............................................. 469 17.6.42. pinctrl bank 3 interrupt mask register de scription ............................................... 470 17.6.43. pinctrl bank 3 interrupt level/edge regist er description ...................................... 471 17.6.44. pinctrl bank 3 interrupt polarity register description ............................................ 472 17.6.45. pinctrl bank 3 interrupt status register description .............................................. 473 18. timers and rotary decoder ........................................................................................... 475 18.1. overview ................................................................................................................ ..................... 475 18.2. timers .................................................................................................................. ....................... 476 18.2.1. using external signals as inputs .................................................................................. 477 18.2.2. timer 3 and duty cycle mode ................... .................................................................... 478 18.2.3. testing timer 3 duty cycle modes .............. ................................................................. 479 18.3. rotary decoder .......................................................................................................... ................. 480 18.3.1. testing the rotary decoder .......................................................................................... 48 2 18.3.2. behavior during reset ................................................................................................. .482 18.4. programmable registers .................................................................................................. .......... 483 18.4.1. rotary decoder control regi ster description ............................................................... 483 18.4.2. rotary decoder up/down c ounter register description ...... ........................................ 484 18.4.3. timer 0 control and status register descrip tion .......................................................... 485 18.4.4. timer 0 count register description .......... .................................................................... 487 18.4.5. timer 1 control and status register descrip tion .......................................................... 487 18.4.6. timer 1 count register description .......... .................................................................... 489 18.4.7. timer 2 control and status register descrip tion .......................................................... 490 18.4.8. timer 2 count register description .......... .................................................................... 491 18.4.9. timer 3 control and status register descrip tion .......................................................... 492 18.4.10. timer 3 count register description ........... ................................................................. 494 19. real-time clock, alarm, watchdog, and pe rsistent bits .................................. 497 19.1. overview ................................................................................................................ ..................... 497 19.2. real-time clock ......................................................................................................... ................ 502 19.2.1. behavior during reset ................................................................................................. .502 19.3. millisecond resolution timing facility ......... .............. .............. ........... ............ ........... ........... ...... 502 19.4. alarm clock ............................................................................................................. .................... 502 19.5. watchdog reset register ................................................................................................. .......... 503 19.6. laser fuse bits ......................................................................................................... .................. 503 19.7. programmable registers .................................................................................................. .......... 503 19.7.1. real-time clock control r egister description .................... .......................................... 503 19.7.2. real-time clock st atus register description ............... ................................................ 505 19.7.3. real-time clock millisecon ds counter description .............. ............ ........... ........... ...... 506 19.7.4. real-time clock seconds c ounter register description ...... ........................................ 507 19.7.5. real-time clock alarm register description ................................................................ 508 19.7.6. watchdog timer register de scription .......................................................................... 508 free datasheet http:/// STMP36XX official product documentation 5/3/06 12 contents 5-36xx-d1-1.02-050306 19.7.7. persistent state register 0 description ........................................................................ 509 19.7.8. persistent state register 1 description ........................................................................ 511 19.7.9. persistent state (on-chip ram configuration) regi ster 2 description ........................ 512 19.7.10. persistent state (on-chip ram configuration) regi ster 3 description ...................... 513 19.7.11. real-time clock debug register description .......... .............. .............. .............. ......... 513 19.7.12. rtc unlock register description ............................................................................... 514 19.7.13. hw laser fuse register 0 description ....................................................................... 515 19.7.14. hw laser fuse register 1 description ....................................................................... 516 19.7.15. hw laser fuse register 2 description ....................................................................... 516 19.7.16. hw laser fuse register 3 description ....................................................................... 517 19.7.17. hw laser fuse register 4 description ....................................................................... 517 19.7.18. hw laser fuse register 5 description ....................................................................... 518 19.7.19. hw laser fuse register 6 description ....................................................................... 518 19.7.20. hw laser fuse register 7 description ....................................................................... 519 19.7.21. hw laser fuse register 8 description ....................................................................... 520 19.7.22. hw laser fuse register 9 description ....................................................................... 520 19.7.23. hw laser fuse register 10 description . .................................................................... 521 19.7.24. hw laser fuse register 11 description . .................................................................... 521 20. pulse-width modulator (pwm ) controller ............................................................. 523 20.1. overview ................................................................................................................ ..................... 523 20.2. operation ............................................................................................................... ..................... 523 20.3. multi-chip attachment mode .............................................................................................. ......... 526 20.4. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 527 20.5. programmable registers .................................................................................................. .......... 527 20.5.1. pwm control and st atus register 0 description .......................................................... 527 20.5.2. pwm channel 0 active register description ................................................................ 528 20.5.3. pwm channel 0 period register description ............................................................... 529 20.5.4. pwm channel 1 active register description ................................................................ 530 20.5.5. pwm channel 1 period register description ............................................................... 531 20.5.6. pwm channel 2 active register description ................................................................ 532 20.5.7. pwm channel 2 period register description ............................................................... 533 20.5.8. pwm channel 3 active register description ................................................................ 534 20.5.9. pwm channel 3 period register description ............................................................... 535 20.5.10. pwm channel 4 active register description .............................................................. 536 20.5.11. pwm channel 4 period register description ............................................................. 537 21. i 2 c interface ................................................................................................................... ....... 539 21.1. overview ................................................................................................................ ..................... 539 21.2. i 2 c interface external pins ..................................................................................................... ..... 539 21.3. i 2 c interrupt sources ........................................................................................................... ....... 540 21.4. i 2 c bus protocol ................................................................................................................ ......... 542 21.4.1. simple device transactions ...................... .................................................................... 54 3 21.4.2. typical eeprom transactions ..................................................................................... 544 21.4.3. master mode protocol .................................................................................................. .545 21.4.4. slave mode protocol ................................................................................................... .. 549 21.5. programming examples .................................................................................................... .......... 552 21.5.1. five byte master write using dma ............................................................................... 552 21.5.2. reading 256 bytes from an eeprom .......................................................................... 553 21.6. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 555 21.7. programmable registers .................................................................................................. .......... 555 21.7.1. i2c control register 0 description ................................................................................ 555 21.7.2. i2c timing register 0 descr iption ................................................................................ 558 21.7.3. i2c timing register 1 descr iption ................................................................................ 558 21.7.4. i2c timing register 2 descr iption ................................................................................ 559 21.7.5. i2c control register 1 description ................................................................................ 560 21.7.6. i2c status register description .................................................................................... 563 21.7.7. i2c controller dma read a nd write data register descripti on ................................... 567 21.7.8. i2c device debug register 0 description . .................................................................... 567 21.7.9. i2c device debug register 1 description . .................................................................... 569 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 contents 13 22. application uart ........................................................................................................... ...... 571 22.1. overview ................................................................................................................ ..................... 571 22.2. operation ............................................................................................................... ..................... 572 22.2.1. fractional baud rate divider ........................................................................................ 57 2 22.2.2. uart character frame ................................................................................................ 57 3 22.2.3. dma operation ......................................................................................................... .... 573 22.2.4. data transmission or reception ................................................................................... 573 22.2.5. error bits ............................................................................................................ ........... 574 22.2.6. overrun bit ........................................................................................................... ......... 574 22.2.7. disabling the fifos ................................................................................................... ... 574 22.3. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 574 22.4. programmable registers .................................................................................................. .......... 575 22.4.1. uart receive dma control register description ........................................................ 575 22.4.2. uart transmit dma contro l register description ............. .......................................... 576 22.4.3. uart control register description .......... .................................................................... 577 22.4.4. uart line control register description ....................... ................................................ 580 22.4.5. uart interrupt register description ......... .................................................................... 581 22.4.6. uart data register description ................. ................................................................. 583 22.4.7. uart status register description ............ .................................................................... 584 22.4.8. uart debug register description .............. ................................................................. 586 23. debug uart ................................................................................................................. ............ 589 23.1. overview ................................................................................................................ ..................... 589 23.2. operation ............................................................................................................... ..................... 590 23.2.1. fractional baud rate divider ........................................................................................ 59 0 23.2.2. uart character frame ................................................................................................ 59 1 23.2.3. data transmission or reception ................................................................................... 591 23.2.4. error bits ............................................................................................................ ........... 592 23.2.5. overrun bit ........................................................................................................... ......... 592 23.3. disabling the fifos ..................................................................................................... ............... 592 23.4. programmable registers .................................................................................................. .......... 592 23.4.1. uart data register description ................. ................................................................. 592 23.4.2. uart receive status register (read) and error clear register (w rite) description .. 594 23.4.3. uart flag register description .................. ................................................................. 594 23.4.4. uart irda low-power counter register de scription .................................................. 595 23.4.5. uart integer baud rate divisor register description ......... ............ ........... ........... ...... 596 23.4.6. uart fractional baud rate divisor regist er description ............................................ 597 23.4.7. uart line control register , high byte description ..................................................... 597 23.4.8. uart control register description .......... .................................................................... 599 23.4.9. uart interrupt fifo level select register description ............................................... 600 23.4.10. uart interrupt mask set/cle ar register description ......... ........................................ 601 23.4.11. uart raw interrupt status register description ............. .......................................... 602 23.4.12. uart masked interrupt status register de scription .................................................. 603 23.4.13. uart interrupt clear regi ster description ....................... .......................................... 604 23.4.14. uart dma control register description ... ................................................................. 606 24. irda controller ............................................................................................................ ...... 607 24.1. overview ................................................................................................................ ..................... 607 24.2. operation ............................................................................................................... ..................... 608 24.2.1. dma operation ......................................................................................................... .... 608 24.2.2. ir transmit processing ................................................................................................ .608 24.2.3. ir receive processing ................................................................................................. .609 24.2.4. ir serial interface ................................................................................................... ...... 609 24.2.5. ir clock configuration ................................................................................................ .. 610 24.3. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 610 24.4. programmable registers .................................................................................................. .......... 611 24.4.1. ir control register description ............... ...................................................................... 61 1 24.4.2. ir transmit dma control re gister description ................... .......................................... 612 24.4.3. ir receive dma register description ...... .................................................................... 613 24.4.4. ir debug control register description ..... .................................................................... 614 24.4.5. ir interrupt register descr iption ................................................................................... 61 5 24.4.6. ir rx data register description ............. ...................................................................... 617 24.4.7. ir status register description ................ ...................................................................... 61 8 free datasheet http:/// STMP36XX official product documentation 5/3/06 14 contents 5-36xx-d1-1.02-050306 24.4.8. ir transceiver control register description ................................................................. 619 24.4.9. ir serial interface read data register description ...................................................... 620 24.4.10. ir debug register descripti on .................................................................................... 620 25. audioin/adc ................................................................................................................ ............. 623 25.1. overview ................................................................................................................ ..................... 623 25.2. operation ............................................................................................................... ..................... 625 25.2.1. audioin dma ........................................................................................................... ... 626 25.3. adc sample rate converter and internal operat ion ................................................................. 627 25.4. microphone .............................................................................................................. ................... 630 25.5. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 631 25.6. programmable registers .................................................................................................. .......... 631 25.6.1. audioin control register description ......................................................................... 631 25.6.2. audioin status register description ........................................................................... 634 25.6.3. audioin sample rate register description ................................................................ 634 25.6.4. audioin volume register description ......................................................................... 636 25.6.5. audioin debug register description ......... .............. .............. .............. .............. ......... 638 25.6.6. adc mux volume and select control register description .. ............ ........... ........... ...... 640 25.6.7. microphone and line control register description ............... ........................................ 641 25.6.8. analog clock control regist er description ......................... .......................................... 643 25.6.9. audioin read data register description ... .............. .............. .............. .............. ......... 644 26. audioout/dac ............................................................................................................... .......... 647 26.1. overview ................................................................................................................ ..................... 647 26.2. operation ............................................................................................................... ..................... 648 26.2.1. audioout dma .......................................................................................................... 649 26.3. dac sample rate converter and internal operat ion ................................................................. 650 26.4. reference control settings ....................... ....................................................................... ........... 653 26.5. headphone ............................................................................................................... .................. 654 26.5.1. board components ...................................................................................................... .656 26.5.2. capless mode operation .............................................................................................. 65 6 26.6. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 656 26.7. programmable registers .................................................................................................. .......... 657 26.7.1. audioout control register description .... ................................................................. 657 26.7.2. audioout status register description ....................................................................... 659 26.7.3. audioout sample rate register description ............................................................ 660 26.7.4. audioout volume register description .... ................................................................. 662 26.7.5. audioout debug register description ........ .............................................................. 664 26.7.6. headphone volume and select control regi ster description ........... ........... ........... ...... 665 26.7.7. speaker volume control register descripti on .............................................................. 666 26.7.8. audio power-down control r egister description .......................................................... 667 26.7.9. audioout reference control register descr iption .................................................... 668 26.7.10. miscellaneous audio controls register description ............ ........................................ 671 26.7.11. miscellaneous test audio co ntrols register description .... ........................................ 673 26.7.12. bist control and status r egister description ............................................................ 674 26.7.13. hardware bist status 0 register description ............................................................ 675 26.7.14. hardware audiout bist st atus 1 register description ... ........................................ 676 26.7.15. analog clock control register description ................................................................. 676 26.7.16. audioout write data regi ster description .............................................................. 677 27. spdif transmitter .......................................................................................................... ..... 679 27.1. overview ................................................................................................................ ..................... 679 27.2. interrupts .............................................................................................................. ....................... 682 27.3. clocking ................................................................................................................ ...................... 682 27.4. dma operation ........................................................................................................... ................ 683 27.5. pio debug mode of operation ............... .............. .............. .............. .............. ........... ........... ...... 684 27.6. programmable registers .................................................................................................. .......... 685 27.6.1. spdif control register description .............................................................................. 685 27.6.2. spdif status register description ............................................................................... 687 27.6.3. spdif frame control register description . ................................................................. 687 27.6.4. spdif sample rate register description ... ................................................................. 688 27.6.5. spdif debug register descr iption ......... .............. .............. .............. ........... ........... ...... 689 27.6.6. spdif write data register description .... .................................................................... 690 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 contents 15 28. digital radio interface (dri) ........................................................................................... 693 28.1. overview ................................................................................................................ ..................... 693 28.2. frame structure ......................................................................................................... ................. 694 28.3. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 696 28.4. programmable registers .................................................................................................. .......... 697 28.4.1. dri control register description .................................................................................. 697 28.4.2. dri timing register description ............... .................................................................... 699 28.4.3. dri status register description ............... .................................................................... 700 28.4.4. dri controlle r dma read data register description ................................................... 701 28.4.5. dri device debug register 0 description ... ................................................................. 702 28.4.6. dri device debug register 1 description ... ................................................................. 703 29. low-resolution adc and touch-screen interface .............................................. 705 29.1. overview ................................................................................................................ ..................... 705 29.2. scheduling conversions .................................................................................................. ........... 706 29.3. delay channels ..... .............. .............. .............. .............. ........... ........... ............ ........... ................. 708 29.4. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 709 29.5. programmable registers .................................................................................................. .......... 710 29.5.1. lradc control register 0 description ........ ................................................................. 710 29.5.2. lradc control register 1 description ........ ................................................................. 711 29.5.3. lradc control register 2 description ........ ................................................................. 714 29.5.4. lradc control register 3 description ........ ................................................................. 717 29.5.5. lradc status register descr iption ............................................................................. 719 29.5.6. lradc 0 result register description .......................................................................... 721 29.5.7. lradc 1 result register description .......................................................................... 722 29.5.8. lradc 2 result register description .......................................................................... 723 29.5.9. lradc 3 result register description .......................................................................... 724 29.5.10. lradc 4 result register description ....... ................................................................. 726 29.5.11. lradc 5 result register description ....... ................................................................. 727 29.5.12. lradc 6 (vddio) result register descripti on ........................................................... 728 29.5.13. lradc 7 (batt) result r egister description ............................................................ 729 29.5.14. lradc scheduling delay 0 register descripti on ....................................................... 731 29.5.15. lradc scheduling delay 1 register descripti on ....................................................... 732 29.5.16. lradc scheduling delay 2 register descripti on ....................................................... 734 29.5.17. lradc scheduling delay 3 register descripti on ....................................................... 735 29.5.18. lradc debug register 0 description .......... .............. .............. .............. .............. ...... 737 29.5.19. lradc debug register 1 description .......... .............. .............. .............. .............. ...... 738 29.5.20. lradc battery conversion register descrip tion ....................................................... 739 30. memory copy device ......................................................................................................... .. 741 30.1. overview ................................................................................................................ ..................... 741 30.2. programming examples .................................................................................................... .......... 742 30.2.1. block copy ............................................................................................................ ........ 742 30.2.2. rom dot data copying and bss fill .............. .............. .............. .............. .............. ...... 743 30.3. behavior during reset ........ .............. .............. .............. .............. .............. ........... .......... ............. 744 30.4. programmable registers .................................................................................................. .......... 744 30.4.1. memory copy device control and status re gister description ........ ............................ 744 30.4.2. memcpy device dma read and write data register description .............................. 745 30.4.3. memcpy device debug register description .............. .............. .............. .............. ...... 746 31. power supply ............................................................................................................... ......... 747 31.1. overview ................................................................................................................ ..................... 747 31.2. dc-dc converters ........................................................................................................ .............. 748 31.2.1. dc-dc operating modes .............................................................................................. 748 31.2.2. dc-dc operation ....................................................................................................... ... 749 31.3. linear regulators ....................................................................................................... ................. 752 31.3.1. usb compliance features ............................................................................................ 752 31.3.2. 5v to battery power intera ction .................................................................................... 753 31.3.3. power-up sequence ........... .............. .............. .............. .............. ........... ............ ........... 754 31.3.4. power-down sequence ................................................................................................ 754 31.3.5. reset sequence ........................................................................................................ .... 755 31.3.6. power up, power down, and reset flow char t ........................................................... 756 31.4. pswitch pin functions ................................................................................................... .......... 757 free datasheet http:/// STMP36XX official product documentation 5/3/06 16 contents 5-36xx-d1-1.02-050306 31.4.1. power on .............................................................................................................. ........ 757 31.4.2. power down ............................................................................................................ ...... 757 31.4.3. software functions/recovery mode ............................................................................. 757 31.5. battery monitor ......................................................................................................... ................... 757 31.6. battery charger ......................................................................................................... .................. 758 31.7. silicon speed sensor .......... .............. .............. .............. .............. ........... ........... ............ .............. 759 31.8. dc-dc programmable registers ............................................................................................ .... 759 31.8.1. power control register descr iption .............................................................................. 759 31.8.2. dc-dc 5v control re gister description ....................................................................... 760 31.8.3. dc-dc minimum power and miscellaneous cont rol register descripti on ................... 763 31.8.4. battery charge control regi ster description ................................................................ 765 31.8.5. vddd and vddio supply targets and brownou ts control register description ......... 766 31.8.6. dc-dc#1 multioutput conver ter modes control register description ......................... 768 31.8.7. dc-dc#1 duty cycle limits control register description .... ........................................ 770 31.8.8. dc-dc#2 duty cycle limits control register description .... ........................................ 770 31.8.9. converter loop behavior control register de scription ........ ............ ........... ........... ...... 771 31.8.10. power subsystem st atus register description ........................................................... 773 31.8.11. temperature and transisto r speed control and status register description ........... 775 31.8.12. battery level monitor register description ................................................................. 777 31.8.13. power module reset register description ................................................................. 778 31.8.14. power module debug register description ................................................................ 779 31.9. dc-dc converter efficiency .............................................................................................. ......... 780 31.9.1. dc-dc1 mode 3 efficiency ........................................................................................... 780 31.9.2. dc-dc1 mode 1 efficiency ........................................................................................... 781 31.9.3. dc-dc1 mode 2/mode 0 efficiency ............. ................................................................. 783 31.9.4. dc-dc2 mode 2 efficiency ........................................................................................... 783 31.9.5. dc-dc2 mode 0 efficiency ........................................................................................... 784 31.9.6. max power out in boost mo des .................................................................................... 785 31.9.7. max power out in buck mode s ..................................................................................... 786 32. boot modes ................................................................................................................. ........... 787 32.1. overview ................................................................................................................ ..................... 787 32.2. mode selection .......................................................................................................... ................. 787 32.2.1. boot pins and boot modes ............................................................................................ 78 7 32.3. boot loader ............................................................................................................. ................... 790 32.3.1. transition from boot loader to runtime image ............................................................ 790 32.3.2. constructing image to be loaded by boot loader ............... ............ ........... ........... ...... 791 32.3.3. on-chip ram used by boot loader ............ .............. .............. .............. .............. ......... 792 32.4. preparing bootable images ............................................................................................... ......... 792 32.4.1. i 2 c eeprom boot mode .............................................................................................. 792 32.4.2. regular nor boot mode .............................................................................................. 792 32.4.3. stmp (usb recovery) boot mode .............. .............. .............. .............. .............. ......... 792 32.4.4. ata hard disk drive boot mode ................................................................................... 792 32.4.5. large-block nand boot mode .................... ................................................................. 794 33. register macro usage ...................................................................................................... 8 01 33.1. definitions ............................................................................................................. ...................... 801 33.2. background .............................................................................................................. ................... 801 33.3. naming convention ....................................................................................................... ............. 802 33.4. examples ................................................................................................................ .................... 803 33.4.1. setting 1-bit wide field .............................................................................................. ... 803 33.4.2. clearing 1-bit wide field ............................................................................................. .803 33.4.3. toggling 1-bit wide field ............................................................................................. .804 33.4.4. modifying n-bit wide field ............................................................................................ 804 33.4.5. modifying multiple fields ...................... ....................................................................... .. 804 33.4.6. writing entire register (a ll fields updated at once) ....... ............................................. 804 33.4.7. reading a bit field ................................................................................................... ..... 804 33.4.8. reading entire register ............................................................................................... .805 33.4.9. accessing multiple instance register ........................................................................... 805 33.4.10. correct way to soft reset a block .......... .................................................................... 805 33.5. summary preferred ....................................................................................................... .............. 805 33.6. summary alternate syntax .......................... ...................................................................... ......... 806 33.7. assembly example ........................................................................................................ ............. 806 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 contents 17 34. memory map ................................................................................................................. ........... 807 35. pin descriptions ........................................................................................................... ........ 809 35.1. pin placement and definitions ..................... ...................................................................... ......... 809 35.1.1. pin definitions for 100-pin tqfp package .. ................................................................. 810 35.1.2. pin definitions for 169-pin bga package .... ................................................................. 814 35.2. functional pin groups ........... .............. .............. .............. .............. ........... ........... .......... ............. 823 35.2.1. analog pins ........................................................................................................... ........ 823 35.2.2. dc-dc converter pins .................................................................................................. 824 35.2.3. general-purpose media interface (gpmi) pins ............................................................ 825 35.2.4. synchronous serial port (ssp) pins ......... .............. .............. ............ ........... ........... ...... 827 35.2.5. application and debug uart pins .............. .............. .............. .............. .............. ......... 827 35.2.6. external memory interface (sdram/nor) pi ns ........................................................... 828 35.2.7. i 2 c interface pins .......................................................................................................... 831 35.2.8. digital radio interface (dri) pins ............. .................................................................... 831 35.2.9. lcd interface (lcdif) pins .......................................................................................... 83 1 35.2.10. power pins ........................................................................................................... ....... 833 35.2.11. system pins .......................................................................................................... ...... 833 35.2.12. timer and pwm pins .................................................................................................. 8 34 35.2.13. usb pins ............................................................................................................. ........ 835 35.2.14. general-purpose input/output (gpio) pins ................................................................ 835 36. package drawings ........................................................................................................... ... 843 36.1. 100-pin tqfp ....... .............. .............. .............. .............. ........... ........... ............ ........... ................. 843 36.2. 169-pin fpbga ......... .............. .............. .............. .............. .............. .............. .............. ................. 844 37. STMP36XX part numbers and ordering info rmation ............................................ 845 appendix:acronyms and abbreviations ........................................................................... 847 index: register names ......................................................................................................... ..... 851 free datasheet http:/// STMP36XX official product documentation 5/3/06 18 list of figures 5-36xx-d1-1.02-050306 list of figures figure 1. system block diagram ................................................................................................. ............. 26 figure 2. chip package photographs ............. .............. .............. .............. .............. .............. .......... ......... 26 figure 3. STMP36XX soc block diagram ........................................................................................... .... 28 figure 4. memory map for d-ahb devi ces ......................................................................................... ..... 29 figure 5. clock diagram ........................................................................................................ ................... 32 figure 6. mixed signal audio elements .......................................................................................... ......... 36 figure 7. arm926 risc processor core ................... ........................................................................ ...... 44 figure 8. arm programmable registers ........................................................................................... ...... 45 figure 9. STMP36XX clock tree .................................................................................................. ............ 50 figure 10. detail diagram of key cl ocks .......... .............. .............. .............. .............. ........... ........... ........... 51 figure 11. pll block diagram ................................................................................................... ................ 52 figure 12. usb 2.0 phy startup flowchart ....................................................................................... ........ 54 figure 13. usb 2.0 phy pll suspend flowchart ............. ...................................................................... .. 55 figure 14. interrupt collector diagram for irq generation ...................................................................... .. 69 figure 15. interrupt collector bit ?37? logic .................................................................................. ............. 70 figure 16. irq control flow .................................................................................................... ................... 71 figure 17. nesting of multi-level irq interrupts ............................................................................... ......... 72 figure 18. fiq generation logic ................................................................................................ ................ 74 figure 19. default first-level page table (dflpt) blo ck diagram ........................................................ 115 figure 20. digital control (digctl) block diagram ..... ......................................................................... ... 123 figure 21. on-chip ram partitioning ..................... ....................................................................... ........... 124 figure 22. on-chip ram e_fuse control .................... ...................................................................... ...... 125 figure 23. usb 2.0 device controller block diagram ..... ........................................................................ .156 figure 24. usb 2.0 check_usb_plugged_in flowchart ........ .............. .............. .............. .............. ......... 158 figure 25. usb 2.0 usb phy startup flowchart ............ ....................................................................... .. 159 figure 26. usb 2.0 phy pll suspend flowchart ............. ...................................................................... 160 figure 27. utmi powerdown ...................................................................................................... .............. 160 figure 28. usb 2.0 phy block diagram ........................................................................................... ....... 161 figure 29. usb 2.0 phy analog transceiver block diagram .................................................................. 163 figure 30. usb 2.0 phy transmitter block diagram ............................................................................... 166 figure 31. 45 ? calibration flowchart ...................................................................................................... 16 8 figure 32. ahb-to-apbh bridge dma block diagram ....... ...................................................................... 185 figure 33. ahb-to-apbh bridge dma channel command stru cture ......... .............. .............. ........... ...... 187 figure 34. ahb-to-apbh bridge dma hwecc example co mmand chain ............................................ 191 figure 35. ahb-to-apbh bridge dma nand read status polling with dma sense command ............ 192 figure 36. ahb-to-apb bridge device interface .................................................................................. .... 193 figure 37. ahb-to-apbx bridge dma blo ck diagram ......... .............. .............. ............ ........... ........... ...... 257 figure 38. ahb-to-apbx bridge dma channel command st ructure .............. ............ ........... ........... ...... 259 figure 39. ahb-to-apbx bridge dma audioout (dac) exampl e command chain .... .............. ......... 262 figure 40. external memory interface block diagram ..... ........................................................................ .326 figure 41. sdram programmable timing parameters ....... .................................................................... 327 figure 42. general-purpose media interface controller bl ock diagram .................................................. 342 figure 43. ata pio timing mode ................................................................................................. ........... 343 figure 44. udma timing ......................................................................................................... ................. 344 figure 45. ata command/irq/c heck status example ........................................................................... 344 figure 46. basic nand timing ............ .............. .............. .............. ........... ........... ........... ............ ........... 346 figure 47. nand command and address timing example ... ................................................................. 346 figure 48. gpmi nand read path timi ng ............... .............. .............. .............. ........... ............ .......... .... 347 figure 49. hardware ecc accelerator block diagram ...... ...................................................................... 36 1 figure 50. hardware ecc reed-solomon block coding?e ncoder ........... .............. .............. ........... ...... 363 figure 51. hardware ecc reed-solomon encode flowchart ................................................................. 364 figure 52. hardware ecc reed-solomon encode dma chai n .............................................................. 365 figure 53. hardware ecc reed-solomon decode flowchart .............. .............. .............. .............. ......... 367 figure 54. hardware ecc reed-solomon block coding?d ecoder phase 1 ......................................... 368 figure 55. hardware ecc reed-solomon block decode dma chain .................................................... 369 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 list of figures 19 figure 56. synchronous serial port block diagram ..... .......................................................................... .. 383 figure 57. motorola spi frame format (single transfer) with polarity=0 and phase=0 ................. 386 figure 58. motorola spi frame form at (continuous transfer) with po larity=0 and phase=0 ......... 386 figure 59. motorola spi frame form at (continuous transfer) with po larity=0 and phase=1 ......... 387 figure 60. motorola spi frame format (single transfer) with polarity=1 and phase=0 ................. 388 figure 61. motorola spi frame form at (continuous transfer) with po larity=1 and phase=0 ......... 388 figure 62. motorola spi frame format with polarity=1 and phase=1 ............................................. 389 figure 63. texas instruments synchronous serial fram e format (single transfer) ... ............................ 390 figure 64. texas instruments synchronous serial fram e format (continuous transf er) ....................... 391 figure 65. microwire frame format (single transfer) ............................................................................ .391 figure 66. microwire frame format (continuous transfer) . .................................................................... 392 figure 67. microwire frame format (continuous transfer) . .................................................................... 393 figure 68. sd/mmc block transfer flowchart ............. ........................................................................ .... 396 figure 69. basic ms protocols .................................................................................................. ............... 399 figure 70. ms operation flowchart .............................................................................................. ........... 400 figure 71. ms four-state read and wr ite ............. .............. .............. .............. ............ ........... .......... ....... 401 figure 72. lcd interface block diagram ................... ...................................................................... ......... 419 figure 73. lcdif timing (command cycl e) ........................................................................................ .... 422 figure 74. pin control mux chart (banks 0 and 1) ...... ......................................................................... ... 432 figure 75. pin control mux chart (banks 2 and 3) ...... ......................................................................... ... 433 figure 76. gpio output setup flowchart ......................................................................................... ....... 435 figure 77. gpio input setup flowchart .......................................................................................... ......... 436 figure 78. gpio interrupt flowchart ............................................................................................ ............ 437 figure 79. gpio interrupt generation .................... ....................................................................... ........... 438 figure 80. timers and rotary decoder block diagram ...... ...................................................................... 4 75 figure 81. timer 0, timer 1, or timer 2 detail ................................................................................. ........ 476 figure 82. timer 3 detail ...................................................................................................... .................... 478 figure 83. pulse-width measurement mo de ........................................................................................ .... 479 figure 84. detail of rotary decoder ............................................................................................ ............. 480 figure 85. rotary decoding mode?debouncing rotary a and b inputs ........ ............ ........... ........... ...... 481 figure 86. rotary decoding mode?input transitions ............................................................................. 4 82 figure 87. rtc, watchdog, alarm, and persistent bits block diagram ................................................... 498 figure 88. rtc initialization sequence ......................................................................................... ........... 499 figure 89. analog/digital interface timing ..................................................................................... .......... 500 figure 90. rtc writing to a master register from cpu .......................................................................... 5 01 figure 91. pulse-width modulation controller (pwm) blo ck diagram ..................................................... 524 figure 92. pwm output example .................................................................................................. ........... 525 figure 93. pwm differential output pair example ................................................................................ ... 526 figure 94. pwm output driver ................................................................................................... .............. 527 figure 94. pwm output driver ................................................................................................... .............. 527 figure 95. i 2 c interface block diagram .................................................................................................... 5 40 figure 96. i 2 c data and clock timing ......... ............................................................................................. 5 42 figure 97. i 2 c data and clock timing generati on ................................................................................... 543 figure 98. i 2 c master mode flow chart?initial states .......... ................................................................. 546 figure 99. i 2 c master mode flow chart?receive states ...... ................................................................. 547 figure 100. i 2 c master mode flow chart?transmit states ........ .............................................................. 548 figure 101. i 2 c master mode flow chart?send stop states ..... .............................................................. 549 figure 102. i 2 c slave mode flow chart ........... .......................................................................................... 55 1 figure 103. i 2 c writing five bytes .......................................................................................................... ... 552 figure 104. i 2 c reading 256 bytes from an eeprom ................ .............................................................. 553 figure 105. application uart block diagram ..................................................................................... ...... 572 figure 106. application uart character frame ............ ....................................................................... ..... 573 figure 107. debug uart block diagram ........................................................................................... ....... 590 figure 108. debug uart character frame ......................................................................................... ...... 591 figure 109. irda controller block diagram ...................................................................................... .......... 607 figure 110. example of 1-byte serial interface write co mmand ............................................................... 610 figure 111. mixed signal audio elements ........................................................................................ ......... 624 free datasheet http:/// STMP36XX official product documentation 5/3/06 20 list of figures 5-36xx-d1-1.02-050306 figure 112. audioin/adc block diagram .......................................................................................... ...... 625 figure 113. variable-rate a/d converter ................... ..................................................................... .......... 629 figure 114. external microphone bias generation ........... .............. .............. .............. .............. ............. .... 630 figure 115. internal microphone bias generation ....... ......................................................................... ...... 631 figure 116. audioout/dac block diagram ......................................................................................... ... 648 figure 117. stereo sigma delta d/a converter ................................................................................... ...... 652 figure 118. conventional stereo headphone application cir cuit .............................................................. 654 figure 119. stereo headphone application circuit with co mmon node .......... .............. ........... ........... ...... 654 figure 120. stereo headphone common short detection and powerdown circuit ....... ........... ........... ...... 655 figure 121. stereo headphone l/r/ short detection and po werdown circuit ............ .............. ........... ...... 655 figure 122. spdif transmitter block diagram .............. ...................................................................... ...... 680 figure 123. spdif flow chart ................................................................................................... ................ 681 figure 124. spdif dma two-block transmit example ....... ...................................................................... 68 3 figure 125. digital radio interface (dri) block diagram ........................................................................ ... 693 figure 126. dri synchronization and data recovery .............................................................................. .. 694 figure 127. digital radio interface (dri) framing .............................................................................. ....... 694 figure 128. digital radio interface (dri) digital signals into analog line-in ............................................ 696 figure 129. low-resolution adc and touch-screen interfac e block diagram ............. ........... ........... ...... 705 figure 130. low-resolution adc successive approximation un it ............................................................ 707 figure 131. using delay channels to oversample a touch- screen ............. .............. .............. ........... ...... 709 figure 132. memory copy device block diagram ......... .......................................................................... .. 741 figure 133. power supply block diagr am ......................................................................................... ......... 748 figure 134. brownout detection flowchart ....................................................................................... ......... 751 figure 135. power up, power down, and reset flow chart ..................................................................... 756 figure 136. efficiency of dc-dc #1 in mode 3 for various vddd loads ........ .............. ........... ........... ...... 780 figure 137. efficiency of dc-dc #1 in mode 3 for various vddio loads ................................................. 781 figure 138. efficiency of dc-dc #1 in mode 1 for various vddd loads ........ .............. ........... ........... ...... 782 figure 139. efficiency of dc-dc #1 in mode 1 for various vddio loads ................................................. 782 figure 140. efficiency of dc-dc #1 in mode 2/mode 0 fo r various vddd loads ......... ........... ........... ...... 783 figure 141. efficiency of dc-dc #2 in mode 2 for various current loads ................................................ 784 figure 142. efficiency of dc-dc #2 in mode 0 for various current loads ................................................ 785 figure 143. 785 figure 144. creating a boot loader image ................. .............. .............. .............. .............. .............. ......... 791 figure 145. ata media layout ................................................................................................... ................ 793 figure 146. lb nand with generalized page layout detail ........................ ............................................. 794 figure 147. ecc coverage for nand pages ................... ..................................................................... .... 795 figure 148. lb nand with specialized bc b page layout detail ................. ............................................. 797 figure 149. data organization in multiple nands ...... .......................................................................... ..... 800 figure 150. chip package photographs ............. .............. .............. .............. .............. ........... ........... ......... 809 figure 151. 100-pin tqfp package drawing ....................................................................................... ..... 843 figure 152. 169-pin fpbga package drawing ...................................................................................... ..... 844 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 revision history 21 revision history revision description 1.02 entered changes to close the following clearq uest stmp defect entries (stmp000nnnnn): 08170, 10337, 10513, 10545, 10550, 10614, 10630, 10902, 10903, 10907, 10917, 10920, 10921, 11001, 11005, 11011, 11088, 11089, 11131 ? updated descriptions in the four pers istent registers, beginning on page 509 , to clarify bit allocation and usage by the rom, the sdk, sigmatel, and the customer. (cq08170) ? updated description of rst_all and rst_dig bit fields in table 998, ?hw_power_reset bit field descriptions,? on page 778 . updated description of pwdn_5vbrnout bit field in ta b l e 9 7 6 , ?hw_power_5vctrl bit field descriptions,? on page 761 . (cq10337) ? updated description of vdd_trg and vddio_trg bit fields in table 982, ?hw_power_vddctrl bit field descriptions,? on page 767 . (cq10513) ? updated dri_clk information in section 28.2 , ?frame structure? on page 694 . (cq10545) ? removed 4.1-v option from batt_charge bit description in table 980, ?hw_power_battchrg bit field descriptions,? on page 766 and section 31.6 , ?battery charger? on page 758 . (cq10614) ? updated section 9.4.2.6 , ?resistor calibration mode? on page 167 , and figure 31 , ?45w calibration flowchart? on page 168 . updated txencal45dp, txencal45dn, and txcalibrate bit fields in table 185, ?hw_usbphy_tx bit field descriptions,? on page 171 . (cq10630) ? corrected value in table 972, ?dc-dc battery modes,? on page 749 for dc-dc mode 2 resistor. (cq10902) ? added section 13.3.5 , ?nand read timing? on page 346 . (cq10903) ? added uart and irda pio word mapping information to section 11.2 , ?apbx dma? on page 258 , section 22.2.3 , ?dma operation? on page 573 , and section 24.2.1 , ?dma operation? on page 608 . (cq10907) ? updated section 25.3 , ?adc sample rate converter and internal operation? on page 627 and the example in ?audioin sample rate register description? on page 634 . (cq10917) ? on the cover page, reinstated the usb hi-speed certification logo, which had been removed in error. (cq10920) ? added table 5, ?pll voltage requirements,? on page 41 . updated description of pllv2isel bit field in table 12, ?hw_clkctrl_pllctrl0 bit field descriptions,? on page 56 . (cq10921) ? updated section 8.4 , ?usb dma interface? on page 157 for on-chip ram and sdram requirements. (cq11001) ? added table 7, ?recommended operating conditions for specific emiclk targets,? on page 42 . (cq11005) ? updated table 4, ?recommended operating conditions for specific cpuclk targets,? on page 41 with new values. (cq11011) ? updated figure 1 , ?system block diagram? on page 26 to show correct linein and microphone amplifier connections. (cq11088) ? updated section 29.1 on page 705 with lradc absolute accuracy value. (cq11089) ? updated section 29.1 on page 705 about using an external thermi stor for temperature sensing. (cq11131) free datasheet http:/// STMP36XX official product documentation 5/3/06 22 revision history 5-36xx-d1-1.02-050306 1.01 updated ?recommended operating conditions for specific clock targets? for vddd requirements. reorganized ?recommended operating conditions for specific hclk targets? and ?recommended operating conditions for specific cpuclk targets? for consistency. added tbd values for maximum cpuclk targets from 0 to 85 mhz. added typical power dissipation value to ?dc characteristics?. entered changes to close the following clearques t stmp defect entries (stmp000nnnnn): 10137, 10138, 10139, 10180 ? updated description of pllv2isel bit field in ?hw_clkctrl_pllctrl0 bit field descriptions?. (cq10137) ? updated description of tran_nohyst in ?hw_power_loopctrl bit field descriptions? and ?dc-dc extended battery li fe features?. (cq10138) ? updated ?arm 926 processor core? to add little endian information. (cq10139) ? added figures and text to ?audioin/adc? to de scribe the microphone. added figures and text to ?audioout/dac? to describe the headphones. (cq10180) 1.00 initial public release. revision description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 1: product overview 23 1. product overview the STMP36XX is sigmatel?s fourth- generation single-chip digital media soc for applications such as digi- tal audio players, pdas, voice recorders, cell ph ones, portable video players, and digital photo wallets. this chapter provides an general overview of th e product and describes hardware features, application capability, design support, and additional documentation. a system block diagram ( figure 1 ), chip block diagram ( figure 3 ), clock overview diagram ( figure 5 ), and mixed signal audio diagram ( figure 6 ) are also provided in this chapter. 1.1. hardware features ? arm926 cpu running at up to 200 mhz ? integrated arm926ej-s cpu ? 8kb + 8kb caches ? arm embedded trace macrocell (etm) version 9-medium ? 256kb of integrated low-power on-chip ram ? universal serial bus (usb) high-speed on-the-go (otg)?up to 480mb/s ? high-speed usb device and host functions ? fully integrated high-speed otg physical layer protocol (phy) ? complete otg support ? power management unit ? multi-channel dc-dc converter supports all common battery configurations ? features multi-channel boost, du al-output buck and buck/boost modes ? pfm mode for low standby power ? improved, high-current battery charger for lithium ion (li-ion) and nickel metal hydride (nimh) batteries ? direct power from 5-v source (usb, wall power, or other source) ? can generate 5v from li-ion battery for usb otg and other applications ? can generate 3.3v for hard drive ? silicon speed and temperature sensors enable adaptive power management over temperature and silicon process ? optimized for very long battery life ? 50 mw system power consumption whil e playing 128-kbps mp3 from sdram ? audio codec ? stereo dac 99db snr ? stereo adc with 90db snr ? stereo headphone amplifier with direct drive to eliminate bulky capacitors ? mono speaker amplifier with direct drive ? amplifiers are designed for click/pop free operation and have short-circuit protection ? two stereo line inputs ? microphone input ? spdif digital out ? 8-channel a/d converter ? 6 external channels, 2 internal channels ? resistive touch screen controller ? temperature sensor controller free datasheet http:/// STMP36XX official product documentation 5/3/06 24 chapter 1: product overview 5-36xx-d1-1.02-050306 ? security features ? read-only unique id for digital rights management algorithms ? secure boot ? external memory interface (emi) ? provides memory-mapped (load/store) access to external memories ? sdram ? nor flash ? wide assortment of external media interfaces ? ata hard drive ? up to four nand flash with hardware management of device interleaving ? high-speed mmc, secure digital, compact flash, ms ? hardware reed-solomon error correction code (ecc) engine offers industry-leading protection and performance for nand ? dual peripheral bus bri dges with 16 dma channels ? multiple peripheral clock domains save power while optimizing performance ? direct memory access (dma) with sophisticated linked dma command architecture saves power and off loads the cpu ? liquid crystal display (lcd) interface works with all standard lcd modules ? 8- or 16-bit bus ? two universal asynchronous receiver-transmitters (uarts) ? high-speed uart operates up to 1.5 mb/s ? i 2 c master/slave ? dma control of an entire eeprom or other device read/write transaction without cpu in tervention ? synchronous serial port (for spi, microwire, mmc, sdio, ms) ? four-channel 16-bit timer with rotary decoder ? five-channel pulse width modulator (pwm) ? real-time clock ? alarm clock can turn the system on ? uses the existing 24-mhz xtal for low cost or 32.76-khz for low power ? spdif transmit ? flexible i/o pins ? all digital pins have drive strength (4ma, 8ma) controls ? almost all digital pins have general-purpose input/output (gpio) mode ? offered in 100-pin thin quad flat pack (tqf p) and 169-pin ball grid array (bga) packages 1.2. application capability ? multi-format compressed audio encode and decode ? digital rights management (drm) ? microsoft pddrm (portable device digital rights management/drm9) ? wmdrm10 (windows media digital rights management 10/janus) free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 1: product overview 25 ? voice record in adpcm or nearly any other format ? graphical equalizer ? sound effects and spatialization ? jpeg image decode and encode ? simultaneous jpeg decoding and compressed audio playback ? video decoder capability ? multi-format compressed video decode ? flexible usb connectivity ? mass storage device ? media transfer protocol device ? also supports proprietary usb device drivers ? mass storage host ? usb otg with mass storage, mtp or ptp ? field-upgradeable firmware ? upgradeable to future compressed audio and video codecs via software ? ready for wi-fi 802.11a/b/g using sdio ? ready for bluetooth using sdio or uart 1.3. design support ? green hills integrated development environment, software development kit (sdk), and debugger ? optional real-time trace port ? application notes, reference schematics, sample pcb layouts are available 1.4. additional documentation additional documentation and information is avai lable from sigmatel, in cluding the following: ? extensive software development kit (sdk) with peripheral device files ? application notes ? reference schematics ? sample printed circuit board (pcb) layouts ? sample bill of materials sigmatel specifically refers the reader to the peripheral device include files from the sdk. these files pro- vide constant declarations for address offsets to the registers defined in this document. note that the name of each programmable register defined in this datasheet corresponds to a c language #define or assembly language equate of the exact same name. these files also c ontain declarations that allow symbolic access to individual bit fields within the registers. user programs can include all of these peripheral include files by simply including the file hw_equ.inc into the assembly files and hw_equ.h into the c files. free datasheet http:/// STMP36XX official product documentation 5/3/06 26 chapter 1: product overview 5-36xx-d1-1.02-050306 1.5. STMP36XX system block diagram figure 1 shows a block diagram of a typical system based on the STMP36XX. figure 2 shows photographs of the two different chip packages. headphone amplifier general purpose input/output dsp on-chip rom 8k x 24bits on-chip ram 96k x 24bits cd control interface spi interface emc sdram interface headphone amplifier 32-bit risc core on-chip rom 16k x 32bits on-chip ram 64k x 32bits lcd interface ssp interface media interface sdram/nor interface STMP36XX peripheral amba ahb dcdc converter low resoluti on adc pll xtal low- resolution adc x8 battery charger dual xtal, rtc, alarm mic in linein 1 / fm dac adc dac adc nor flash sdram ata hdd nand flash mlc flash compact flash mmc/spi sd/sdio wifi/bluetooth ms fm tuner eeprom usb high-speed otg usb full-speed otg microphone stfm1000 fm radio headphones rechargable battery 24.0-mhz crystal ui: led/ switches dcdc converter dc-dc converters usb ecc engine i2c interface i 2 c interface i2c interface gpio interface temperature 5v input capless direct-drive spi interface pulse width backlight usb usb 2.0 otg device/host usb usb phy (hs/fs otg) lcd i2c interface spdif xmit 8k i$ 8k d$ dac amp ui: buttons, touch-screen pll and clkgen interrupt control, timers, 16xdmas, jtag, trace spdif xmit i2c interface rotary decoder i2c interface irda-vfir ui: rotary peer-to-peer 3.3v to hard drive 32768-hz crystal speaker amp 2x uarts i/o pin multiplexer host, debug linein 2 90 94 98 102 106 figure 1. system block diagram figure 2. chip package photographs note: for additional package measurements, see chapter 36 , ?package drawings? on page 843 . 100 tqfp 169 fpbga 14 x 14 mm 11 x 11 mm pin 1 pin a1 pin a1 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 1: product overview 27 1.6. STMP36XX product features the STMP36XX is sigmatel?s fourth generation single-chip digital media system for applications such as digital audio player s, pdas, voice recorders, cell phones, por- table video players, and digital photo walle ts. the STMP36XX offers long battery life, minimal external components, high processing performance, and excellent software development and debug support. the STMP36XX features low power consumption to enable long battery life in porta- ble applications. the integrated power ma nagement unit includes a high efficiency, on-chip dc-dc converter that supports many different battery configurations includ- ing 1xaa, 1xaaa, 2xaa, 2xaaa and li-i on. the powe r management unit also includes an intelligent batt ery charger for li-ion cells and is designed to support adaptive voltage control (avc), which can reduce system power consumption by half. avc also allows the chip to operate at a higher peak cpu operating frequency than typical voltag e control systems. to provide the maximum app lication flexibility, the STMP36XX integrates a wide range of i/o ports. it can efficiently interf ace to nearly any type of flash memory, ata drive, serial bus, or lcd. it is also r eady for advanced connectivity applications such as bluetooth and wifi via its integrated 4-bit sdio controller and high-speed uart. as with previous stmp3xxx products, the STMP36XX integrates the entire suite of analog components needed for a portable audio player. this includes a high-resolu- tion audio codec with headphone and speaker amplifiers, 8-channel 12-bit adc, high-current battery charger, linear regulators for 5-v operation, high-speed usb otg phy, and various system moni toring and infrastructure systems. an arm 926 ej-s cpu with 256 kbytes of on-chip sram and an integrated mem- ory management unit provides the processing power needed to support advanced features such as audio cross-fading, as well as still and motion video decoding. these and other advanced features are int egrated into software development kits that support the STMP36XX. contact your local sigmatel representative or visit the sigmatel extranet at: http:/ /extranet.sigmatel.com for more information on the soft- ware development kits available for the STMP36XX. 1.6.1. arm 926 processor core the on-chip risc processor core is an arm, ltd. 926ej-s. this cpu implements the arm v5te instruction set architectu re. the arm9ej-s has two instructions sets, a 32-bit instruction set used in the arm state and a 16-bit instruction set used in thumb state. the core offers the choice of running in the arm state or the thumb state or a mix of the two. this enables opt imization for both code density and perfor- mance. arm studies indicate that thumb co de is typically 65% the size of equiva- lent arm code, while providing 160% of the effective performance in constrained memory bandwidth applications . the arm cpu is described in chapter 3 , ?arm cpu complex? on page 43 . the arm risc cpu is the central cont roller for the entire STMP36XX soc, as shown in figure 3 . the arm 926 core includes two ahb masters. one is used for instruction fetches while the other is used fo r data load/stores, page table accesses, dma traffic, etc. the ahb has three othe r bus masters, the arm core i and d mas- ters, the usb master, and an ahb-to-apbh bridge dma master, and an ahb-to- apbx bridge dma master. the ahb has six slaves: the usb slave, the on-chip ram, the on-chip rom, the ex ternal memory interface (sdram), default first-level page table, and the two apb bridges. free datasheet http:/// STMP36XX official product documentation 5/3/06 28 chapter 1: product overview 5-36xx-d1-1.02-050306 execution always begins in on-chip rom after reset, unless over-ridden by the debugger. there is a 2-kbyte lock out re gion (rom shield) within the on-chip rom. this region is not visible when the jtag debugger is attached. it is further disabled by a write-once bit in the digital control bl ock. when written by instructions in the rom boot loader, this feature enables the expansion of a trust zone to a certified boot manager software loaded by the rom. a number of devices are programmed only at initialization or application state change, such as dc-dc converter voltages, clock generator settings, etc. certain other devices either operate in the crystal clock domain or have significant portions that operate in the crystal clock domain, e.g., adc, dac, pll, etc. these devices operate on a slower speed asynchronous peripheral bus. write posting in the arm dma control arm 926ej-s ahb-d m,s ahb 256 kb sram external memory interface (emi) s s m usb otg + phy m,s ahb-to-apbx bridge/dma ecc synchronous serial port i 2 c m/s audio in spdif tx pwm rtc/alarm, watchdog, persistent, laser fuse gpio application uart power clock/reset audio out multichannel adc/touchscreen ahb-i m apbx timers/ rotary decode lcd interface ahb-to-apbh bridge/dma m,s apbh irq control gpmi ram controller 64 kb rom debug uart rom controller s usb phy digctrl + entropy + bist to digctrl digital radio interface (dri) irda emi pio (shield) etm9 + jtag nand ata sdram nor s default first-level page table camera spi mmc sd/sdio/ ms m,s figure 3. STMP36XX soc block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 1: product overview 29 core, additional write post buffering in the peripheral ahb, and set/clear operations at the device registers make these operations efficient. figure 4 shows the memory map for the d-ahb devices. the dc-dc converters and the clock generator can be reprogrammed on-the-fly to dynamically trade off power versus performance. 1.6.2. on-chip ram and rom the STMP36XX includes 64kx32-bit on-chip ram. the ram includes embedded redundancy. any necessary ram repairs are done by the rom, as described in chapter 7 , ?digital control and on-chip ram? on page 123 . the STMP36XX also includes 16k 32-bit words of on-chip masked programmed rom. the rom contains init ialization code written by sigmatel, inc. to handle the initial boot and hardware initia lization. software in this rom offers a large number of boot configuration options, includi ng manufacturing boot modes for burn-in and tester operation. sdram/nor a 256 mbytes (cs0) 0x00040000 on-chip rom (64 kbytes) 4095 aliases of 256 kbytes on-chip sram 0x3fffffff 0x40000000 0x4fffffff sdram/nor b 256 mbytes (cs1) 0x50000000 0x5fffffff sdram/nor c 256 mbytes (cs2) 0x60000000 0x6fffffff sdram/nor d 256 mbytes (cs3) 0x7fffffff default slave 0x80100000 0x80000000 0x800fffff peripheral space 128 kbytes aliased in 1 gbyte rom aliased through 1 gbyte 0xc0000000 0xfffeffff 0xffff0000 0xffffffff on-chip sram 256 kbytes 0x00000000 0x0003ffff 0x70000000 figure 4. memory map for d-ahb devices free datasheet http:/// STMP36XX official product documentation 5/3/06 30 chapter 1: product overview 5-36xx-d1-1.02-050306 other boot modes are responsible for loading application code from off-chip into the on-chip ram. it supports initial program loading from a number of sources: ? nand flash devices ? nor flash devices ? ata hard drive ?i 2 c master mode from eeprom devices ? usb recovery mode at power-on time, the first instruction ex ecuted by the arm core comes from this rom. the reset boot vector is located at 0xffff0000. the on-chip boot code includes a firmware recovery mode. if the device fails to boot from nand flash, nor flash, or hard drive, fo r example, the device will atte mpt to boot from a pc host connected to its usb port. the on-chip ram and rom run on the ahb hclk domain. the maximum hclk frequency is 100 mhz. at this frequen cy, the on-chip ram and rom can supply a maximum of 400 mbytes per second. the rom boot loader can boot images fr om different devices, depending on the boot modes. this function is enabled by different boot mode pin configurations. additional laser fuse bits select one of 16 customer keys, which are further modified by laser fuses. a polynomial lsfr is used to decrypt the supplied boot image. a second polynomial computes an authentication code for the boot image. if the decrypted image does not compute the correct authentication code, then the boot loader will enter recovery mode and at tempt to boot from the usb device. these features are described in chapter 32 , ?boot modes? on page 787 . 1.6.3. interrupt collector the STMP36XX contains a 64-bit vector ed interrupt collector for the cpu?s irq input and a separate non-vectored interrupt collection mechanism for the cpu?s fiq input. each interrupt can be assigned to one of four levels of priority. the interrupt collector supports nesting of interrupts t hat preempt an interrupt service routine run- ning at a lower priority level. the interrupt collect or is described in chapter 5 , ?interrupt collector? on page 69 . 1.6.4. default first-level page table the STMP36XX contains a default first-le vel page table implemented as an ahb slave. this device provides an economical way to present 16 kbytes of nearly static data to the arm cpu?s mmu. the default fi rst-level page table provides access to the pio block at 0x80000000, as well as up to 16 mbytes of virtual memory defined in up to 16 secondary page tables. this feature is described more completely in chapter 6 , ?default first-level page table for arm926 mmu? on page 115 . 1.6.5. external memory interf ace (sdram/nor flash controller) the STMP36XX contains an external memo ry interface (emi) controller that can be used to connect external sdram memory chips. the controller is designed to work with 16 bit wide memory systems. it supports sdram products from 16mbit to 512mbit jedec families. the emi also su pports external nor flash devices at up to 512mbit per chip. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 1: product overview 31 the emi?s ahb slave supports split transactions to improve system wide perfor- mance and overlap with the on-chip ram. the external memory interface is described in chapter 12 , ?external memory inter- face (emi)? on page 325 . 1.6.6. dma controller many peripherals on the STMP36XX utilize direct me mory access (dma) transfers. some peripherals, such as the usb co ntroller, make highly random accesses to system memory for a large number of descriptor, queue heads, and packet payload transfers. this highly random access natu re is supported by integrating a dedicated dma into the usb controller and connecting it directly to the high-speed ahb bus. other peripherals have a small number of highly sequential transactions, for exam- ple the adc or dac streams, spdif transm itter, etc. these devices share a cen- tralized address generation and data transf er function that allows them to share a single shared master on the ahb. there are two amba peripheral buses on the STMP36XX: ? the apbh bus runs completely synchronous to the ahb?s hclk. ? the apbx bus runs in an independent clock domain that can be slowed down significantly for power reduction. thus, the ahb and apbh can run at 60 mhz, while the apbx runs at 6 mhz. see chapter 10 , ?ahb-to-apbh bridge with dma? on page 185 , and chapter 11 , ?ahb- to-apbx bridge with dma? on page 257 , for more deta iled information. the two bridge dmas are controlled through linked dma command lists. the cpu sets up the dma command chains before starting the dma. the dma command chains include set-up information for a peripheral and associated dma channel. the dma controller reads the dma command, writes any peripheral set up, tells the peripheral to start running and then transfers data, all without cpu intervention. the cpu can add commands to the end of a chain to keep data moving without inter- ventions. the linked dma command architecture offloads most of the real-time aspects of i/o control from the cpu to the dma controller. this provides better system perfor- mance, while allowing longer interr upt latency tolerances for the cpu. 1.6.7. clock generation subsystem the STMP36XX uses twenty-five domains to provide clocks to the various sub- systems, as shown in figure 5 . these clocks are either derived from the 24-mhz crystal or from the integrated high-speed pll. the pll output is programmable from 240 mhz to 480 mhz in 4 mhz steps. the pll must be set to 480 mhz for usb or spdif operation. more details about the system cl ock architecture can be found in chapter 4 , ?clock generation and control? on page 47 . the system includes a real-time clock that can use either the 24-mhz system crystal or a 32.768-khz rtc crystal. an integrated watchdog reset timer is also available for automatic recovery from errant code execution. see chapter 19 , ?real-time clock, alarm, watchdog, and pe rsistent bits? on page 497 for more information about these features. free datasheet http:/// STMP36XX official product documentation 5/3/06 32 chapter 1: product overview 5-36xx-d1-1.02-050306 1.6.8. power management unit the STMP36XX contains a sophisticated power management unit (pmu), including two integrated dc-dc converters and two linear regulators. the pmu can operate from a battery (1-cell, 2-cell, or li-ion) using the dc-dc converter(s) or a 5-v supply using the linear regulators and can automatically switch between them without inter- rupting operation. the pmu includes circui ts for battery and system voltage brown- out detection, as well as on-chip temp erature, digital speed, and process monitoring. xclk tree i 2 c m/s dc-dc multichannel adc / touch-screen audio control lcd if xtal 24 xtal32k 32,768 hz rtc digital clock generation pll pllclk 24 mhz pio rtcclk 32768 hz audio dac/adc analog and digital pio dcdcclk 6mhz audioclk 24 mhz pio pio xclk 0-24 mhz 24 mhz 32 khz arm926 cpuclk 0- 200 mhz tap jtag/tclk source h clk 0 -100 m h z usb phy usb arc pio usb clk utmi 30m sram controller external memory interface (emi) ahb - apbx bridge/dma ahb - apbh bridge/dma gpmi irq controller ecc gpio apbx master ahb if caches mmu clock top pio xclk 0-24 mhz spdif 60 mhz pio gpmiclk rom controller timers/ rotary decoder application uart debug uart pwm sclk ssp 24 mhz emiclk figure 5. clock diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 1: product overview 33 the chip has two programmable integrated dc-dc converters that can be used to provide power for the device as well as the entire application . the converters can be configured to operate from standard battery chemistries in the range of 0.9-4.2 volts including alkaline cells, nimh, li-ion, etc. these converters use off-chip reactive components (l/c) in a pulse width or frequency modulated dc-dc converter. the real-time clock includes an alarm function that can be used to ?wake-up? the dc-dc converters, which will then wake up the rest of the system. the power subsystem is described in chapter 31 , ?power supply? on page 747 . 1.6.9. usb interface the chip includes a high-speed universal serial bus (usb) version 2.0 controller and integrated usb transceiver macrocell interface (utmi) phy. the STMP36XX device interface can be attached to usb 2.0 hosts and hubs running in the usb 2.0 high-speed mode at 480mbit/second. it can be attached to usb 2.0 full-speed inter- faces at 12mbit/second. the usb controller and integrated phy support high-speed otg modes for peer- to-peer file interchange. the STMP36XX has a high-current pwm channel that can be used with low-cost external components to generate up to 8ma of 5 volts on the otg vbus for otg session initiation. the usb controller can also be configured as a high-speed host. the usb subsystem is designed to make efficient use of system resources within the STMP36XX. it contains a random access dma engine that reduces the interrupt load on the system and reduces the total bus bandwidth that must be dedicated to servicing the eight on-chip physical endpoints. it is a dynamically configured port that can support up to 5 endpoints, each of which may be configured for bulk, interrupt, or isochronous transfers. the usb configura- tion information is read from on-chip memory via the usb controller?s dma. see chapter 8 , ?usb high-speed on-the-go (host/device) controller? on page 155 and chapter 9 , ?integrated usb 2.0 phy? on page 161 for more information. 1.6.10. general-purpose media interface (gpmi) the chip includes a general-purpose media interface (gpmi) controller that sup- ports nand and ata devices. the nand flash interface provides a state machine that provides all of the logic necessary to perform dma functions between on- or off- chip ram and up to four nand flash devices. the controller and dma are sophisti- cated enough to manage the sharing of a single 16 bit wide data bus among 4 nand devices without detaile d cpu intervention. this allows the STMP36XX to pro- vide unprecedented levels of nand perf ormance. the gpmi?s ata mode provides a high-speed link to a hard drive or cd-rom. it supports pio-4 and udma mode 4 (up to 66mb/s). the general-purpose media interface can be described as two fairly independent devices in one. unlike previous generations, the three operating modes are inte- grated into one overall state machine that can freely intermix cycles to different device types on the media interface. there are four chip selects on the media inter- face. each chip select can be programmed to have a different type device installed, as shown in ta b l e 1 . for nand mp3 player applications, these might be all nand flash devices. the chip selects are shared with the external memory interface, so that chip select pins that are unused by the gpmi for nand or ata devices can be used by the emi free datasheet http:/// STMP36XX official product documentation 5/3/06 34 chapter 1: product overview 5-36xx-d1-1.02-050306 for sdram or nor flash devices. the two interfaces have independent data and control paths, so that simultaneous transfers can take place on both gpmi and the emi. the gpmi pin timings are based on a dedicated clock divider from the pll, allowing the cpu clock divider to change without affecting the gpmi. see chapter 13 , ?general-purpose media interface (gpmi)? on page 341 for more information. 1.6.11. hardware acceleration for ecc for robust external storage the forward error correction circuit (ecc) is used to provide STMP36XX applications with a reliable interface to various stor age media that would otherwise have unac- ceptable bit error rates. the ecc module c onsists of two different error correcting code processors: ? 1-bit error correcting samsung ssfdc (hamming code) encoder/decoder ? 4-symbol error correcting (9 bits/symbol) reed-solomon encoder/decoder the 1-bit hamming code is ssfdc compliant and can be used with most slc nand flash memories. this code is capabl e of correcting a single bit or detecting two incorrect bits over a 256-byte block. the reed-solomon mode is used for memori es that have a higher native defect probability, such as mlc nand. it can co rrect up to four 9-bit symbols over a 512-byte block. both of these error correction encoder/decoders use dma transfers to move data to and from on-chip ram completely in para llel with the cpu performing other useful work. the ecc reads source data blocks and parity bytes from the shared ahb master, decodes the error correction code, and generates an error report telling the cpu which, if any, bits need to be modified. see chapter 14 , ?hardware ecc accelerator (hwecc)? on page 361 for more information. 1.6.12. memory copy unit the soc contains a memory-to-memory copy controller using two channels of the dma. the source can be either from th e on-chip ram, rom, external sdram, or nor flash. similarly, the destination can target either on-chip or off -chip ram. see chapter 30 , ?memory copy device? on page 741 for more information. table 1. media interface options by application chip select nand player hard disk 0 nand hard disk 1 nand hard disk 2 nand sdram 3 nand nor free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 1: product overview 35 1.6.13. mixed signal audio subsystem the STMP36XX contains an integrated hi gh-quality mixed signal audio subsystem, including high-quality sigma delta d/a and a/d converters, as shown in figure 6 . the d/a converter is the mainstay of the audio decoder/player product application, while the a/d converter is used for voice recording and mp3 encoding applications. the chip includes a low-noise headphone driv er that allows it to directly drive low impedance (8 ? or 16 ? ) headphones. the direct drive, or ?capless? mode, removes the need for large, expensive dc blocking capacitors in the headphone circuit. the headphone power amplifier can detect headphone shorts and report them via the icoll interrupt system. a digitally prog rammable master volume control allows user control of the headphone volume. annoying clicks and pops are eliminated by zero crossing updates in the volume/mute circuits and by headphone driver startup and shutdown circuits. the microphone circuit has a mono to stereo programmable gain pre-amp and an optional microphone bias generator. these features are described in chapter 25 , ?audioin/adc? on page 623 , and chapter 26 , ?audioout/dac? on page 647 . 1.6.14. master digital control unit (digctl) the master digital control un it (digctl) provides control registers for a number of blocks that do not have their own ahb or apb slaves, notably the on-chip ram and on-chip rom controllers. in addition, it provides control registers for the sdram controller. finally, it provides several security features , including an entropy register, as well as the rom shield and jtag shield trust zone controls. see chapter 7 , ?digital control and on-chip ram? on page 123 for more information. 1.6.15. synchronous serial port (ssp) the ssp supports a wide range of synchronous serial interfaces, including: ? 4-bit high-speed mmc/sd/sdio ? spi ? 1-bit ms ? ti ssi ? microwire the ssp has a dedicated dma channel and a dedicated clock divider from the pll. see chapter 15 , ?synchronous serial port (ssp)? on page 383 for more information about these features. 1.6.16. i 2 c interface the chip contains a two-wire smb/i 2 c bus interface. it can act as either a slave or master on the smb interface. the on-chip rom supports boot operations from i 2 c mastered eeproms, as well as slave i 2 c boot mode. see chapter 21 , ?i2c interface? on page 539 for more information. free datasheet http:/// STMP36XX official product documentation 5/3/06 36 chapter 1: product overview 5-36xx-d1-1.02-050306 1.6.17. general-purpose input/output (gpio) the STMP36XX contains 85 gpio pins in th e 169-pin package. most digital pins that are available for specific functions, fo r example, the sdram interface, are also available as gpio pins if they are not ot herwise used in a particular application. see chapter 17 , ?pin control and gpio? on page 429 for more information line 1 adc l fifo to adc dma adc gain adc left input mux mic bias micin line 2 speaker headphone right headphone left dac r fifo from dac dma line 1 r dac l from dac dma line 1 l controlled by speaker pwd select=00 select=01 select=10 select=00 or 10 select=01 audioout_hpvol_select note: select=11 is invalid output speaker output r output l fifo adc r fifo to adc dma adc gain adc right input mux 1 1 2 2 7 7 4 4 5 5 6 3 1. audioout_dacvolume: digital volume control. 2. audioout_hpvol: analog volume control. 3. audioout_spkrvol: analog volume control that works on the speaker amp output. 4. audioin_adcvolume: digital volume control. 5. audioin_adcvol: analog volume control that controls the adc gain block. 6. audioin_micline_micgain: analog volume control that controls the mic amp. 7. atten_line bit notes: figure 6. mixed signal audio elements free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 1: product overview 37 1.6.18. lcd controller the lcd controller has a dedicated dma channel and can be used to transfer data directly to 8- or 16-bit lcd modules. it has programmable pin timing, support for 8080 and 6800 modes and automatically handshakes transfers to the lcd. see chapter 16 , ?lcd interface (lcdif)? on page 419 for more information. 1.6.19. spdif transmitter the STMP36XX includes a sony-philips digi tal interface format (spdif) transmit- ter. it includes independent sample-rate conv ersion hardware so that the a/d, d/a, and spdif can run simultaneously. the spdif has a dedicated dma channel. the spdif has its own clock divider from the pll. see chapter 27 , ?spdif transmitter? on page 679 for more information. 1.6.20. rotary decoder an automatic rotary decoder function is integrated into the chip. two digital inputs are monitored to determine which is leading and by how much. in addition, the hard- ware automatically determines the period for rotary inputs. see chapter 18 , ?timers and rotary decoder? on page 475 for more information. 1.6.21. dual uarts each of two uarts, similar to a 16550 uart, are provided?one for application use and one for debug use. both uarts are high-speed with 16-byt e rx and tx fifos. the application uart supports dma and flow control (cts/rts). see chapter 22 , ?application uart? on page 571 , and chapter 23 , ?debug uart? on page 589 for more information. 1.6.22. infrared interface the infrared interface supports serial infrar ed (sir), mid infrared (mir), fast infra- red (fir), and very fast irda (vfir) ra tes. it shares pins and dma channels with the application uart. see chapter 24 , ?irda controller? on page 607 for more information. 1.6.23. low-resolution adc and touch-screen interface eight channels of 12-bit resolution analog- to-digital conversion are provided. chan- nel 7 is always connected to the battery and cannot be used for any other purpose other than battery voltage measurement. channel 6 can be configured to monitor a number of internal system parameters. th e remaining six channels are available for other uses and can be used for resistive button sense, touch sc reens, or other ana- log input. channels 0 and 1 have integrated drivers for external temperature monitor thermistors. channels 2?5 have integrated drivers for resistive touch-screens. the lradc provides typical performance of 11-bit no-missing-codes and 9-bit snr. see chapter 29 , ?low-resolution adc and touch-screen interface? on page 705 for more information. 1.6.24. pulse width modulator (pwm) controller the STMP36XX contains four pwm output co ntrollers that can be used in place of gpio pins. applications include led brightness control and high-voltage generators for electroluminescent lamp (el) display backlights. independent output control of free datasheet http:/// STMP36XX official product documentation 5/3/06 38 chapter 1: product overview 5-36xx-d1-1.02-050306 each phase allows zero, one, or high-z to be independently selected for the active and inactive phases. individual outputs can be run in lock step with guaranteed non- overlapping portions for differential drive applications. see chapter 20 , ?pulse-width modulator (pwm) controller? on page 523 for more information. 1.6.25. camera interface the gpmi (ata/nand interface) has an experimental mode to support a standard digital camera. when camera data is being downloaded, the gpmi cannot perform other functions. contact your sigmatel r epresentative for more information before using this feature. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 2: c haracteristics and specifications 39 2. characteristics an d specifications this chapter describes the characteristics and specif ications of the STMP36XX and includes sections on absolute maximum ratings, recommended operating conditions, and dc characteristics. 2.1. absolute maximum ratings notes: 1. pswitch can tolerate vddio driven through a 47k resi stor, as the on-chip circui try prevents the actual voltage on the pin from exceeding acceptable levels. 2. pin sets for dcdc_mode, dio3, aio, and usbio, are defined in the pin list in chapter 35 , beginning on page 809 . table 2. absolute maximum ratings parameter min max units storage temperature ?40 125 c battery pin (batt)?dc-dc modes 0 and 1 ?0.3 4.242 v battery pin (batt)?dc-dc mode 2 ?0.3 3.40 v battery pin (batt)?dc-dc mode 3 ?0.3 1.98 v 5-volt source pin (vdd5v) ?0.3 5.25 v pswitch?dc-dc mode 3 (note 1 ) ?0.3 batt v pswitch?all other dc-dc modes (note 2 ) ?0.3 batt/2 v analog/digital supply voltage (vdda1, vddd1, vddd2, vddd3) ?0.3 1.98 v i/o supply (vddio1, vddio2, vddio3, vddio4) ?0.3 3.63 v dc-dc converter #1 (dcdc_vddd) ?0.3 1.98 v dc-dc converter #1 (dcdc_vddio)?dc-dc mode 0 ?0.3 4.242 v dc-dc converter #1 (dcdc_vddio) ?all other dc-dc modes ?0.3 3.63 v dc-dc converter #1 (dcdc1_batt) ?0.3 max (vddio, batt) v dc-dc converter #2 (dcdc2_vddio) ?0.3 3.63 v dc-dc converter #2 (dcdc2_pfet) ?0.3 4.242 v input voltage on dcdc_mode input pin relative to ground (note 2 ) ?0.3 batt v input voltage on any digital i/o pin relative to ground (dio3) (note 2 ) ?0.3 vddio+0.3 v input voltage on usb d+, d? pins relative to ground (usbio) (note 2 ) ?0.3 3.63 v input voltage on any analog i/o pin relative to ground (aio) (note 2 ) ?0.3 vdda+0.3 v free datasheet http:/// STMP36XX official product documentation 5/3/06 40 chapter 2: characteristics and specifications 5-36xx-d1-1.02-050306 2.2. recommended operating conditions table 3. recommended operating conditions parameter min typ max units ambient operating temperature (note 1 ) ?10 70 c digital/analog core supply voltage?vddd1, vddd2, vddd3, vdda1. specification dependent on frequency. (note 2 ) 1.35 - 1.98 v digital i/o supply voltage?vddio1, vddio2, vddio3, vddio4 2.90 3.0 3.63 v minimum battery startup voltage: dc-dc mode 0 - 3.1 - v dc-dc mode 1 - 2.9 - v dc-dc mode 3 - 0.9 - v standby current (note 3 ): dc-dc mode 0 (32-khz rtc off), batt = 4.2 v - 45 a dc-dc mode 0 (32-khz rtc on), batt = 4.2 v - 43 a dc-dc mode 3 (32-khz rtc off), batt = 1.6 v - 3 a dc-dc mode 3 (32-khz rtc on), batt = 1.6 v - 5 a microphone: full-scale input voltage (0 db gain) - 0.6 - vrms full-scale input voltage (20 db gain) - 0.06 - vrms full-scale input voltage (40 db gain) - 0.006 - vrms input resistance - 100 - k ? line inputs: full-scale input voltage (note 4 ) - 0.6 - vrms crosstalk between input channels (16 ? load) - ?75 - db input resistance (note 5 )-50- k ? linein-to-hp snr idle channel (note 6 )9599-db adc snr idle channel (note 6 )-85-db adc ?60 db dynamic range (note 6 )-85-db headphone: full-scale output voltage (vdda = 1.8 v, 16 ? load) - 0.54 - vrms full-scale output voltage (vdda = 1.35 v, 16 ? load) - 0.42 - vrms output resistance - - <1 ? thd+n (16 ? load) - ?79 ?66 db thd+n (10k ? load) - ?84 - db dac snr idle channel (note 6 )-99-db dac ?60 db dynamic range (note 6 )9599-db speaker: full-scale output voltage (vdda = 1.8 v, 8 ? load ) - 0.83 - vrms full-scale output voltage (vdda = 1.35 v, 8 ? load) - 0.62 - vrms full-scale output voltage (vdda = 1.8 v, 4 ? load) - 0.62 - vrms full-scale output voltage (vdda = 1.35 v, 4 ? load) - 0.45 - vrms output resistance - - <1 ? thd+n (8 ? load) ?66 db thd+n (4 ? load) ?60 db snr idle channel (8 ? load) (note 6 )90db snr idle channel (4 ? load) (note 6 )90db free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 2: c haracteristics and specifications 41 notes: 1. contact sigmatel for extended temperature range options. in most system designs, battery and display specifications will limit the operating range to well wit hin these specifications. mo st battery manufacturers recommend enabling battery charge only when the ambient temperature is bet ween 0 and 40c. to ensure that battery charging does not occur outside the recommended temperature range, the player ambient temperature may be monitored by connecting a thermistor to the lradc0 or lradc1 pin on the STMP36XX. 2. these limits should be guard-banded by 100 mv. recommended operating voltages for cpuclk can be found in ta b l e 4 . recommended operating voltages for hclk can be found in ta b l e 6 . 3. when the real-time clock is enabled, the chip cons umes current when in the off state to keep the crystal oscillator and the real-time clock running. with a typical 2850 mahour aa battery, this off state standby current would take more than one year to drain the battery fully. 4. at 1.35 vdda, max input is 0.45 vrms. 5. input resistance changes with volume setting: 20k ? at +12 db, 50k ? at 0 db, 100k ? at ?34.5 db. 6. measured ?a weighted? over a 20-hz to a 20-khz bandwidth, relative to full scale output voltage (when vdda = 1.8 v). 2.2.1. recommended operating conditions for specific clock targets use the tables in this section to select a proper setting for vddd and vddd brownout voltages based on standard analysis of worst case design and characterization data. notes: vddd must be set to the higher of the voltages listed in table 4 , table 5 , table 6 , and table 7 for the specific clock targets. measured supply voltage may not match the programmed value; see table 982, ?hw_power_vddctrl bit field descriptions,? on page 767 for more information. note: pllv2isel transitions from 0x2 to 0x0 are recommended only when also changing freq from 240 to 480 mhz. similarly, pllv2isel transitions from 0x0 to 0x2 are recommended only when changing freq from 480 to 240 mhz. table 4. recommended operating conditions for specific cpuclk targets max cpuclk target (mhz) min vddd target voltage hw_power_vddctrl_ vddd_trg (using dc-dc converters) corresponding vddd brownout voltage hw_power_vddctrl_ vddd_bo up to 150 1.440 0xd 1.344 0xa 160 1.472 0xe 1.376 0xb 170 1.536 0x10 1.440 0xd 180 1.600 0x12 1.504 0xf 190 1.664 0x14 1.568 0x11 200 1.696 0x15 1.600 0x12 table 5. pll voltage requirements pll frequency (mhz) hw_cpuctrl _pllctrl0_ freq hw_cpuctrl _pllctrl0_ pllv2isel min vddd target voltage hw_power_vddctrl _vddd_trg (using dc-dc converters) corresponding vddd brownout voltage hw_power _vddctrl_ vddd_bo 240?300 0x0f0?0x12c 0x2 1.376 0xb 1.312 0x9 304?360 0x130?0x168 0x2 1.504 0xf 1.408 0xc 364?400 0x16c?0x190 0x2 1.600 0x12 1.504 0xf 404?480 0x194?0xie0 0x2 1.888 0x1b 1.792 0x18 300?480 0x12c?0xie0 0x0 1.376 0xb 1.312 0x9 free datasheet http:/// STMP36XX official product documentation 5/3/06 42 chapter 2: characteristics and specifications 5-36xx-d1-1.02-050306 note: 1. emiclk = hclk = cpuclk after split-lot characterization of the part performa nce versus speed-sensor values, a closed-loop method for setting vddd voltage and brownout le vels will be provided that allows vddd settings to be tuned to the actual process corner of a part, at the t hen current ambient temperature and voltage. 2.3. dc characteristics table 6. recommended operating conditions for specific hclk targets max hclk target (mhz) min. vddd target voltage hw_power_vddctrl_ vddd_trg (using dc-dc converters) corresponding vddd brownout voltage hw_power_vddctrl_ vddd_bo up to 80 1.472 0xe 1.376 0xb 81?90 1.504 0xf 1.408 0xc 91?100 1.600 0x12 1.504 0xf table 7. recommended operating conditions for specific emiclk targets vddio target voltage max emiclk 1 target (mhz) pll min vddd target voltage hw_power_vddctrl_ vddd_trg (using dc-dc converters) corresponding vddd brownout voltage hw_power_ vddctrl_vddd_ bo 3.585 up to 24 on or off 1.472 0xe 1.376 0xb 3.585 30?60 on 1.504 0xf 1.408 0xc 3.585 70 on 1.536 0x10 1.440 0xd 3.585 80 240 mhz only 1.600 0x12 1.504 0xf 3.329 up to 24 on or off 1.472 0xe 1.376 0xb 3.329 30?60 on 1.472 0xe 1.376 0xb 3.329 70 on 1.504 0xf 1.408 0xc 3.329 80 240 mhz only 1.504 0xf 1.408 0xc 3.073 up to 24 on or off 1.472 0xe 1.376 0xb 3.073 30?70 on 1.472 0xe 1.376 0xb 3.073 80 on 1.504 0xf 1.408 0xc 2.945 up to 24 off 1.440 0xd 1.344 0xa table 8. dc characteristics parameter min typ max units power dissipation: vddd = 1.35 v, vdda = 1.35 v, vddio = 3.3 v, dc-dc_mode = 00 (li-ion h), vddd brownout = 1.30 v, cpuclk = 24 mhz, hclk = 24 mhz, pll off, usb off, application = mp3 play, minimu m power configuration selected. 45 mw v ih (dio3)?input high voltage for dio3 di gital i/o pin set in 3.3-v mode. 2.0 v v il (dio3)?input low voltage for dio3 di gital i/o pin set in 3.3-v mode 0.8 v v oh (dio3)?output high voltage for dio3 digital i/o pin set in 3.3-v mode, 4-ma mode 0.7*vddio v v oh (dio3)?output high voltage for dio3 digital i/o pin set in 3.3-v mode, 8-ma mode 0.7*vddio v v ol (dio3)?output low voltage for dio3 di gital i/o pin set in 3.3-v mode. 0.4 v free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 3: arm cpu complex 43 3. arm cpu complex this chapter describes the arm cpu incl uded on the STMP36XX and includes sec- tions on the processor core, the jtag debugger, and the embedded trace macrocell (etm) interface. 3.1. arm 926 processor core the on-chip reduced instruction set computer (risc) processor core is an arm, ltd. 926ej-s. this cpu implements the arm v5te instruction set architecture, which includes enhanced dsp instructions. the arm9ej-s has two instruction sets: a 32-bit instruction set used in the arm state and a 16-bit instruction set used in thumb state. the core offers the choice of running in the arm state or the thumb state or a mix of the two. this enables opti- mization for both code density and perfor mance. arm studies indicate that thumb code is typically 65% the size of equiva lent arm code, while providing 160% of the effective performance in constrained memory bandwidth applications. a block diagram of the arm926ej-s core is shown in figure 7 . see the following arm documentation for more information on the arm926ej-s core (http://www.arm.com/documentatio n/armprocessor_cores/index.html): ? arm926ej-s technical reference manual, ddi0198d ? arm926ej-s development chip reference manual, ddi0287a the arm9 core has a total of 37 programmer-visible registers, including 31 gen- eral-purpose 32-bit registers, six 32-bit status registers, and a 32-bit program counter, as shown in figure 8 . in arm state, 16 general-purpose registers and one or two status registers are accessible at any one time. in privileged modes, mode- specific banked registers become available. the arm state register set contains 16 dire ctly addressable registers, r0 through r15. an additional register, the current program status regist er (cpsr), contains condition code flags and the current mode bits. registers r0?r13 are general-pur- pose registers used to hold data and address values, with r13 being used as a stack pointer. r14 is used as the subroutine link register (lr) to hold the return address. register r15 holds the program counter (pc). the thumb state register set is a subset of the arm register set. the programmer has access to eight general-purpose registers, r0?r7, the pc (arm r15), the stack pointer (arm r13), the link register (arm r14), and the cpsr. exceptions arise whenever the normal flow of program execution has to be tempo- rarily suspended, for example, to service an interrupt from a peripheral. before attempting to handle an exception, the arm core preserves the current processor state, so that the original program can resume when the handler is finished. free datasheet http:/// STMP36XX official product documentation 5/3/06 44 chapter 3: arm cpu complex 5-36xx-d1-1.02-050306 the following exceptions are recognized by the core: ? swi?software interrupt ? undef?undefined instruction ? pabt?instruction prefetch abort ? fiq?fast periphe ral interrupt ? irq?normal peripheral interrupt ? dabt?data abort ? reset?reset ? bkpt?breakpoint the vector table pointing to these interr upts can be located at physical address 0x00000000 or 0xffff0000. the STMP36XX maps its 64-kbyte on-chip rom to the address 0xffff0000 to 0xffffffff. th e core is hardwired to use the high address vector table at hard reset (core port vinithi =1). the arm 926 core includes an 8-kbyte instruction cache and 8-kbyte data cache and has two master interfaces to the amba ahb, as shown in figure 7 . the STMP36XX always operates in little endian mode. arm9ej-s core instruction cache (8 kbytes) data cache (8 kbytes) control logic and bus interface unit write buffer integrated coprocessor amba ahb interface d-ahb arm926ej-s mmu mmu data tcm interface instruction tcm interface embedded trace macrocell interface unused unused interrupts fiq amba ahb interface i-ahb vinithi irq figure 7. arm926 risc processor core free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 3: arm cpu complex 45 3.2. jtag debugger the tap controller of the arm core in the STMP36XX performs the standard debug- ger instructions. 3.2.1. jtag read id the tap controller returns the following 32 -bit data value in response to a jtag read id instruction: 0x0792_64f3 3.2.2. jtag hardware reset the jtag reset instruction can be acco mplished by writing 0xdeadc0de to etm address 0x70. the etm is on scan chain 6. the bit stream is 0xf0deadc0de. the digital wide reset does not affect the dc-dc converters or the contents of the persistent registers in the analog side of the rtc. 3.2.3. jtag interaction with cpuclk because the jtag clock is sampled from the processor clock cpuclk, there are cases in which the behavior of cpuclk af fects the ability to make use of jtag. specifically, the jtag block will not function as expected if: ? cpuclk is stalled d ue to an interrupt ? cpuclk is less than 3x the jtag clock ? cpuclk is disabled for any reason r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) r8 r9 r10 r11 r12 user fiq irq abort svc undef thumb mode low registers thumb mode high registers figure 8. arm programmable registers free datasheet http:/// STMP36XX official product documentation 5/3/06 46 chapter 3: arm cpu complex 5-36xx-d1-1.02-050306 3.3. embedded trace macr ocell (etm) interface the STMP36XX includes an arm etm-9 trace module implementing a medium mode trace buffer. see the pin list in chapter 35 for the pinout of trace information. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 47 4. clock generation and control this chapter describes the clock generati on and control featur es of the STMP36XX and includes sections on the crystal os cillators, clock domai ns, low-power opera- tion, clock dividers, pll, usb phy initializ ation, and clocking behavior during reset. figure 9 shows a comprehensive view of all clocks included on the STMP36XX and their relationships to each other. the programmable registers are described in section 4.9 . 4.1. overview the STMP36XX clock architecture is desig ned to offer high performance, low power, and efficient software power management. the STMP36XX has up to three clock sources (two crystals and a phase-locked loop (pll)) that are distributed to twenty-four clock domains. many of the clock domains have variable frequency and gating to minimize power co nsumption. the high-speed bu s clock, used by many of the peripherals, has an automatic slow-down mode to reduce power while maintain- ing high performance. 4.2. crystal oscillators the STMP36XX integrates tw o crystal oscillators. a 24- mhz crystal is mandatory and provides the clock source for the pll and the main digital blocks. the 32.768-khz crystal oscillato r is available in the 169b ga package and can optionally be used as a clock referenc e for the real-time clock (rtc). the 32.768-khz oscilla- tor is used only to provide a low power, accurate reference for the rtc and is not used for any other functions. the crystal oscillators have severa l configurable parameters, including: ? crystal on or off when the STMP36XX is powered off. ? real-time clock circuit can use either crystal ? bias current adjustment ? extra load capacitor (used to adjust frequency error) the crystal configuration registers are pers istent through the normal digital reset and are located with all the other persistent control bits in the real-time clock block. 4.3. clock domains to offer the best combination of perform ance, power consumption, and ease of use, the STMP36XX has 25 clock domains, which are listed table 9 . free datasheet http:/// STMP36XX official product documentation 5/3/06 48 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 during reset, most clock domains are connected together and are sourced from xtal_clk24m, divided down to 6 mhz. ex ceptions include the dc-dc converter and real-time clock, which are always cloc ked by their nominal sources, even in reset. eight cycles after reset is deasserted, each clock domain is switched to its table 9. clock domains clk domain used by speed range comments xtal_clk24m most clock generators 24 mhz the root clo ck for most of the chip. it is converted into other clocks through dividers and muxes. cpuclk arm cpu 0.1?200 mhz divided from pll or xtal_clk24m. always an integer multiple of hclk. hclk main and hbus peripherals 0.1?100 mhz divided from cpuclk. always an integer multiple of emiclk. xclk xbus peripherals 0.1?24 mhz lower speed peripherals, divided from xtal_clk24m. ana_clk24m dc-dc, dac, adc 24 mhz low jitter analog clock, sourced from xtal_clk24m. digctrl_clk1m digctl 1- s timer 1 mhz gated and divided clock sourced from xtal_clk24m. dri_clk24m digital radio interface 24 mh z gated clock sourced from xtal_clk24m. emiclk emi hclk/n divided from hclk. exram_clk16k sdram controller 16 khz gat ed and divided clock sourced from xtal_clk24m. filt_clk24m dac/adc filters 24 mhz gat ed clock sourced from xtal_clk24m. gpmiclk gpmi 16?120 mhz allows constant bus speed while hclk varies. sourced from the pll. irclk ir 2400 hz?24 mhz sourced from irovclk. irovclk ir 1.8432?120 mhz source from the pll. lradc_clk2k lradc 2 khz gated and divided clock sourced from xtal_clk24m. ocram_clk main on-chip ram 0?24 mhz (32 khz typ.) gated and divided clock sourced from xtal_clk24m. pcm_spdifclk spdif 4.096?6.144 mhz fra ctional divider from spdifclk. rtc_clk32k rtc 32.768 khz or 32 khz clock tree for rtc_ana, sourced from either xtal_clk24m or xtal_clk32k. sclk ssp 20?120 mhz allows constant serial clock while hclk varies. sourced from the pll. spdifclk spdif 120 mhz sourced from the pll. timrot_clk32k timers/rotary decoder 32 kh z gated and divided clock sourced from xtal_clk24m. uart_clk uart 0.1?24 mhz gated clock sourced from xclk. utmi_clk120m usb 120 mhz clock for usb phy-to-controller interface. utmi_clk30m usb 30 mhz clock for usb phy-to-controller interface. utmi_clk480m utmi 480 mhz sourced from the pll. xtal_clk32k rtc 32.768 khz low-power source for real-time clock. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 49 default source. the pll is bypassed by default, so clock domains that are sourced from it are clocked at the 24-mhz cryst al rate. some clock domains are gated by default, including filt_clk24m, sclk, gpmiclk, and spdifclk. STMP36XX clocks having restricted rela tionships with each other are listed in table 10 . any clock relationship not listed in the table is not restricted. note: any clock relationship not listed is not restricted. 4.4. power saving features of the clock architecture the STMP36XX clocking system is designed for low-power operation. some of the low-power features include: ? multiple clock domains allo w lower performance peripherals to operate at lower clock rates. ? most digital blocks include clock gating options to reduce power consumption when they are not used. ? dynamic clock adjustment?most clock dom ains have adjustable dividers. in most modes, the pll speed can be adjusted from 240 mhz to 480 mhz in 4-mhz steps. this ensures that each part of the system can always run very close to the minimum frequency needed for the application. 4.5. clock dividers most of the clock domains have integer dividers. the dividers are designed to switch frequency within three of the slow er clocks?s periods. for example, when switching the cpuclk divider from (480 mhz/8) to (480 mhz/32), it could take up to 200 ns before the sw itch is complete. 4.5.1. automatic hclk divider to save power on the very large hclk domain, an automatic hclk divider can be used. the divider automatically adjusts hclk from a nominal ?fast? rate to a low power ?slow? rate when the cpu or other high-bandwidth users are not requesting the bus. the ratio of fast to slow rates is programmable to 2:1, 4:1 and 8:1. hclk can switch from slow to fast within 1 ?fas t? clock cycle. the hclk register has sev- eral options to select which criteria are used to put hclk into the fast mode. table 10. restricted clock relationships related clocks ratio min max hclk/sclk 1/4 4/1 hclk/gpmi 1/4 4/1 cpuclk/jtag_tck 12/1 none free datasheet http:/// STMP36XX official product documentation 5/3/06 50 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 crystal clock xtal_clk24m 24.000 mhz pll 240m-480m utmi_clk120m utmi_clk30m sclk gpmiclk cpuclk hclk emiclk spdifclk irclk crystal clock xtal_clk32k 32.768 khz 4 4 1 - 16 1 - 16 1 - 1024 1 - 255 1 - 255 1 - 4 4 - 130 fractional 5 - 768 768 rtc_clk32k utmi_clk480m filt_clk24m dri_clk24m digctrl_clk1m 24 ocram_clk 750 lradc_clk 12000 exram_clk16k 1500 xclk 1 - 1024 uart_clk timrot_clk32k 750 ana_clk24m hw_clkctrl_irclkctrl fixed divider fixed divider hw_clkctrl_spdifctrl hw_clkctrl_gpmictrl hw_clkctrl_sclkctrl hw_clkctrl_xclkctrl fixed divider fixed divider fixed divider fixed divider hw_clkctrl_cpuclkctrl hw_clkctrl_hbusclkctrl hw_clkctrl_emiclkctrl hw_clkctrl_irclkctrl fixed divider hw_clkctrl_pllctrl* hw_clkctrl_pllctrl_bypass hw_rtc_persistent0_clksource 0 1 0 1 irovclk pcm_spdifclk analog digital ? xtal only digital ? xtal or pll legend figure 9. STMP36XX clock tree free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 51 4.6. phase-locked loop (pll) the STMP36XX includes a 480-mhz pll to clock the high-speed transceiver. this pll can also be used for generating the system-wide digital clock. figure 11 shows a block diagram of the pll. the STMP36XX pll is programmable to generate a 240 to 480 mhz clock in 4-mhz steps. the pll clock is used at high fr equency by the usb. other digital clock domains divide the pll clock to lower frequencies. the pll is designed for low power, low jitter, and high frequency s witching speed. the frequency change time has been minimized to make dynamic clock ad justment more flexible to save power. most of the clock domains that are sourced from the pll use dividers to decrease the frequency to the desired range. typically, the pll and dividers are set to gener- ate a desired cpu frequency. the dividers can change very quickly, typically in just a few clock cycles. however, the pll requires up to 10 s to change frequency. during that time, the output of the clock divider is at a different frequency than was desired. it is typically acceptable for the frequency to be below the target for such a short period of time, but it is often unacceptable for the frequency to be above the target for even one clock cycle. pll hw_clkctrl_pllctrl * (240..480 mhz) crystal clock xtal_clk24m (24.000 mhz) 1 0 pll bypass mux hw_clkctrl_pllctrl0_bypass cpuclk divider hw_clkctrl_cpuclkctrl_div hclk divider hw_clkctrl_hbusclkctrl_div cpu hclk peripherals hclk auto slow down hw_clkctrl_hbusclkctrl_ slow_div emiclk divider hw_clkctrl_emiclkctrl_div emi xclk divider hw_clkctrl_xbusclkctrl_div xclk peripherals figure 10. detail diagram of key clocks free datasheet http:/// STMP36XX official product documentation 5/3/06 52 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 to ensure that the clocks are never faster than desired, the system must control the order of pll and frequency divider adjustme nts. if the divider ratio is increasing, then the divider adjustment must be made before the pll frequency change is com- plete. if the divide ratio is decreasing, then the divider adjustment is made after the pll adjustment is complete. the pll has a lock indicator bit that is set when a frequency adjustment is com- pleted. that lock bit can be used by softwa re. however, it is not necessary for soft- ware to wait for the pll lock bit to request a divider adjustment. the dividers can be programmed to wait for pll lock before adju sting their settings. this feature allows software to adjust the pll and all result ing frequencies, without waiting for the pll to finish its adjustment. note that the wa it for pll lock bit is edge-sensitive and takes effect only when the pll lock transitions from 0 to 1 (i.e., if the pll is already locked, then the wait for lock does not trigger). note: the pll is not capable of operating to its maximum frequency at low operat- ing voltages. refer to chapter 2 , ?characteristics and specifications? on page 39 , for detailed information about the relationship between maximum pll operating fre- quency and vdd voltage. 4.6.1. frequency program the pll can be programmed from 240 mhz to 480 mhz. the system uses many divided-down frequencies controlled by the clkctrl registers. the hw_clkctrl_pllctrl0.freq sets the frequency in 4-mhz increments. 4.6.2. pll use in usb and spdif modes to ensure proper operation and conform to industry standards, the pll must oper- ate at a fixed 480-mhz when usb is active . it must be a multiple of 120 mhz when spdif is active. the clocks that are source d by the pll can be adjusted using their dividers. for example, when the pll is o perating at 480 mhz, the cpu can operate at 160, 120, 96, 80, 68.5 mhz, etc. to use the on-chip usb phy, software must set the enable_usb_clk bit in the pll register. this function requires extra power, so it should only be used when the 24 mhz 480 mhz phase 2 hw_clkctrl_pllctrl0_pllcpnsel usbphy hw_clkctrl_pllctrl0_freq charge pump 480 mhz phase 3 480 mhz phase 3z 480 mhz phase 2 figure 11. pll block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 53 usb phy is powered up. see figure 12 and figure 13 for additional detail about phy initialization and suspend. 4.6.3. vco and phase followers the heart of the pll is th e variable crystal oscillator (vco), which can operate from 240 mhz to 480 mhz. the vco frequency is determined by the output of the charge pump, in standard fashion. the vco produces a 480-mhz clock for usb application and its exact out-of-phase comp onent. in the design, these are identified as vco_clk2 and vco_clk2z. in addition, three phase followers are included to pro- duce a precise eight-phase clock at 480 mhz. these eight phases are used in the high-speed digital receiver to operate the pll that tracks the incoming 480mbit/s usb receive digital stream. the vco_clk2 clock is also used as a single phase 480-mhz digital clock for various clock divi ders and other circuits within the clkc- trl. the vco and various of its phase followers can be selectively powered down to reduce the overall energy requirements of the STMP36XX. note: in non-usb mode, all clocks except vco_clk2 can be gated off by hw_clkctrl_pllctrl0.en_usb_clks to save power. 4.6.4. pfd and charge pump the phase/frequency detector (pfd) and charge pump (cp) are used to lock the vco to the reference oscillator. for the STMP36XX, the referenc e is the integrated crystal oscillator. the most common refe rence crystal frequencies are 24 mhz and 20 mhz. selective power down and control of the pfd, the cp, and various loop fil- ter parameters can be controlled in hw_clkctrl_pllctrl0 /1 . the charge pump gain (current) should be adjusted for different feedback settings; see hw_clkctrl0_pllcpnsel. free datasheet http:/// STMP36XX official product documentation 5/3/06 54 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 4.7. integrated usb 2.0 phy initialization flow charts hw_clkctrl_ pllctrl1_ lock==1 device and host operation not otg phy startup clear hw_usbphy_ctrl_sftrst clear hw_usbphy_ctrl_clkgate clear hw_usbphy_pwd clear hw_power_ctrl_clkgate set hw_power_debug_vbusvalidpiolock set hw_power_debug_avalidpiolock set hw_power_debug_bvalidpiolock set hw_power_sts_bvalid set hw_power_sts_avalid set hw_power_sts_vbusvalid set hw_clkctrl_cpuclkctrl_wait_pll_lock set hw_clkctrl_cpuclkctrl_div=400 set hw_clkctrl_gpmiclkctrl_wait_pll_lock set hw_clkctrl_gpmiclkctrl_div=400 set cpu clock to 1.2 mhz set gpmi clock to 1.2 mhz make sure xbus is lower than hbus hw_clkctrl_xbusclkctrl_power hw_clkctrl_pllctrl0_div=20 power on pll hw_clkctrl_pllctrl0_freq=480 program to 480 mhz clear hw_clkctrl_pllctrl0_bypass hw_clkctrl_xbusclkctrl_div=1 set hw_clkctrl_pllctrl0_en_usb_clks clear hw_clkctrl_utmiclkctrl_utmi_clk30m_gate switch to pll from crystal clear hw_clkctrl_utmiclkctrl_utmi_clk120m_gate no yes figure 12. usb 2.0 phy startup flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 55 4.8. clocking during reset while the digital reset is asserted, all digital clock domains are connected to a 6-mhz clock based on xtal_clk24m. in this mode, the clock trees are not bal- anced, but the low 6-mhz rate ensures that timing is met. the reset is allowed to propagate for sixteen 6-mhz clocks. eight 6- mhz clocks after reset is released, all clock domains revert to their defaults. a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. yes arc suspend interrupt? no arc irq to other arc isr set hw_usbphy_ctrl_enirqresumedetect set all power-down bits in hw_usbphy_pwd play shut down set hw_digctrl_ctrl_usb_clkgate set hw_clkctrl_pllctrl0_bypass set hw_clkctrl_pllctrl0_power pll bypass, switches to xtal figure 13. usb 2.0 phy pll suspend flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 56 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 4.9. programmable registers the following programmable registers are available to software for controlling and using the clock generation and control features of the STMP36XX. 4.9.1. pll control register 0 description the pll control register 0 programs the divide factor and sets vco and v2i. hw_clkctrl_pllctrl0 0x80040000 hw_clkctrl_pllctrl0_set 0x80040004 hw_clkctrl_pllctrl0_clr 0x80040008 hw_clkctrl_pllctrl0_tog 0x8004000c table 11. hw_clkctrl_pllctrl0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd5 pllvcokstart pllcpshortlfr pllcpdblip rsrvd4 pllcpnsel rsrvd3 pllv2isel force_freq en_usb_clks bypass power rsrvd1 freq table 12. hw_clkctrl_pllct rl0 bit field descriptions bits label rw reset definition 31 rsrvd5 ro 0x0 always set to zero. 30 pllvcokstart rw 0x0 test mode for sigm atel use only. this test bit is provided for the unlikely event that the vco does not start oscillation. this is theoretically possible, but highly unlikely and can only happen in a noiseless system. normally set to zero. to kick-start the vco, perform a zero-to-one transition on this bit followed by a one-to-zero transition. 29 pllcpshortlfr rw 0x0 test mode for sigmatel use only. this normally low test mode bit is used to short the charge pump resistor for a highly under-damped response. set to one to short the resistor. the resistor should only be shorted in test mode. 28 pllcpdblip rw 0x0 test mode for sigm atel use only. set to one to double the charge pump current to speed up lock time. it can be used in conjunction with the pllcpnsel field to change the loop performance. at start-up time, it can be set to one to shorten the lock time. during normal operation, this should be set to zero for the lowest overall tracking jitter. 27 rsrvd4 ro 0x0 always set to zero. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 57 description: the pll control register 0 programs the divide factor and sets vco and v2i. do not turn off the bypass bit until th e pll has completed a lock cycle. the pll generates clocks from 240 mhz to 480 mhz on the pllclk net. the pllclk net can be driven either from the pll or from the 24.0 -mhz crystal oscilla- 26:24 pllcpnsel rw 0x0 test mode for sigmatel use only. these bits are set in conjunction with pllcpdblip to maintain a constant loop-filter damping factor for the different divide ratios. they can also be used independently to speed up or slow down the activity of the pll. default = 0x0 default ip current times_15 = 0x2 ip current * 1.5 times_075 = 0x3 ip current * 0.75 times_05 = 0x4 ip current * 0.5 times_04 = 0x7 ip current * 0.4 23:22 rsrvd3 ro 0x0 always set to zero. 21:20 pllv2isel rw 0x0 these bits can be used to extend the frequency range of pll. pllv2isel transitions from 0x2 to 0x0 are recommended only when also changing freq from 240 to 480 mhz. similarly, pllv2isel transitions from 0x0 to 0x2 are recommended only when changing freq from 480 to 240 mhz. normal = 0x0 normal range lower = 0x1 lower the useful frequency range lowest = 0x2 lowest useful frequency range. highest = 0x3 highes t useful frequency range 19 force_freq rw 0x0 set this bit to one to fo rce a write to this register to push a repeated value in the freq bit field out to the pll. this allows firmware to bypass the logic that looks for a write to freq bit to be writing a different value than is already there. force_same_freq = 0x1 force the value in the freq field out to the pll, even if one is overwriting exactly the same value. honor_same_freq_rule = 0x0 honor the rule that says the freq field value must be over writen with a different value to force the value in the freq field out to the pll. 18 en_usb_clks rw 0x0 0: 8-phase pll outputs for usb phy are powered down. if set to 1, 8-phase pll outputs for usb phy are powered up. the pll must also be set to 480 mhz for usb operation. additionally, the utmiclk120_gate and utmiclk30_gate must be deasserted to enable usb operation. 17 bypass rw 0x1 if set to 1, pll is bypassed and pllclk is 24 mhz. 0: pllclk is sourced from the pll. pll must be powered up before this bit is set. 16 power rw 0x0 pll power on(0= pll of f; 1=pll on). allow 1 ms after turning the pll on before enabling the pll. 15:9 rsrvd1 ro 0x0 always set to zero. 8:0 freq rw 0x1e0 pll output frequency in mhz. the pll has 4-mhz steps (bits 0 and 1 are ignored). table 12. hw_clkctrl_pllct rl0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 58 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 tor. when bypass is set to zero, the pl lclk net is driven by the pll. when bypass is set to one, then pllclk is dr iven from the 24.0-mhz crystal oscillator. example: hw_clkctrl_pllctrl0_wr(bf_clkctrl_pllctrl0_freq(480)); // set to 480 mhz hw_clkctrl_pllctrl0_wr(bf_clkctrl_pllctrl0_bypass(0)); // final enable of pll 4.9.2. pll control register 1 description the pll control register 1 specifies the lock count to use for pll stabilization. hw_clkctrl_pllctrl1 0x80040010 hw_clkctrl_pllctrl1_set 0x80040014 hw_clkctrl_pllctrl1_clr 0x80040018 hw_clkctrl_pllctrl1_tog 0x8004001c description: use this register to control the various aspects of pll lock management. example: hw_clkctrl_pllctrl1_wr(bf_clkctrl_pllctrl1_lock_count(9000)); 4.9.3. cpu clock control register description the cpuclk clock control register prov ides controls for generating the arm cpuclk. hw_clkctrl_cpuclkctrl 0x80040020 table 13. hw_c lkctrl_pllctrl1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 lock force_lock rsrvd1 lock_count table 14. hw_clkctrl_pllct rl1 bit field descriptions bits label rw reset definition 31 lock ro 0x0 0: pll not locked. if set to 1, pll is locked. the pll lock timer should be set according to changes to the freq or power registers. the timer count depends on the change. 30 force_lock rw 0x0 set to one to start another pll lock cycle. note: to start another lock cycle, this must be cleared first. 29:16 rsrvd1 ro 0x0 always set to zero. 15:0 lock_count ro 0x0 reflects the number of cycles required by the pll to lock to the newly programmed frequency. default, power-on lock-time is 8192-cycles. counts up from zero until the value from the internal table is reached. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 59 description: controls for the arm 926 clock divider. example: hw_clkctrl_cpuclkctrl_wr(bf_clkctrl_cpuclkctrl_div(12)); // 480 mhz/12 = 40 mhz 4.9.4. ahb, apbh bus clock control register description the ahb, apbh bus clock control regi ster provides controls for hclk genera- tion. hw_clkctrl_hbusclkctrl 0x80040030 table 15. hw_c lkctrl_cpuclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd3 wait_pll_lock busy rsrvd2 interrupt_wait rsrvd1 div table 16. hw_clkctrl_cpucl kctrl bit field descriptions bits label rw reset definition 31 rsrvd3 ro 0x0 always set to zero. 30 wait_pll_lock rw 0x0 wait for pll lock. if this is set, then new data written to the div field will not take effect until the pll lock bit is set. 29 busy ro 0x0 this read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 28:13 rsrvd2 ro 0x0 always set to zero. 12 interrupt_wait rw 0x0 enables the gating of cpuclk when used in conjunction with the wait for interrupt instruction (mcr). 11:10 rsrvd1 ro 0x0 always set to zero. 9:0 div rw 0x001 this field controls the cpuclk divide ratio. cpuclk is generated from pllclk through this divider. this is an integer divider. values between 1 and 1023 are valid. changes to the cpuclk frequency will also affect hclk. note: pllclk is either sourced from the pll at frequencies between 240 mhz and 480 mhz or from the crystal oscillator at 24.0 mhz. the divider is set to divide by 1 at power-on reset. free datasheet http:/// STMP36XX official product documentation 5/3/06 60 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 table 17. hw_c lkctrl_hbusclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 wait_pll_lock busy rsrvd3 emi_busy_fast apbhdma_busy_fast apbxdma_busy_fast traffic_jam_fast traffic_fast cpu_data_fast cpu_instr_fast auto_slow_mode rsrvd2 slow_div rsrvd1 div table 18. hw_clkctrl_hbuscl kctrl bit field descriptions bits label rw reset definition 31 rsrvd4 ro 0x0 reserved 30 wait_pll_lock rw 0x0 wait for pll lock. if this is set, then new data written to the div field will not take effect until the pll lock bit has transitioned from cleared to set. note that this function is edge-sensitive. 29 busy ro 0x0 this read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 28 rsrvd3 ro 0x0 reserved 27 emi_busy_fast rw 0x0 from auto-slow mode, switch to fast mode when the external memory interface is busy. 26 apbhdma_busy_fast rw 0x0 from auto-slow mode, switch to fast mode when the apbh dma has pending activity. 25 apbxdma_busy_fast rw 0x0 from auto-slow mode, switch to fast mode when the apbx dma has pending activity. 24 traffic_jam_fast rw 0x0 from auto-slow mode, switch to fast mode when three or more masters are trying to use the ahb. 23 traffic_fast rw 0x0 from auto-slow mode, switch to fast mode when any master accesses the ahb. 22 cpu_data_fast rw 0x0 from auto-slow mode, switch to fast mode with cpu data access to ahb. 21 cpu_instr_fast rw 0x0 from auto-slow mode, switch to fast mode with cpu instruction access to ahb. 20 auto_slow_mode rw 0x0 enable hclk auto-slow mode. when this is set, then hclk will run at the slow rate until one of the fast mode events has occurred. 19:18 rsrvd2 ro 0x0 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 61 description: this register controls the clock divide r that generates the hclk, the clock used by the ahb and apbh buses. example: hw_clkctrl_hbusclkctrl_wr(bf_clkctrl_hbusclkctrl_div(2)); // set hclk to half the arm clock frequency 4.9.5. apbx clock control register description the apbx clock control register provides control of the xclk clock divider. hw_clkctrl_xbusclkctrl 0x80040040 17:16 slow_div rw 0x0 slow mode divide ratio. sets the ratio of hclk fast rate to the slow rate. 00=1, 01=2, 10 =4, 11=8 by1 = 0x0 slow mode divide ratio = 1 by2 = 0x1 slow mode divide ratio = 2 by4 = 0x2 slow mode divide ratio = 1 by8 = 0x3 slow mode divide ratio = 1 15:5 rsrvd1 ro 0x0 reserved 4:0 div rw 0x01 cpuclk-to-hclk divide ratio. hclk is sourced from pllclk but is related to cpuclk by the value in this divider. the hclk frequency is dependent on the pll, cpuclkdiv and hclkdiv. this is an integer divider. values between 1 and 16 are valid. note: pllclk is either sourced from the pll at frequencies between 240 mhz and 480 mhz or from the crystal oscillator at 24.0 mhz. the divider is set to divide by 1 at power-on reset. table 19. hw_clkctrl_xbusclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 busy rsrvd1 div table 20. hw_clkctrl_xbuscl kctrl bit field descriptions bits label rw reset definition 31 busy ro 0x0 this read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 30:10 rsrvd1 ro 0x0 always set to zero. 9:0 div rw 0x001 this field controls the xclk divide ratio. xclk is sourced from the 24-mhz xtal through this divider. this is an integer divider. values between 1 and 1023 are valid. table 18. hw_clkctrl_hbuscl kctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 62 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 description: this register controls the clock divide r that generates the xclk, the clock used by the apbx bus. example: hw_clkctrl_xbusclkctrl_wr(bf_clkctrl_xbusclkctrl_div(4)); // set apbx xbus clock to 1/4 the 24.0mhz crystal clock frequency 4.9.6. xtal clock control register description this xclk control register provides cont rol of various fixed dividers sourced from the 24-mhz xtal clock domain. hw_clkctrl_xtalclkctrl 0x80040050 description: this register controls various fixed-ra te dividers working off the 24.0-mhz crystal clock. table 21. hw_clkctrl_xtalclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 uart_clk_gate filt_clk24m_gate pwm_clk24m_gate dri_clk24m_gate digctrl_clk1m_gate timrot_clk32k_gate exram_clk16k_gate lradc_clk2k_gate rsrvd1 table 22. hw_clkctrl_xtalcl kctrl bit field descriptions bits label rw reset definition 31 uart_clk_gate rw 0x0 if set to 1, variable uart_clk is gated off. 30 filt_clk24m_gate rw 0x1 if set to 1, fixed 24-mhz clock for the digital filter is gated off. 29 pwm_clk24m_gate rw 0x0 if set to 1, fixed 24 -mhz clock for the pwm is gated off. 28 dri_clk24m_gate rw 0x0 if set to 1, fixed 24-mhz clock for the digital radio interface (dri) is gated off. 27 digctrl_clk1m_gate rw 0x0 if set to 1, fixed 1- mhz clock for digctrl is gated off. 26 timrot_clk32k_gate rw 0x0 if set to 1, fixed 32-khz clock for the timrot block is gated off. 25 exram_clk16k_gate rw 0x0 if set to 1, fixed 16-k hz clock for off-chip sram is gated off. 24 lradc_clk2k_gate rw 0x0 if set to 1, fixed 2- khz clock for lradc is gated off. 23:0 rsrvd1 ro 0x0 always set to zero. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 63 example: hw_clkctrl_xtalclkctrl_wr(bf_clkctrl_xtalclkctrl_uart_clk_gate(1)); 4.9.7. on-chip sram clock control register description this register is reserved for si gmatel use and should not be written. hw_clkctrl_ocramclkctrl 0x80040060 4.9.8. utmi clock control register description hw_clkctrl_utmiclkctrl 0x80040070 table 23. hw_clkctrl_ocramclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 clkgate busy rsrvd1 div table 24. hw_clkctrl_ocramcl kctrl bit field descriptions bits label rw reset definition 31 clkgate rw 0x0 reserved. 30 busy ro 0x0 reserved. 29:10 rsrvd1 ro 0x0 reserved. 9:0 div rw 0x2ee reserved. table 25. hw_clkctrl_utmiclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 utmi_clk120m_gate utmi_clk30m_gate rsrvd1 free datasheet http:/// STMP36XX official product documentation 5/3/06 64 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 description: this register controls the clock gating for the integrated usb 2.0 phy utmi. example: hw_clkctrl_utmiclkctrl_wr(bf_clkctrl_utmiclkctrl_utmi_clk120m_gate(0)); hw_clkctrl_utmiclkctrl_wr(bf_clkctrl_utmiclkctrl_utmi_clk30m_gate(0)); 4.9.9. synchronous serial port clock control register description hw_clkctrl_sspclkctrl 0x80040080 table 26. hw_clkctrl_utmicl kctrl bit field descriptions bits label rw reset definition 31 utmi_clk120m_gate rw 0x1 utmiclk120 gate. if set to 1, utmiclk120m is gated off. 0: utmiclk120m is not gated. utmiclk120m is a 120-mhz fixed clock that is only valid when the pll is running at 480 mhz. 30 utmi_clk30m_gate rw 0x1 utmiclk30 gate. if set to 1, utmiclk30 is gated off. 0: utmiclk30 is not gated. utmiclk30 is a 30- mhz fixed clock that is only valid when the pll is running at 480 mhz. 29:0 rsrvd1 ro 0x0 always set to zero. table 27. hw_clkctrl_sspclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 clkgate wait_pll_lock busy rsrvd1 div table 28. hw_clkctrl_sspcl kctrl bit field descriptions bits label rw reset definition 31 clkgate rw 0x1 sclk gate. if set to 1, sclk is gated off. 0: sclk is not gated 30 wait_pll_lock rw 0x0 wait for pll lock. if this is set, then new data written to the div field will not take effect until the pll lock bit is set. 29 busy ro 0x0 this read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 65 description: this register controls the clock divide r that generates the clock for the synchronous serial port (ssp). example: hw_clkctrl_sspclkctrl_wr(bf_clkctrl_sspclkctrl_div(40)); 4.9.10. general-purpose media interface clock control register description hw_clkctrl_gpmiclkctrl 0x80040090 28:9 rsrvd1 ro 0x0 always set to zero. 8:0 div rw 0x1 the synchronous serial port clock frequency is determined by dividing the pllclk by the value in this bit field. note: pllclk is either sourced from the pll at frequencies between 240 mhz and 480 mhz or from the crystal oscillator at 24.0 mhz. the divider is set to divide by 1 at power-on reset. table 29. hw_cl kctrl_gpmiclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 clkgate wait_pll_lock busy rsrvd1 div table 30. hw_clkctrl_gpmiclkctrl bit field descriptions bits label rw reset definition 31 clkgate rw 0x1 gpmiclk gate. if set to 1, gpmiclk is gated off. 0: gpmiclk is not gated 30 wait_pll_lock rw 0x0 wait for pll lock. if this is set, then new data written to the div field will not take effect until the pll lock bit is set. 29 busy ro 0x0 this read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. table 28. hw_clkctrl_sspcl kctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 66 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 description: this register controls the divider that generates the general-purpose media inter- face (gpmi) clock. example: hw_clkctrl_gpmiclkctrl_wr(bf_clkctrl_gpmiclkctrl_div(40)); 4.9.11. spdif clock control register description hw_clkctrl_spdifclkctrl 0x800400a0 description: this register controls the clock divider that generat es the spdif clock. example: 28:10 rsrvd1 ro 0x0 always set to zero. 9:0 div rw 0x1 the gpmi clock frequency is determined by dividing the pllclk by the value in this bit field. note: pllclk is either sourced from the pll at frequencies between 240 mhz and 480 mhz or from the crystal oscillator at 24.0 mhz. the divider is set to divide by 1 at power-on reset. table 31. hw_clkctrl_spdifclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 clkgate busy rsrvd1 div table 32. hw_clkct rl_spdifclkctrl bit field descriptions bits label rw reset definition 31 clkgate rw 0x1 spdifclk gate. if set to 1, spdifclk is gated off. 0: spdifclk is not gated 30 busy ro 0x0 this read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 29:3 rsrvd1 ro 0x0 always set to zero. 2:0 div rw 0x4 this field controls the spdifclk divide ratio. spdifclk is sourced from the pll through this divider. this is an integer divider. values between 1 and 4 are valid. to meet industry standards, the spdifclk must always be set to 120 mhz, i.e., at pll=480 mhz, spdifclkdiv = 4. table 30. hw_clkctrl_gpmiclkctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 4: clock generation and control 67 hw_clkctrl_spdifclkctrl_wr(bf_clkctrl_spdifclkctrl_div(4)); 4.9.12. emi clock control register description hw_clkctrl_emiclkctrl 0x800400b0 description: this register controls the clock divider that generates the external memory inter- face (emi) clock. example: hw_clkctrl_emiclkctrl_wr(bf_clkctrl_emiclkctrl_div(1)); 4.9.13. ir clock control register description hw_clkctrl_irclkctrl 0x800400c0 table 33. hw_c lkctrl_emiclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 clkgate wait_pll_lock busy rsrvd1 div table 34. hw_clkctrl_emicl kctrl bit field descriptions bits label rw reset definition 31 clkgate rw 0x1 emiclk gate. if set to 1, emiclk is gated off. 0: emiclk is not gated 30 wait_pll_lock rw 0x0 wait for pll lock. if this is set, then new data written to the div field will not take effect until the pll lock bit is set. 29 busy ro 0x0 this read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 28:3 rsrvd1 ro 0x0 always set to zero. 2:0 div rw 0x1 this field controls the emiclk divide ratio. emiclk is sourced from hbusclk through this divider. this is an integer divider. values between 1 and 7 are valid. note that this bit cannot be changed during a transfer, or else the data in the dram may be corrupted. free datasheet http:/// STMP36XX official product documentation 5/3/06 68 chapter 4: clock generation and control 5-36xx-d1-1.02-050306 description: this register controls the generation of both the ir clock and the ir oversample clock. example: hw_clkctrl_irclkctrl_wr(bf_clkctrl_irclkctrl_irov_div(4) | bf_clkctrl_irclkctrl_ir_div(4)); clkctrl xml revision: 1.54 table 35. hw_clkctrl_irclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 clkgate wait_pll_lock auto_div ir_busy irov_busy rsrvd2 irov_div rsrvd1 ir_div table 36. hw_clkctrl_irclkctrl bit field descriptions bits label rw reset definition 31 clkgate rw 0x1 irclk gate. if set to 1, irclk is gated off. 0: irclk is not gated 30 wait_pll_lock rw 0x0 wait for pll lock. if this is set, then new data written to the div field will not take effect until the pll lock bit is set. 29 auto_div rw 0x1 allow hardware to autom atically set the divide ratios. 28 ir_busy ro 0x0 this read-only bit field returns a one when the ir_div clock divider is busy transfering a new divider value across clock domains. 27 irov_busy ro 0x0 this read-only bit field returns a one when the irov_div clock divider is busy transfering a new divider value across clock domains. 26:25 rsrvd2 ro 0x0 always set to zero. 24:16 irov_div rw 0x4 this field controls the irclk divide ratio-1. this is an integer divider. values between 4 and 130 are valid. this divider is used in conjunction with ir_div to set the final rate of the irclk. 15:10 rsrvd1 ro 0x0 always set to zero. 9:0 ir_div rw 0x4 this field controls the irclk divide-ratio-2. this is an integer divider. values between 5 and 768 are valid. this divider is used in conjunction with irov_div to set the final rate of the irclk. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 69 5. interrupt collector this chapter describes the interrupt control features of the STMP36XX and includes sections on interrupt nesting, fiq generat ion, and cpu wait-f or-interrupt mode. ta b l e 3 7 lists all of the interrupt sources available on the STMP36XX. programmable registers for interrupt generation and control are described in section 5.7 . 5.1. overview the arm926 cpu core has two interrupt input lines, irq and fiq. as shown in figure 14 , the interrupt collector (icoll) steers 64 interrupt sources to the two inter- rupt input signals on the arm core: irq and fiq. within an individual interrupt request line, the icoll offers four-level priority (above base level) for each of its inter- rupt sources. preemption of a lower priority interrupt by a higher priority is supported (interrupt nesting). interrupts assigned to the same level are serviced in a strict linear priority order within level from lowest to highest interrupt source bit number. 0 . . . 31 32 . . . 63 int sources arm 926 fiq irq hw_icollvbase (vector table base addr) hw_icollraw0 (read-only) hw_icollpriority0 (priority register) 0 hw_icollpriority (enable bit) hw_icollpriority (software interrupt) hw_icollpriority7 (priority register) 3 27 31 0 . . . 31 0 . . . 31 hw_icollraw1 (read-only) hw_icollpriority8 (priority register) 32 hw_icollpriority15 (priority register) 35 60 63 32 . . . 63 32 . . . 63 vector address = vector base address + 4 * source bit number hw_icollvector apbh ahb hw_icollpriority (enable bit) hw_icollpriority (software interrupt) figure 14. interrupt collec tor diagram for irq generation free datasheet http:/// STMP36XX official product documentation 5/3/06 70 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 fiq interrupts are not prioritized, nor are they vectorized. exactly four of the inter- rupt sources can be selected to generate the fiq interrupt, source bits 32 through 35. if more than one is routed to the fiq, then they must be discriminated by soft- ware. generally, the fiq is reserved for the exclusive use of brownout interrupts. 32 . . . 63 int sources arm 926 fiq irq hw_icoll_vbase (vector table base addr) hw_icoll_raw1 (read-only) hw_icoll_priority9_enable1 hw_icoll_vector apbh ahb hw_icoll_priority9_softirq1 hw_icoll_priority9_priority1 1:4 vector address = vector base address + 4 * source bit number figure 15. interrupt collector bit ?37? logic free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 71 for a single interrupt source bit, there is an enable bit that gates it to the priority logic. a software interrupt bit per source bit can be used to force an interrupt at the appropriate priority level directed to the corresponding vector address. each source can be applied to one of four interrupt levels, as shown in figure 15 . the enable bit, the software interrupt bit, a nd the two-bit priority level specification for each interrupt source bit are contained in a byte in the programmable registers. the data path for generating the vector address for the vectored interrupt portion of the interrupt collector is implemented as a multicycle path, as shown in figure 16 . the interrupt sources are continuously sampled in the holding register until one or more arrive. the fsm causes the holding register to stop sampling while a vector address is computed. each interrupt source bit is applied to one of four levels based on the two-bit priority specification of each source bit. when the holding register ?closes,? there can be more than one newly arrived source bit. thus, the source bits could be assigned such that more than one interrupt level is requesting an interrupt. the pipeline first determines the highest level requesting interrupt service. all inter- rupt requests on that level are presented to the linear priority encoder. the result of this stage is a six-bit number corresponding to the source bit number of the highest priority requesting an interrupt. this six-bit source number is used to compute the vector address as follows: vectoraddress = vectorbase + (4 * sourcebitnumber) 32 . . . 63 int sources arm 926 fiq irq hw_icoll_raw1 (read-only) hw_icoll_vector apbh ahb priority37[1:0] pick hghest level enable37 softirq37 holding register 1:4 fsm linear priority compute vector address apb pio cycles multicycle path 3x (1x) figure 16. irq control flow free datasheet http:/// STMP36XX official product documentation 5/3/06 72 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 5.2. nesting of multi-level irq interrupts there are a number of very important interactions between the interrupt collector?s fsm and the interrupt service routine (isr) running on the cpu. see figure 17 for the following discussion. as soon as the interrupt source is recogn ized in the holding register, the fsm delays two clocks, then grabs the vector address and asserts irq to the cpu. as soon as possible after the cpu enters the interrupt se rvice routine, it must notify the interrupt collector. software indicates the in -service state by writing to the hw_icoll_vector register. the contents of the data bus on this write do not matter. optionally, firmware can enable the arm read side-effect mode. in this case, the in-service state is indicated as a side effect of having read the hw_icoll_vector register at the exceptio n vector (0xffff0018). at this point, the fsm reopens the holding register and scans for new interrupt sources. any such irq sources are presented to the cpu, provided that they are at a level higher than any currently in-service level. base irq level 0 irq level 3 irq level 2 irq level 1 inservice re-enable irq inservice re-enable irq acklevel3 inservice re-enable irq acklevel2 acklevel0 irq csr irq critical section critical section critical section figure 17. nesting of multi-level irq interrupts free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 73 whenever the arm cpu takes an irq exception, it turns off the irq enable in the cpu status register (csr), as shown in figure 17 . if a higher priority interrupt is pending at this point, then a nother irq exception is taken. the example in figure 17 shows going from the base to a level 0 isr. when the isr at level 0 was ready, it enabled irq inte rrupts. at this point , it nests irq inter- rupts up to a level 3 interrupt. the level 3 isr marks its in-service state, which causes the interrupt collector to open the holding register to search for new interrupt sources. in this example, none comes in, so the level 3 isr completes. as part of the return process, the isr disables irq interrupts, then acknowledges the level 3 service state. this is accomplished by writi ng the level number (3 in this case) to the interrupt collector?s level acknowledge register. the interrupt collector resets the in- service bit for level 3. if this enables an irq at level 3, then it asserts irq and goes through the nesting process again. since irq exceptions are masked in the level 3 isr, this nesting does not take place until the level 3 isr returns from interrupt. this return automatically re-enables irq exc eptions. at this point, another exception could occur. figure 17 shows a second nesting of the irq interrupt by the arrival of a level 2 interrupt source bit. finally, the figure shows the point at which the level 0 isr enters its critical section (masks irq) a nd acknowledges level 0 to the interrupt col- lector and returns from interrupt. the fsm reverts to its ?base? level state waiting for an in terrupt re quest to arrive in the holding register. the waveform for the irq mask in the cpu status register (csr) and the waveform for the irq input to the cpu as they rela te to the interrupt collector action are shown in figure 17 . warning : there is an inherent race condition between notifying the interrupt col- lector that an isr has been entered and having that isr re-enable irq exceptions in the csr. the in-service notification ca n take a number of cycles to percolate through the write buffer, through the ahb and apb bridge and into the interrupt col- lector where it removes the irq assertio n to the cpu. this icoll irq must be deasserted before the csr irq on the cp u is re-enabled or the cpu will see a phantom interrupt. this is why the arm vect ored interrupt controller provides this in service notification as a read side effect of the vector address read. alternatively, the isr can read the interrupt collector?s csr. the value received is unimportant, but the time required to do the read ensures that the write data has arrived at the inter- rupt collector. if firmware uses this method, it should allow cloc ks after the read for the fsm and for the cpu to recognize that the irq has been deasserted. 5.3. fiq generation four of the interrupt source bits can be used to generate an fiq instead of an irq exception. these are source bits 32 thro ugh 35, inclusive. an fiq may be gener- ated by one of four source bits. figure 18 shows the fiq sequence for interrupt source bit 33. when enabled to the fiq, th e software interrupt associated with these bits can be used to generate the fiq from these sources for test purposes. fiq for a given interrupt should be enabled only when the irq for that interrupt is disabled. free datasheet http:/// STMP36XX official product documentation 5/3/06 74 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 32 . . . 63 int sources arm 926 fiq irq hw_icoll_vbase (vector table base addr) hw_icoll_raw1 (read-only) hw_icoll_priority8_enable1 hw_icoll_vector apbh ahb hw_icoll_priority8_softirq1 hw_icoll_priority8_priority1 1:4 hw_icoll_ctrl_enable2fiq33 vector address = vector base address + 4 * source bit number figure 18. fiq generation logic free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 75 5.4. interrupt sources ta b l e 3 7 lists all of the interrupt sources on the STMP36XX. use hw_irq.h to access these bits. table 37. interrupt sources interrupt source src vector fiq description debug uart 0 0x0000 no no dma on the debug uart comms rx 1 0x0004 no jtag debug communications port comms tx 2 0x0008 no jtag debug communications port vdd5v 3 0x000c no irq on 5v connect or disconnect also otg 4.2v headphone_short 4 0x0010 no headphone short dac_dma 5 0x0014 no dac dma channel dac_error 6 0x0018 no dac fifo buffer underflow adc_dma 7 0x001c no adc dma channel adc_error 8 0x0020 no adc fifo buffer overflow spdif_dma 9 0x0024 no spdif dma channel spdif_error 10 0x0028 no spdif underflow usb_ctrl 11 0x002c no usb controller interrupt usb_wakeup 12 0x0030 no also arc core to remain suspended gpmi_dma 13 0x0034 no from dma channel for gpmi ssp_dma 14 0x0038 no from dma channel for ssp ssp_error 15 0x003c no ssp device level error and status gpio0 16 0x0040 no gpio bank 0 interrupt gpio1 17 0x0044 no gpio bank 1 interrupt gpio2 18 0x0048 no gpio bank 2 interrupt gpio3 19 0x004c no gpio bank 3 interrupt ecc_dma 20 0x0050 no from dma channel for hwecc ecc_error 21 0x0054 no from the hwecc device itself rtc_alarm 22 0x0058 no rtc alarm event uart_tx_dma 23 0x005c no application uart transmitter dmaq uart1_internal 24 0x0060 no application uart internal error uart_rx_dma 25 0x0064 no application uart receiver dma interrupt i2c_dma 26 0x0068 no from dma channel for i 2 c i2c_error 27 0x006c no from i 2 c device detected errors and line conditions timer0 28 0x0070 no timrot timer0 timer1 29 0x0074 no timrot timer1 timer2 30 0x0078 no timrot timer2 timer3 31 0x007c no timrot timer3 bat_brnout 32 0x0080 yes power module battery brownout detect free datasheet http:/// STMP36XX official product documentation 5/3/06 76 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 vddd_brnout 33 0x0084 yes power module vddd brownout detect vddio_brnout 34 0x0088 yes power module vddio brownout detect vdd18_brnout 35 0x008c yes reserved for future use touch_irq 36 0x0090 no touch detection lradc_ch0 37 0x0094 no channel 0 complete lradc_ch1 38 0x0098 no channel 1 complete lradc_ch2 39 0x009c no channel 2 complete lradc_ch3 40 0x00a0 no channel 3 complete lradc_ch4 41 0x00a4 no channel 4 complete lradc_ch5 42 0x00a8 no channel 5 complete lradc_ch6 43 0x00ac no channel 6 complete lradc_ch7 44 0x00b0 no channel 7 complete memcpy_dma_src 45 0x00b4 no from dma channel for memcpy source memcpy_dma_dst 46 0x00b8 no from dma channel for memcpy destination lcd_dma 47 0x00bc no from dma channel for lcd rtc_1msec 48 0x00c0 no rtc 1-ms tick interrupt dri_dma 49 0x00c4 no from dma channel for dri dri_attention 50 0x00c8 no from dri internal error and attention irq gpmi_attention 51 0x00cc no from gpmi internal error and status irq ir 52 0x00d0 no from ir (infrared) internals. note that the ir shares dma channels with the applications uart. reserved for future hardware 53?59 0x00d4? 0x00e8 no do not use these interrupts in STMP36XX. softwareirq60? softwareirq63 60?63 0x00f0? 0x00fc no for software use. table 37. interrupt sources (continued) interrupt source src vector fiq description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 77 5.5. cpu wait-for-interrupt mode to enable wait-for-interrupt mode, two distinct actions are required by the program- mer. 1. set the interrupt_wait bit in the hw_clkctrl_cpuclkctrl register. this must be done via a rmw operation. for example: uclkctrl = hw_clkctrl_cpuclkctrl_rd(); uclkctrl |= bm_clkctrl_cpuclkctrl_interrupt_wait; hw_clkctrl_cpuclkctrl_wr(uclkctrl); 2. after setting the interrupt_wait bit, a coprocessor instru ction is required. asm ( // note: r0 is used in the following example, but any usual // STMP36XX official product documentation 5/3/06 78 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 5.7. programmable registers the following registers provide interrupt generation and control for the STMP36XX. 5.7.1. interrupt collector interrupt vector address register description the interrupt collector interrupt vector address register is read by the interrupt service routine (isr) at the irq vector location (0xffff0018) using a load pc instruction. the priority logic presents the vector address of the next irq interrupt to be processed by the cpu. the vector addr ess is held until acknowledged by a cpu write to the hw_icoll_vector register. hw_icoll_vector 0x80000000 hw_icoll_vector_set 0x80000004 hw_icoll_vector_clr 0x80000008 hw_icoll_vector_tog 0x8000000c description: this register mediates the vectored interrupt collectors in terface with the cpu when it enteres the irq exception trap. the exception trap should have a ldpc instruction from this address. example: ldpc hw_icoll_vector_addr; irq exception at 0xffff0018 5.7.2. interrupt collector level acknowledge register description the interrupt collector level acknowledge re gister is used by software to indicate the completion of an inte rrupt on a specific level. hw_icoll_levelack 0x80000010 table 38. hw_icoll_vector 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 irqvector rsrvd1 table 39. hw_icoll_vector bit field descriptions bits label rw reset definition 31:2 irqvector rw 0x0 this register presents the vector address for the interrupt currently active on the cpu irq input. writing to this register notifies the interrupt collector that the interrupt service routine for the current interrupt has been entered. 1:0 rsrvd1 ro 0x0 always write zeroes to this field. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 79 description: this register is written to advance the icoll internal irq state machine. it advances from an in-service on a level stat e to the next pending interrupt level or to the idle state. this register is written at the very end of an interrupt service routine. if nesting is used, then the cpu irq must be turned on before writing to this register to avoid a race condition in the cpu interrupt hardware. warning: the value writ- ten to the interrupt collector level acknowle dge register is decoded not binary, i.e., 8, 4, 2, 1. example: hw_icoll_levelack_wr(hw_icoll_levelack__level3); 5.7.3. interrupt collector control register description the interrupt collector control register prov ides overall control of interrupts being routed to the cpu. this register is not at offset zero from the block base because that location is needed for single 32-bit instructions to be placed in the exception vector location. hw_icoll_ctrl 0x80000020 hw_icoll_ctrl_set 0x80000024 hw_icoll_ctrl_clr 0x80000028 hw_icoll_ctrl_tog 0x8000002c table 40. hw _icoll_levelack 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 irqlevelack table 41. hw_icoll_level ack bit field descriptions bits label rw reset definition 31:4 rsrvd1 ro 0x0 any value can be written to this bit field. writes are ignored. 3:0 irqlevelack rw 0x0 this bit field is written by the processor to acknowledge the completion of an interrupt. the value written must correspond to the priority level of the completed interrupt: level0 = 0x1 level 0 level1 = 0x2 level 1 level2 = 0x4 level 2 level3 = 0x8 level 3 free datasheet http:/// STMP36XX official product documentation 5/3/06 80 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 table 42. hw_icoll_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsrvd3 enable2fiq35 enable2fiq34 enable2fiq33 enable2fiq32 rsrvd2 bypass_fsm no_nesting arm_rse_mode fiq_final_enable irq_final_enable rsrvd1 table 43. hw_icoll_ctr l bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 when set to one, this bit causes a soft reset to the entire interrupt collector. this bit must be turned off for normal operation. run = 0x0 allow the interrupt collector to operate normally. in_reset = 0x1 hold the interrupt collector in its reset state. 30 clkgate rw 0x1 when set to one, this bit causes all clocks within the interrupt collector to be gated off. warning: do not set this bit at the same time as sftrst. doing so causes the softreset to have no effect. setting sftrst will cause the clkgate bit to set automatically four clocks later. run = 0x0 enable clocks for normal operation of interrupt collector. no_clocks = 0x1 disable clocking within the interrupt collector. 29:28 rsrvd3 ro 0x0 always write zeroes to this bit field. 27 enable2fiq35 rw 0x0 set this bit to one enable interrupt bit 35 as a source for the fiq. warning: disable irq for this bit prior to enabling fiq. disable = 0x0 disable enable = 0x1 enable 26 enable2fiq34 rw 0x0 set this bit to one enable interrupt bit 34 as a source for the fiq. warning: disable irq for this bit prior to enabling fiq. disable = 0x0 disable enable = 0x1 enable 25 enable2fiq33 rw 0x0 set this bit to one enable interrupt bit 33 as a source for the fiq. warning: disable irq for this bit prior to enabling fiq. disable = 0x0 disable enable = 0x1 enable 24 enable2fiq32 rw 0x0 set this bit to one enable interrupt bit 32 as a source for the fiq. warning: disable irq for this bit prior to enabling fiq. disable = 0x0 disable enable = 0x1 enable 23:21 rsrvd2 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 81 description: this register handles the overall control of the interrupt collector, including soft reset and clock gate. in addition, it handles state machine variations such as no_nesting and arm read side effect proc essing on the vector address register. example: hw_icoll_ctrl_clr(bm_icoll_ctrl_sftrst | bm_icoll_ctrl_sftrst ); 5.7.4. interrupt collector status register description the interrupt collector status register prov ides a read-only view into various inter- nal states, including the vector number of the current interupt. hw_icoll_stat 0x80000030 20 bypass_fsm rw 0x0 set this bit to one to bypass the fsm control of the request holding register and the vector address. with this bit set to one, the vector address register is continuously updated as interrupt requests come in. turn off all enable bits and walk a one through the software interrupts, observing the vector address changes. set to zero for normal operation. this control is included as a test mode and is not intended for use by a real application. normal = 0x0 normal bypass = 0x1 no fsm handshake with cpu 19 no_nesting rw 0x0 set this bit to one disable interrupt level nesting, i.e., higher priority interrupt interrupting lower priority. for normal operation, set this bit to zero. normal = 0x0 normal no_nest = 0x1 no support for interrupt nesting 18 arm_rse_mode rw 0x0 set this bit to one enable the arm-style read side effect associated with the vector address register. in this mode, interrupt inservice is signaled by the read of the hw_icoll_vector regi ster to acquire the interrupt vector address. set this bit to zero for normal operation, in which the isr signals inservice explicitly by means of a write to the hw_icoll_vector register. must_write = 0x0 must write to vector register to go in-service read_side_effect = 0x1 go in-service as a read side effect 17 fiq_final_enable rw 0x1 set this bit to one to enable the final fiq output to the cpu. set this bit to zero for testing the interrupt collector without causing actual cpu interrupts. disable = 0x0 disable enable = 0x1 enable 16 irq_final_enable rw 0x1 set this bit to one to enable the final irq output to the cpu. set this bit to zero for testing the interrupt collector without causing actual cpu interrupts. disable = 0x0 disable enable = 0x1 enable 15:0 rsrvd1 ro 0x0 always write zeroes to this bit field. table 43. hw_icoll_ctr l bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 82 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register is used to test interrup t collector state machine and its associated request holding register. example: if(hw_icoll_stat_vector_number_read() == 0x00000017) isr_vector_23(); // isr for vector 23 decimal, 17 hex 5.7.5. interrupt collector raw interrupt input register 0 description the lower 32 interrupt source states ar e visible in this read-only register. hw_icoll_raw0 0x80000040 hw_icoll_raw0_set 0x80000044 hw_icoll_raw0_clr 0x80000048 hw_icoll_raw0_tog 0x8000004c description: this register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. its purpos e is to improve diag nostic observability. example: ultest = hw_icoll_raw0.raw_irqs; table 44. hw_icoll_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 vector_number table 45. hw_icoll_stat bit field descriptions bits label rw reset definition 31:6 rsrvd1 ro 0x0 always write zeroes to this bit field. 5:0 vector_number ro 0x0 vector number of current interrupt. multiply by 4 and add to vector base address to obtain the value in hw_icoll_vector. table 46. hw_icoll_raw0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 raw_irqs table 47. hw_icoll_raw0 bit field descriptions bits label rw reset definition 31:0 raw_irqs ro 0x0 read-only view of the lower 32 interrupt request bits. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 83 5.7.6. interrupt collector raw interrupt input register 1 description the upper 32 interrupt source states ar e visible in this read-only register. hw_icoll_raw1 0x80000050 hw_icoll_raw1_set 0x80000054 hw_icoll_raw1_clr 0x80000058 hw_icoll_raw1_tog 0x8000005c description: this register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. the purp ose is to improve di agnostic ob servability. example: ultest = hw_icoll_raw0.raw_irqs; 5.7.7. interrupt collector priority register 0 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority0 0x80000060 hw_icoll_priority0_set 0x80000064 hw_icoll_priority0_clr 0x80000068 hw_icoll_priority0_tog 0x8000006c table 48. hw_icoll_raw1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 raw_irqs table 49. hw_icoll_raw1 bit field descriptions bits label rw reset definition 31:0 raw_irqs ro 0x0 read-only view of the upper 32 interrupt request bits. table 50. hw_icoll_priority0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 51. hw_icoll_priority0 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 3 force_interrupt = 0x1 force a software interrupt free datasheet http:/// STMP36XX official product documentation 5/3/06 84 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 3. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 3. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 2. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 2. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 2. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 1. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 1. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 1. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 0. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 0. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 0. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 51. hw_icoll_priority0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 85 interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(0,0x00000001); 5.7.8. interrupt collector priority register 1 description the interrupt collector priori ty register 1 provides a mechanism to specify the prior- ity level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority1 0x80000070 hw_icoll_priority1_set 0x80000074 hw_icoll_priority1_clr 0x80000078 hw_icoll_priority1_tog 0x8000007c table 52. hw_icoll_priority1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 53. hw_icoll_priority1 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 7. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 7. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 7. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 6. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 6. disable = 0x0 disable enable = 0x1 enable free datasheet http:/// STMP36XX official product documentation 5/3/06 86 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(1,0x00000001); 5.7.9. interrupt collector priority register 2 description the interrupt collector priori ty register 2 provides a mechanism to specify the prior- ity level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority2 0x80000080 hw_icoll_priority2_set 0x80000084 hw_icoll_priority2_clr 0x80000088 hw_icoll_priority2_tog 0x8000008c 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 6. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 5. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 5. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 5. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 4. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 4. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 4. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 53. hw_icoll_priority1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 87 table 54. hw_icoll_priority2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 55. hw_icoll_priority2 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 11. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 11. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 11. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 10. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 10. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 10. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 9. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 9. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 9. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 88 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(2,0x00000001); 5.7.10. interrupt collector priority register 3 description the interrupt collector priori ty register 3 provides a mechanism to specify the prior- ity level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority3 0x80000090 hw_icoll_priority3_set 0x80000094 hw_icoll_priority3_clr 0x80000098 hw_icoll_priority3_tog 0x8000009c 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 8. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 8. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 8. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 56. hw_icoll_priority3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 57. hw_icoll_priority3 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 15. force_interrupt = 0x1 force a software interrupt table 55. hw_icoll_priority2 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 89 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 15. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 15. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 14. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 14. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 14. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 13. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 13. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 13. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 12. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 12. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 12. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 57. hw_icoll_priority3 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 90 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(3,0x00000001); 5.7.11. interrupt collector priority register 4 description the interrupt collector priori ty register 4 provides a mechanism to specify the prior- ity level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority4 0x800000a0 hw_icoll_priority4_set 0x800000a4 hw_icoll_priority4_clr 0x800000a8 hw_icoll_priority4_tog 0x800000ac table 58. hw_icoll_priority4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 59. hw_icoll_priority4 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 19. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 19. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 19. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 18. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 18. disable = 0x0 disable enable = 0x1 enable free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 91 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(4,0x00000001); 5.7.12. interrupt collector priority register 5 description the interrupt collector priori ty register 5 provides a mechanism to specify the prior- ity level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority5 0x800000b0 hw_icoll_priority5_set 0x800000b4 hw_icoll_priority5_clr 0x800000b8 hw_icoll_priority5_tog 0x800000bc 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 18. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 17. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 17. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 17. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 16. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 16. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 16. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 59. hw_icoll_priority4 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 92 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 table 60. hw_icoll_priority5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 61. hw_icoll_priority5 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 23. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 23. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 23. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 22. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 22. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 22. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 21. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 21. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 21. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 93 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(5,0x00000001); 5.7.13. interrupt collector priority register 6 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority6 0x800000c0 hw_icoll_priority6_set 0x800000c4 hw_icoll_priority6_clr 0x800000c8 hw_icoll_priority6_tog 0x800000cc 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 20. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 20. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 20. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 62. hw_icoll_priority6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 63. hw_icoll_priority6 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 27. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 27. disable = 0x0 disable enable = 0x1 enable table 61. hw_icoll_priority5 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 94 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 27. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 26. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 26. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 26. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 25. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 25. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 25. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 24. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 24. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 24. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 63. hw_icoll_priority6 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 95 example: hw_icoll_priorityn_set(6,0x00000001); 5.7.14. interrupt collector priority register 7 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority7 0x800000d0 hw_icoll_priority7_set 0x800000d4 hw_icoll_priority7_clr 0x800000d8 hw_icoll_priority7_tog 0x800000dc table 64. hw_icoll_priority7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 65. hw_icoll_priority7 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 31. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 31. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 31. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 30. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 30. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 30. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 96 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(7,0x00000001); 5.7.15. interrupt collector priority register 8 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority8 0x800000e0 hw_icoll_priority8_set 0x800000e4 hw_icoll_priority8_clr 0x800000e8 hw_icoll_priority8_tog 0x800000ec 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 29. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 29. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 29. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 28. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 28. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 28. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 65. hw_icoll_priority7 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 97 table 66. hw_icoll_priority8 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 67. hw_icoll_priority8 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 35. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 35. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 35. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 34. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 34. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 34. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 33. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 33. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 33. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 98 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(8,0x00000001); 5.7.16. interrupt collector priority register 9 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority9 0x800000f0 hw_icoll_priority9_set 0x800000f4 hw_icoll_priority9_clr 0x800000f8 hw_icoll_priority9_tog 0x800000fc 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 32. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 32. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 32. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 68. hw_icoll_priority9 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 69. hw_icoll_priority9 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 39. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 39. disable = 0x0 disable enable = 0x1 enable table 67. hw_icoll_priority8 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 99 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 39. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 38. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 38. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 38. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 37. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 37. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 37. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 36. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 36. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 36. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 69. hw_icoll_priority9 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 100 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 example: hw_icoll_priorityn_set(9,0x00000001); 5.7.17. interrupt collector priority register 10 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority10 0x80000100 hw_icoll_priority10_set 0x80000104 hw_icoll_priority10_clr 0x80000108 hw_icoll_priority10_tog 0x8000010c table 70. hw_icoll_priority10 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 71. hw_icoll_priorit y10 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 43. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 43. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 43. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 42. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 42. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 42. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 101 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(10,0x00000001); 5.7.18. interrupt collector priority register 11 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority11 0x80000110 hw_icoll_priority11_set 0x80000114 hw_icoll_priority11_clr 0x80000118 hw_icoll_priority11_tog 0x8000011c 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 41. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 41. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 41. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 40. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 40. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 40. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 71. hw_icoll_priorit y10 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 102 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 table 72. hw_icoll_priority11 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 73. hw_icoll_priorit y11 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 47. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 47. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 47. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 46. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 46. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 46. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 45. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 45. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 45. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 103 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(11,0x00000001); 5.7.19. interrupt collector priority register 12 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority12 0x80000120 hw_icoll_priority12_set 0x80000124 hw_icoll_priority12_clr 0x80000128 hw_icoll_priority12_tog 0x8000012c 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 44. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 44. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 44. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 74. hw_icoll_priority12 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 75. hw_icoll_priorit y12 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 51. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 51. disable = 0x0 disable enable = 0x1 enable table 73. hw_icoll_priorit y11 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 104 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 51. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 50. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 50. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 50. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 49. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 49. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 49. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 48. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 48. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 48. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 75. hw_icoll_priorit y12 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 105 example: hw_icoll_priorityn_set(12,0x00000001); 5.7.20. interrupt collector priority register 13 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority13 0x80000130 hw_icoll_priority13_set 0x80000134 hw_icoll_priority13_clr 0x80000138 hw_icoll_priority13_tog 0x8000013c table 76. hw_icoll_priority13 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 77. hw_icoll_priorit y13 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 55. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 55. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 55. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 54. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 54. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 54. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 106 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(13,0x00000001); 5.7.21. interrupt collector priority register 14 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority14 0x80000140 hw_icoll_priority14_set 0x80000144 hw_icoll_priority14_clr 0x80000148 hw_icoll_priority14_tog 0x8000014c 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 53. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 53. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 53. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 52. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 52. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 52. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 77. hw_icoll_priorit y13 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 107 table 78. hw_icoll_priority14 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 79. hw_icoll_priorit y14 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 59. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 59. disable = 0x0 disable enable = 0x1 enable 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 59. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 58. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 58. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 58. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 57. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 57. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 57. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 108 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. example: hw_icoll_priorityn_set(14,0x00000001); 5.7.22. interrupt collector priority register 15 description this register provides a mechanism to spec ify the priority level for four interrupt sources. it also provides an enable and software interrupt for each one. hw_icoll_priority15 0x80000150 hw_icoll_priority15_set 0x80000154 hw_icoll_priority15_clr 0x80000158 hw_icoll_priority15_tog 0x8000015c 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 56. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 56. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 56. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 80. hw_icoll_priority15 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 softirq3 enable3 priority3 rsrvd3 softirq2 enable2 priority2 rsrvd2 softirq1 enable1 priority1 rsrvd1 softirq0 enable0 priority0 table 81. hw_icoll_priorit y15 bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 always write zeroes to this bit field. 27 softirq3 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request irq bit 63. force_interrupt = 0x1 force a software interrupt 26 enable3 rw 0x0 enable the interrupt bit through the collector. irq bit 63. disable = 0x0 disable enable = 0x1 enable table 79. hw_icoll_priorit y14 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 109 description: this register provides a mechanism to specify the priority associated with four interrupt bits. in addition, this register controls the enable and software-generated interrupts for the four interrupt input bits. warning: modifying the priority of an enabled interrupt may result in undefined behavior. always disable an interrupt prior to changing its priority. 25:24 priority3 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 63. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 23:20 rsrvd3 ro 0x0 always write zeroes to this bit field. 19 softirq2 rw 0x0 set this bit to one to force a software interrupt. irq bit 62. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 18 enable2 rw 0x0 enable the interrupt bit through the collector. irq bit 62. disable = 0x0 disable enable = 0x1 enable 17:16 priority2 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 62. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 15:12 rsrvd2 ro 0x0 always write zeroes to this bit field. 11 softirq1 rw 0x0 set this bit to one to force a software interrupt. irq bit 61. no_interrupt = 0x0 turn off the software interrupt request force_interrupt = 0x1 force a software interrupt 10 enable1 rw 0x0 enable the interrupt bit through the collector. irq bit 61. disable = 0x0 disable enable = 0x1 enable 9:8 priority1 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 61. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority 7:4 rsrvd1 ro 0x0 always write zeroes to this bit field. 3 softirq0 rw 0x0 set this bit to one to force a software interrupt. no_interrupt = 0x0 turn off the software interrupt request. irq bit 60. force_interrupt = 0x1 force a software interrupt 2 enable0 rw 0x0 enable the interrupt bit through the collector. irq bit 60. disable = 0x0 disable enable = 0x1 enable 1:0 priority0 rw 0x0 set the priority level for this bit, 0x3 is highest, 0x0 is lowest (weakest). irq bit 60. level0 = 0x0 level 0, lowest or weakest priority level1 = 0x1 level 1 level2 = 0x2 level 2 level3 = 0x3 level 3, highest or strongest priority table 81. hw_icoll_priorit y15 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 110 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 example: hw_icoll_priorityn_set(15,0x00000001); 5.7.23. interrupt collector interrupt v ector base address register description the interrupt collector interrupt vector base address register is used by the prior- ity logic to generate a unique vector address for each of the 64 interrupt request lines coming into the interrupt collector. the vector address is formed by multiply the interrupt bit number by 4 and adding it to the vector base address. hw_icoll_vbase 0x80000160 hw_icoll_vbase_set 0x80000164 hw_icoll_vbase_clr 0x80000168 hw_icoll_vbase_tog 0x8000016c description: this register provides a mechanism to specify the base address of the interrupt vector table. it is used in the computation of the value supplied in hw_icoll_vector register. example: hw_icoll_vbase_wr(pinterruptvectortable); 5.7.24. interrupt collector debug register 0 description the contents of this register will be defined as the ha rdware is developed. hw_icoll_debug 0x80000170 hw_icoll_debug_set 0x80000174 hw_icoll_debug_clr 0x80000178 hw_icoll_debug_tog 0x8000017c table 82. hw_icoll_vbase 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 table_address rsrvd1 table 83. hw_icoll_vba se bit field descriptions bits label rw reset definition 31:2 table_address rw 0x0 this bit field holds the upper 30 bits of the base address of the vector table. 1:0 rsrvd1 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 111 description: this register provides di agnostic visibility into the irq request state machine and its various inputs. example: table 84. hw_icoll_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 inservice level_requests requests_by_level rsrvd2 fiq irq rsrvd1 vector_fsm table 85. hw_icoll_debug bit field descriptions bits label rw reset definition 31:28 inservice ro 0x0 read-only view of the inservice bits used for nesting irqs. level0 = 0x1 level0 level1 = 0x2 level1 level2 = 0x4 level2 level3 = 0x8 level3 27:24 level_requests ro 0x0 read-only view of the requsts by priority level for the current irq. level0 = 0x1 level0 level1 = 0x2 level1 level2 = 0x4 level2 level3 = 0x8 level3 23:20 requests_by_level ro 0x0 read-only view of the requsts by priority level for the current irq. level0 = 0x1 level0 level1 = 0x2 level1 level2 = 0x4 level2 level3 = 0x8 level3 19:18 rsrvd2 ro 0x0 always write zeroes to this bit field. 17 fiq ro 0x0 read-only view of the fiq output to the cpu. no_fiq_requested = 0x0 no fiq requested fiq_requested = 0x1 fiq requested 16 irq ro 0x0 read-only view of the fiq output to the cpu. no_irq_requested = 0x0 no irq requested irq_requested = 0x1 irq requested 15:10 rsrvd1 ro 0x0 always write zeroes to this bit field. 9:0 vector_fsm ro 0x0 empty description. fsm_idle = 0x000 fsm_idle fsm_multicycle1 = 0x001 fsm_multicycle1 fsm_multicycle2 = 0x002 fsm_multicycle2 fsm_pending = 0x004 fsm_pending fsm_multicycle3 = 0x008 fsm_multicycle3 fsm_multicycle4 = 0x010 fsm_multicycle4 fsm_isr_running1 = 0x020 fsm_isr_running1 fsm_isr_running2 = 0x040 fsm_isr_running2 fsm_isr_running3 = 0x080 fsm_isr_running3 fsm_multicycle5 = 0x100 fsm_multicycle5 fsm_multicycle6 = 0x200 fsm_multicycle6 free datasheet http:/// STMP36XX official product documentation 5/3/06 112 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 if (bf_rd(icoll_debug, level_requests) != hw_icoll_debug_level_requests__level3) error(); tprintf(tp_med, ("icoll inservice = 0x%x inservice))); tprintf(tp_med, ("icoll state = 0x%x vector_fsm))); 5.7.25. interrupt collector debug read register 0 description this register always returns a known read value for debug purposes. hw_icoll_dbgread0 0x80000180 hw_icoll_dbgread0_set 0x80000184 hw_icoll_dbgread0_clr 0x80000188 hw_icoll_dbgread0_tog 0x8000018c description: this register is used to te st the read mux paths on the apbh. example: if (hw_icoll_dbgreadn_rd(0) != 0xeca94567) error(); 5.7.26. interrupt collector debug read register 1 description this register always returns a known read value for debug purposes. hw_icoll_dbgread1 0x80000190 hw_icoll_dbgread1_set 0x80000194 hw_icoll_dbgread1_clr 0x80000198 hw_icoll_dbgread1_tog 0x8000019c description: this register is used to te st the read mux paths on the apbh. example: if (hw_icoll_dbgreadn_rd(1) != 0x1356da98) table 86. hw_icoll_dbgread0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 value table 87. hw_icoll_dbgread0 bit field descriptions bits label rw reset definition 31:0 value ro 0xeca94567 fixed read-only value. table 88. hw_icoll_dbgread1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 value table 89. hw_icoll_dbgread1 bit field descriptions bits label rw reset definition 31:0 value ro 0x1356da98 fixed read-only value. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 5: interrupt collector 113 error(); 5.7.27. interrupt collector debug flag register description the interrupt collector debug flag register is used to post diagnostic state into simulation. hw_icoll_dbgflag 0x800001a0 hw_icoll_dbgflag_set 0x800001a4 hw_icoll_dbgflag_clr 0x800001a8 hw_icoll_dbgflag_tog 0x800001ac description: this register provides a posting register to synchronize c program execution and the internal simulation environment. example: bf_wr(icoll_dbgflag, flag, 3); // ... do some diagnostic action bf_wr(icoll_dbgflag, flag, 4); // ... do some more diagnostic actions bf_wr(icoll_dbgflag, flag, 5); 5.7.28. interrupt collector debug read request register 0 description the interrupt collector debug read request register 0 provides a read-only view into the low 32 bits of the request holding register. hw_icoll_dbgrequest0 0x800001b0 hw_icoll_dbgrequest0_set 0x800001b4 hw_icoll_dbgrequest0_clr 0x800001b8 hw_icoll_dbgrequest0_tog 0x800001bc table 90. hw_icoll_dbgflag 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 flag table 91. hw_icoll_dbgflag bit field descriptions bits label rw reset definition 31:16 rsrvd1 ro 0x0 always write zeroes to this bit field. 15:0 flag rw 0x0 this debug facility is probably temporary. table 92. hw_icoll_dbgrequest0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 93. hw_ico ll_dbgrequest0 bit field descriptions bits label rw reset definition 31:0 bits ro 0x0 low 32 bits of the request holding register. free datasheet http:/// STMP36XX official product documentation 5/3/06 114 chapter 5: interrupt collector 5-36xx-d1-1.02-050306 description: this register is used to test interrup t collector state machine and its associated request holding register. example: if (hw_icoll_dbgrequestn_rd(0) != 0x00000000) error(); 5.7.29. interrupt collector debug read request register 1 description the interrupt collector debug read request register 1 provides a read-only view into the high 32 bits of the request holding register. hw_icoll_dbgrequest1 0x800001c0 hw_icoll_dbgrequest1_set 0x800001c4 hw_icoll_dbgrequest1_clr 0x800001c8 hw_icoll_dbgrequest1_tog 0x800001cc description: this register is used to test interrup t collector state machine and its associated request holding register. example: if (hw_icoll_dbgrequestn_rd(n) != 0x00000000) error(); icoll xml revision: 1.51 table 94. hw_icoll_dbgrequest1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 95. hw_ico ll_dbgrequest1 bit field descriptions bits label rw reset definition 31:0 bits ro 0x0 high 32 bits of the request holding register. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 6: default first-level page table for arm926 mmu 115 6. default first-level pa ge table for arm926 mmu this chapter describes the default first-level page table for the arm926 mmu. 6.1. overview the STMP36XX contains a compact hardware implementation of a default 16-kbyte first-level page table for the mmu. this ar ea-efficient implementation allows a cost- effective alternative to allocating 16 kbytes of on-chip sram to hold this extremely sparse table. this is particularly important for applications that do not include exter- nal sdram. the default page table be gins at address 0x800c0000 and runs through 0x800c3fff, as shown in figure 19 . firmware can point the arm926 mmu?s translation base address register to this default first-level page table by loading it with 0x800c0000. 0x800c0000 arm 926 mmu translation table base register default page table entry 4095 default page table entry 4094 default page table entry 4093 default page table entry 4092 default page table entry 4091 default page table entry 4090 default page table entry 4089 default page table entry 4088 default page table entry 4087 default page table entry 4086 default page table entry 4085 default page table entry 4084 default page table entry 4083 default page table entry 4082 default page table entry 4081 default page table entry 4080 default page table entry 4088 through entry 2049 always reads back zeroes default page table entry 2048 default page table entry 0 default page table entry 2047 through entry 0001 always reads back zeroes 0x800c3ffc pio sram virtual memory unused unused 0x800c2000 arm core ahb sram default first-level page table apbh bridge usb apbh bridge 0x800c3fc0 figure 19. default first-level page table (dflpt) block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 116 chapter 6: default first-level page table for arm926 mmu 5-36xx-d1-1.02-050306 table 96. default first-level page table virtual address flpt entry # dflpt ahb address coarse secondary page table pointer fine secondary page table pointer usage, domain and ap values 0xfffxxxxx 4095 0x800c3ffc 0x0003fc00 0x0003f000 can select all four first-level descriptor options. default is v==r section covering rom at 0xffff0000. domain, ap and cb can be specified for the v==r section. 0xffexxxxx 4094 0x800c3ff8 0x0003f800 0x0003e000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xffdxxxxx 4093 0x800c3ff4 0x0003f400 0x0003d000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xffcxxxxx 4092 0x800c3ff0 0x0003f000 0x0003c000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xffbxxxxx 4091 0x800c3fec 0x0003ec00 0x0003b000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xffaxxxxx 4090 0x800c3fe8 0x0003e800 0x0003a000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xff9xxxxx 4089 0x800c3fe4 0x0003e400 0x00039000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xff8xxxxx 4088 0x800c3fe0 0x0003e000 0x00038000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xff7xxxxx 4087 0x800c3fdc 0x0003dc00 0x00037000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xff6xxxxx 4086 0x800c3fd8 0x0003d800 0x00036000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xff5xxxxx 4085 0x800c3fd4 0x0003d400 0x00035000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 6: default first-level page table for arm926 mmu 117 6.2. 16-megabyte page-mapped virtual memory (0xffxxxxxx) there are 16 1-mbyte entries in the default first-level page table that can point to second-level page tables. this makes them available for use in paged virtual mem- ory applications. each time an entry is enabled as a pointer to second-level page table, it consumes either a 1-kbyte or 4-kbyte chunk of on-chip sram at a hard- wired location in the sram. for example, entry 4095 points to the top-most 1-kbyte or 4-kbyte block of on-chip sram. most of the entries return 0x00000000. this is true for entries 0001 through 2047 and entries 2049 through 4093. 0xff4xxxxx 4084 0x800c3fd0 0x0003d000 0x00034000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xff3xxxxx 4083 0x800c3fcc 0x0003cc00 0x00033000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xff2xxxxx 4082 0x800c3fc8 0x0003c800 0x00032000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xff1xxxxx 4081 0x800c3fc4 0x0003c400 0x00031000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xff0xxxxx 4080 0x800c3fc0 0x0003c000 0x00030000 can select, unavailable, pointer to coarse secondary page table, pointer to fine secondary page table. sections are unavailable. 0xfefxxxxx - 0x801xxxxx 4079 - 2049 0x800c3fbc through 0x800c2004 0x00000000 0x00000000 these entries are never available and always return zeroes when read. 0x800xxxxx 2048 (0x800) 0x800c2000 never points to secondary page table never points to secondary page table always available, v==r section covering pio registers at 0x800xxxxx. domain, ap and cb can be specified. 0x7ffxxxxx - 0x001xxxxx 2047- 1 0x800c1ffc through 0x800c0004 0x00000000 0x00000000 these entries are never available and always return zeroes when read. 0x000xxxxx 0 0x800c0000 never points to secondary page table never points to secondary page table can select unavailable or v==r section at 0x00000000. domain, ap and cb bits not available. this is the power on default. table 96. default first-level page table (continued) virtual address flpt entry # dflpt ahb address coarse secondary page table pointer fine secondary page table pointer usage, domain and ap values free datasheet http:/// STMP36XX official product documentation 5/3/06 118 chapter 6: default first-level page table for arm926 mmu 5-36xx-d1-1.02-050306 6.2.1. default first-level page table entry 4095 the last entry in the default first-level page table is designed to allow the 1-mbyte region containing the on-chip rom image to be mapped ?virtual equal real.? this allows the rom to be accessed directly when the mmu is first turned on. alterna- tively, it can be set to point to either a coar se or fine second-level page table. only a subset of the 32 bits are actually writable . the pointers are hardwired to the top of on-chip sram and depend on the setting of bits [1:0]. at power on, it reads back 0xfff00c12. dflpt_entry4095 0x800c3ffc . table 97. first-level page table entry 4095 (0xfff00000 -0xffffffff) @ 0x800c3ffc 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x00000000 pointer to coarse page table @ 0x0003fc00 (this bit field reads back 0x0003f) ap =11 0 domain 1 cb =00 01 virtual == real section 0xfff0000 ap domain c b 10 pointer to fine page table @ 0x0003f000 (this bit field reads back 0x0003f) ap =00 domain cb =00 11 table 98. dflpt_entry4095 field descriptions bits label rw reset definition 31:12 pointer ro 0xfff00 for section, points to 0xfffxxxxx. for fine page table, points to 0x0003f000 for coarse page table, points to 0x0003fc00 11:10 ap rw 0x3 for section, set to 0x3, allowing all accesses or other value as desired. for coarse page table, always set to 0x3. for fine page table, always set to 0x0 9 always_zero ro 0x0 always reads back a zero. 8:5 domain rw 0x0 for section, set as desired. for secondary page pointers, set to zero. 4 always_one ro 0x1 always reads back a one, as required in 926 trm 3 cache rw 0x0 for section, set to desired calculability. for secondary page table pointers, set to zero. 2 buffer rw 0x0 for section, set to desired buffer ability. for secondary page table pointers, set to zero. 1:0 first_level rw 0x2 for sections, set to 0x2. for coarse page table pointer, set to 0x1. for fine page table pointer, set to 0x3 to mark the regions unavailable, set to 0x0. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 6: default first-level page table for arm926 mmu 119 6.2.2. default first-level page table entries 4094?4080 in a similar fashion, 15 additional 1-mbyte regions at the top of virtual memory can be enabled to point to second-level page tables. again, these r egisters only have a subset of the bits that can be written. for each first-level page table entry, there is a definite hardwired address that is pointe d to when the entry is enabled as a coarse or fine page table pointer. dflpt_entry4094 0x800 c3 ff8 dflpt_entry4093 0x800 c3 ff4 dflpt_entry4092 0x800 c3 ff0 dflpt_entry4091 0x800 c3 fec dflpt_entry4090 0x800 c3 fe8 dflpt_entry4089 0x800 c3 fe4 dflpt_entry4088 0x800 c3 fe0 dflpt_entry4087 0x800 c3 fdc dflpt_entry4086 0x800 c3 fd8 dflpt_entry4085 0x800 c3 fd4 dflpt_entry4084 0x800 c3 fd0 dflpt_entry4083 0x800 c3 fcc dflpt_entry4082 0x800 c3 fc8 dflpt_entry4081 0x800 c3 fc4 dflpt_entry4080 0x800 c3 fc0 table 99. first-level page table entry 4094?entry 4080 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x00000000 bits [31:9] of coarse page table, see table 96 domain 100 01 section cannot be specified, will revert to unavailable (0x00000000) 10 bits [31:9] of fine page table, see table 96 domain 100 11 table 100. dflpt_entry4094?dflpt_ entry4080 bit field descriptions bits label rw reset definition 31:9 pointer ro 0x0 bits [31:9] of coarse or fine page table power, depending on first-level setting. 8:5 domain rw 0x0 set as desired. 4:2 special_arm_value ro 0x0 for abort mode (first_level==00), this field returns a value of 0x0. for coarse page tables (first_level == 01) or fine page tables, (first_level == 11) the field returns a value of 0x4. 1:0 first_level rw 0x0 set to 0x0 to mark the regions as unavailable (register will read all zeros) set to 0x1 for coarse page table pointer set to 0x2, same effect as 0x0 set to 0x3 for fine page table pointer free datasheet http:/// STMP36XX official product documentation 5/3/06 120 chapter 6: default first-level page table for arm926 mmu 5-36xx-d1-1.02-050306 6.2.3. default first-level page table pio register map entry 2048 the 1-mbyte pio region at physical ad dress 0x800xxxxx is ma pped ?virtual equal real? by the default first-level pa ge table entry_2048, as shown below. dflpt_entry_2048 0x800c2000 table 101. first-level page table entr y 2048 (0x80000000 -0x800fffff) @ 0x800c2000 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 virtual == real section, i.e., 0x80000 ap 0 domain 1 c b 10 table 102. dflpt_entry2048 bit field descriptions bits label rw reset definition 31:12 pointer ro 0x80000 this section points to 0x80000000 and is always available. 11:10 ap rw 0x3 initially set to 0x3 for allowing all acce sses, set to other values as desired. 9 always_zero ro 0x0 always reads back a zero. 8:5 domain rw 0x0 set as desired. 4 always_one ro 0x1 always reads back a one, as required in 926 trm 3 cache rw 0x0 set to desired cachability. 2 buffer rw 0x0 set to desired bufferability. 1:0 first_level ro 0x2 always reads back 0x2 for section descriptor. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 6: default first-level page table for arm926 mmu 121 6.2.4. default first-level page table entry 0000 v==r sram access finally, the sram at physical address 0x 0000000 can be mapped ?virtual equal real?, if desired. when enabled, this locati on reads back as a first-level page table section descriptor with a 32-bit value of 0x00000c12. when disabled, it reads back 0x0000000 to abort any access attempts. dflpt_entry_0000 0x800c0000 table 103. first-level page table entr y 0000 (0x00000000 -0x000fffff) @ 0x800c0000 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x00000000 virtual == real section, i.e., 0x00000c12 s e c t i o n 0 table 104. dflpt_entry0000 bit field descriptions bits label rw reset definition 31:2 pointer ro 0x0x0000304 for section, points to 0x000000000. with ap==3, domain==0, always_one, non cached, non-buffered. otherwise unavailable (returns all zeroes). 1 section rw 0x1 set to one to enable sram at address 0x00000000. if set to zero, the address returns 0x00000009. 0 always_zero ro 0x0 always reads back a zero. free datasheet http:/// STMP36XX official product documentation 5/3/06 122 chapter 6: default first-level page table for arm926 mmu 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 123 7. digital control and on-chip ram this chapter describes the digital control block and the on-chip ram features of the STMP36XX. it includes sections on cont rolling the sram, rom, performance moni- tors, high-entropy pseudo-random numb er seed, and free-running microseconds counter. programmable registers for the block are described in section 7.6 . 7.1. overview the digital control block provides overall control of various items within the top digi- tal block of the chip, including the on-chip ram controls, default page-table controls, and hclk performance counter, as shown in figure 20 . the on-chip ram is constructed from an array of six-transistor dynamic ram bit cells. the repair functions of this sram are controlled by registers in the digctl block. clkgen (hclk) digctl pio programmable registers arm core ahb slave ahb shared dma ahb master apbh master ahb-to-apbh bridge sram e_fuse fsm apbh sram revision ahb arb. perf. monitors entropy pswitch laser fuses rom shield figure 20. digital contro l (digctl) block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 124 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 7.2. sram controls the on-chip ram is based on a six-transistor dynamic ram cell. it is implemented in four segments of 64 kbytes each (4 by 16kx32), as shown in figure 21 . a 32-bit ahb address is converted to an sram macrocell address, as shown in table 105 . accessing on-chip ram over the bus requ ires only one initial wait state for arbitration. the on-chip ram includes some redundancy for ram repair. each segment con- tains two spare columns that can be substituted for failures. the macrocell contains eight 7-bit e_fuse registers that control the repair circ uitry. the macrocell documen- tation refers to these as e_fuse registers, because it was originally designed to work with electric fused repair information. in this application, the repair information is stored in conventional flip-flops by firmware. the interface to the e_fuse repair regis- ters is serial. a state machine in the digctl block shifts the 56 bits of repair data into the on-chip ram macrocell. software runs the bist algorithm hardware and determines the proper corrections. it loads the repair in formation into the hw_digctl_ramrepair0 and hw_digct l_ramrepair1 registers and sets hw_digctl_ramctrl_repair_transmit. software must wait until table 105. on-chip ram address bits (within macrocell) ahb addr bits macro cell bits usage description 71:16 15:14 segment address selects one 64-kbyte segment 15:11 13:9 row address selects a row in the array 10:7 8:5 column address selects a column in the array 6:2 4:0 bank address selects a bank in the array 0x00000000 on-chip ram segment 3 (64 kbytes) on-chip ram segment 2 (64 kbytes) on-chip ram segment 1 (64 kbytes) on-chip ram segment 0 (64 kbytes) 0x0000ffff 0x00010000 0x0001ffff 0x00020000 0x0002ffff 0x00030000 0x0003ffff figure 21. on-chip ram partitioning free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 125 hw_digctl_ramctrl_repair_status retu rns to zero before attempting to use the on-chip ram. see figure 22 . to substitute a spare column, a 7-bit e_fuse register is loaded with the defective bank and column number and the valid is set, as shown in ta b l e 1 0 6 . once this information has been shifted into the on-chip ram macrocell, then the redundant column is used for subsequent accesses. table 106. e_fuse control for one 64-kbyte bank of on-chip ram bits label definition 6 e_fuse_valid set to one to mark a valid e_fuse entry. 5:1 defective_bank address[4:0] of the defective locations. 0 defective_column address[5] of the defective locations. segment 3 seg3_efuse1 seg3_efuse0 segment 2 seg2_efuse1 seg2_efuse0 segment 1 seg1_efuse1 seg1_efuse0 segment 0 seg0_efuse1 seg0_efuse0 on-chip ram hw_digctl_ramrepair0 efuse1 efuse0 efuse2 efuse3 hw_digctl_ramrepair1 efuse1 efuse0 efuse2 efuse3 digctl figure 22. on-chip ram e_fuse control free datasheet http:/// STMP36XX official product documentation 5/3/06 126 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 7.2.1. sram bist control the sram has a built-in self-test (bist) engine that tests ram using algorithms defined by mosys, the supplier for the ip. the bist performs a 10n test using row fast addressing, followed by a 10n test in column fast addressing, followed by a retention test using row fast addressing. the 10n tests use 0 and f data, and the retention test uses 5 and a data. the sram has four blocks, each of wh ich contain 32 banks and one redundant bank. the redundant bank can be used to re pair the ram. there are two sub-blocks in each block that can be switched in for repair, for a total of eight values that can be shifted into the ram to repair eight sub-blocks. the sram bist engine tests the ram and stores information on eight unique fail- ing addresses that can be used for the repair, two for each block in registers in the digctl block. these are the hw_digctl_1tbist_repair0 and hw_digctl_1tbist_repair1 registers. th is data can be transferred directly to the hw_digctl_ramrepair0 and hw_d igclt_ramrepair1 registers and transferred to the sram for the repair. the sram bist operation is started by setting the bist_start bit in the hw_digctl_1tbist_csr register. this st arts the bist operation, and, when completed, the bist_done signal in this re gister is set. this register also contains the results of the bist in the bist_pass and bist_fail bits. additional information on the fails is provided in the bits shown in table 107 . the 14 status registers containi ng fail informati on are listed in table 108 . table 107. bist fail table bit description fail_block_0_0 set for the second fail in block 0 fail_block_1_0 set for the first fail in block 1 fail_block_1_1 set for the second fail in block 1 fail_block_2_0 set for the first fail in block 2 fail_block_2_1 set for the second fail in block 2 fail_block_3_0 set for the first fail in block 3 fail_block_3_1 set for the second fail in block 3 table 108. bist fail register information register information hw_digctl_1tbist_status0 contains fail data for fail1 of block 0 hw_digctl_1tbist_status1 contains fail data for fail2 of block 0 hw_digctl_1tbist_status2 contains fail data for fail1 of block 1 hw_digctl_1tbist_status3 contains fail data for fail2 of block 1 hw_digctl_1tbist_status4 contains fail data for fail1 of block 2 hw_digctl_1tbist_status5 contains fail data for fail2 of block 2 hw_digctl_1tbist_status6 contains fail data for fail1 of block 3 hw_digctl_1tbist_status7 contains fail data for fail2 of block 3 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 127 this data can be used for debug and analysis. 7.3. rom controls the on-chip rom contains a shielded 2-kbyte area, 0xffff0800?0xffff0fff, that is used to hold various decryption and authentication keys used by the boot loader to certify a legal b oot image into the trust zone. this area can be shielded from view by writing to the hw_d igctl_romshield_write_once bit. this shields the keys from further reading. the bit is a write-once op eration, i.e., the rom cannot be unshielded until the next chip-wide reset event. note : the shield is also raised, automatically, when the jtag debugger is detected, as evidenced by a number of jtag clock rising-edges being detected. 7.4. miscellaneous controls the digital control block also contains a number of other miscellaneous functions, as detailed in this section. 7.4.1. performance monitoring the digital control block contains several registers for performance monitoring, including hw_digctl_hclkcount, which co unts hclk rising edges. this regis- ter counts at a variable rate as the hw_clkctrl_hbusclkctrl_auto_slow _down is enabled. the hw_digctl_ahbstalled and hw_digctl_ahbcycles registers can be used to measure ahb bus utiliz ation. the stalled register counts all cycles in which any device has an outstanding and unfulfilled bus operation in flight. the cycles reg- ister counts the number of data transfer cycl es. subtract cycles from stalls to deter- mine under utilized bus cycles. these counters can be us ed to tune the performance of the hclk frequency for spec ific activities. in addition, these moni- tors can be focus on specific masters. see the hw_digctl_ctrl _master_select bit description, for example. 7.4.2. high-entropy prn seed a 32-bit entropy register begins runni ng a pseudo-random number algorithm from the time reset is removed until the pswitch is released by the user. this high- entropy value can be used as the seed for other pseudo-random number genera- tors. hw_digctl_1tbist_status8 contains fail address of fail 1 and 2 for block 0 hw_digctl_1tbist_status9 contains fail address of fail 1 and 2 for block 1 hw_digctl_1tbist_status10 contains fail address of fail 1 and 2 for block 1 hw_digctl_1tbist_status11 contains fail address of fail 1 and 2 for block 3 hw_digctl_1tbist_status12 contains the state in which fail occurred for fails 1 and 2 of blocks 0 and 1 hw_digctl_1tbist_status13 contains the state in which fail occurred for fails 1 and 2 of blocks 2 and 3 table 108. bist fail register information (continued) register information free datasheet http:/// STMP36XX official product documentation 5/3/06 128 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 7.4.3. write-once register a 32-bit write-once register holds a runt ime-derived locked seed. once written, it cannot be changed until the next chip wide reset event. the contents of this register are frequently derived from the entropy register. 7.4.4. microseconds counter a 32-bit free-running microsec onds counter provides fine-gr ain real-time control. its period is determined by dividing the 24.0-m hz crystal oscillator by 24. thus, its fre- quency does not change as hclk, xclk , and the processor clock frequency are changed. 7.5. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 7.6. programmable registers the following registers provide control of all programmable elements of the digital control block. 7.6.1. digctl control register description the digctl control register provides overall control of various functions through- out the digital portion of the chip. hw_digctl_ctrl 0x8001c000 hw_digctl_ctrl_set 0x8001c004 hw_digctl_ctrl_clr 0x8001c008 hw_digctl_ctrl_tog 0x8001c00c table 109. hw_digctl_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd3 master_select rsvd2 usb_testmode analog_testmode digital_testmode utmi_testmode uart_loopback rsvd1 debug_disable usb_clkgate jtag_shield package_sense_enable free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 129 description: this register controls various functions throughout the digital portion of the chip. table 110. hw_digctl_ct rl bit field descriptions bits label rw reset definition 31:29 rsvd3 ro 0x0 always write zeroes to this bit field. 28:24 master_select rw 0x0 set various bits of this bit field to one to enable performance monitoring in the ahb arbiter for the corresponding ahb master. arm_i = 0x01 select arm i master. arm_d = 0x02 select arm d master. apbh = 0x04 select apbh dma master. apbx = 0x08 select apbx dma master. usb = 0x10 select usb master. 23:21 rsvd2 ro 0x0 always write zeroes to this bit field. 20 usb_testmode rw 0x0 reserved. always write a 0 to this bit field. 19 analog_testmode rw 0x0 reserved. always write a 0 to this bit field. 18 digital_testmode rw 0x0 reserved. always write a 0 to this bit field. 17 utmi_testmode rw 0x0 reserved. always write a 0 to this bit field. 16 uart_loopback rw 0x0 set this bit to one to loop the two uarts back on themselves in a null modem configuration. normal = 0x0 no loopback. loopit = 0x1 loop the debug uart and the application uart together. 15:4 rsvd1 ro 0x0 always write zeroes to this bit field. 3 debug_disable rw 0x0 set this bit to one to disable the arm core's debug logic (for power savings). th is bit must remain zero following power-on reset for normal jtag debugger operation of the arm core. when set to one, it gates off the clocks to the arm core 's debug logic. once this bit is set, the part must undergo a power-on reset to re- enable debug operation. manually clearing this bit via a write after it has been set produces unknown results. 2 usb_clkgate rw 0x1 this bit must be set to zero for normal operation of the usb controller. when set to one, it gates off the clocks to the usb controller. run = 0x0 allow usb to operate normally. no_clks = 0x1 do not clock usb gates in order to minimize power consumption. 1 jtag_shield rw 0x1 this bit is set to one by laser fuse to disable the jtag debugger during boot rom execution. it is set to zero at the end of boot rom ex ecution, just before branching to the loaded code. normal = 0x0 jtag debugger enabled. shields_up = 0x1 jtag debugger disabled. 0 package_sense_enable rw 0x0 set this bit to one to enable the pullup resistor on the package-type sense pad. this pad is floating in 100- pin packages; therefore turn ing on the pullup will cause the package_type sensor to read back a one. the pad is bonded to ground in 169-pin packages so that a zero is read back by the sensor. disable = 0x0 disable the package-sense pullup resistor. enable = 0x1 enable the package-sense pullup resistor. free datasheet http:/// STMP36XX official product documentation 5/3/06 130 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 example: hw_digctl_ctrl_clr(bm_digctl_ctrl_usb_clkgate); // enable usb clock 7.6.2. digctl status register description the digctl status register reports status for the digital control block. hw_digctl_status 0x8001c010 hw_digctl_status_set 0x8001c014 hw_digctl_status_clr 0x8001c018 hw_digctl_status_tog 0x8001c01c description: the status register provies a read-only vi ew to various input conditions and internal states. example: if(hw_digctl_status.package_type) table 111. hw_digctl_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rom_keys_present rsvd1 jtag_shield_default rom_shielded jtag_in_use pswitch package_type written table 112. hw_digctl_stat us bit field descriptions bits label rw reset definition 31 rom_keys_present ro 0x1 this read-only bit field returns a one if the rom key set is available. otherwise, it returns a zero. 30:7 rsvd1 ro 0x0 reserved. 6 jtag_shield_default ro 0x0 this read-only bit is a one if the jtag shield default all layer change bit is a one. 5 rom_shielded ro 0x0 this read-only bit is a on e if the rom shield is raised so that the last 2k bytes cannnot be read. 4 jtag_in_use ro 0x0 this read-only bit is a one if jtag debugger usage has been detected. 3:2 pswitch ro 0x0 these read-only bits reflect the current state of the pswitch comparators. 1 package_type ro 0x0 this read-only bit returns a one in 100-pin packages. it reads back a zero in 169-pin packages. 0 written ro 0x0 set to one by any successful write to the hw_writeonce register. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 131 { // do 100-pin package things } 7.6.3. free-running hclk counter register description this free-running counter is ava ilable for performance metrics. hw_digctl_hclkcount 0x8001c020 hw_digctl_hclkcount_set 0x8001c024 hw_digctl_hclkcount_clr 0x8001c028 hw_digctl_hclkcount_tog 0x8001c02c description: this counter increments once per hclk rising edge. example: starttime = hw_digctl_hclkcount; // do something you want timed here endtime = hw_digctl_hclkcount; duration = endtime - starttime; // make sure to handle rollover in a real application 7.6.4. on-chip ram control register description the on-chip ram control register hold s on-chip sram control bit fields. hw_digctl_ramctrl 0x8001c030 hw_digctl_ramctrl_set 0x8001c034 hw_digctl_ramctrl_clr 0x8001c038 hw_digctl_ramctrl_tog 0x8001c03c table 113. hw_digctl_hclkcount 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 count table 114. hw_digctl_hclkco unt bit field descriptions bits label rw reset definition 31:0 count ro 0x0 this counter counts up from reset using hclk. table 115. hw_digctl_ramctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd5 test_margin pwdn_banks rsvd4 temp_sensor rsvd3 test_temp_comp rsvd2 shift_count flip_clk rsvd1 over_ride_temp ref_clk_gate repair_status repair_transmit free datasheet http:/// STMP36XX official product documentation 5/3/06 132 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 table 116. hw_digctl_ramctrl bit field descriptions bits label rw reset definition 31 rsvd5 ro 0x0 reserved. 30:28 test_margin rw 0x0 set these bits to various test margin levels to the sram tls bits. normal = 0x0 normal operation. level1 = 0x1 test mode level 1. level2 = 0x2 test mode level 2. level3 = 0x3 test mode level 3. level4 = 0x4 test mode level 4. level5 = 0x5 test mode level 5. level6 = 0x6 test mode level 6. level7 = 0x7 test mode level 7. 27:24 pwdn_banks rw 0x0 powers down the sram banks. each bit powers down 64kb of sram. pwdn_bank3 = 0x8 set to one to power down bank3, i.e., 0x00030000 through 0x0003ffff. pwdn_bank2 = 0x4 set to one to power down bank2, i.e., 0x00020000 through 0x0002ffff. pwdn_bank1 = 0x2 set to one to power down bank1, i.e., 0x00010000 through 0x0001ffff. pwdn_bank0 = 0x1 set to one to power down bank0, i.e., 0x00000000 through 0x0000ffff. 23 rsvd4 ro 0x0 reserved. 22:20 temp_sensor ro 0x7 three-bit temperature code from the on-chip temperature sensor. this value can be automatically copied into test_temp_comp 19 rsvd3 ro 0x0 reserved. 18:16 test_temp_comp rw 0x7 temperature compensation for ram repair. 0=normal mode (default). during ram test and repair, the die temperature must be written to this field. temperature is determined using on-chip temperature sensor (see lradc). low_temp = 0x1 temperature less than 15c. range_a = 0x2 temperature 15c to 25c. range_b = 0x3 temperature 25c to 35c. range_c = 0x4 temperature 35c to 45c. range_d = 0x5 temperature 45c to 55c. range_e = 0x6 temperature 55c to 70c. range_f = 0x7 temperature great than 70c. 15 rsvd2 ro 0x0 reserved. 14:8 shift_count ro 0x0 this read-only bit field reads back the state of the shift counter. the lsb toggles to generate an efuse_clk. 7 flip_clk rw 0x0 use the opposite edge for efuse_clk. normal = 0x0 normal rising edge. invert = 0x1 inverted, i.e., falling edge. 6:4 rsvd1 ro 0x0 reserved. 3 over_ride_temp rw 0x0 normally, the three-bit hardware temperature sensor value is copied into the test_temp_code register automatically. set to one to override the copying of the on-chip temperature sensor value into the test_temp_comp bit field. the value in test_temp_comp always drives the temperature inputs to the on-chip ram. normal = 0x0 normal operation, provide hardware temperature sensor value to on-chip ram (default). over_ride = 0x1 firmware-supplied value in test_temp_comp is not modified by hardware. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 133 description: this register controls various parts of the on-chip ram, including the repair state machine that shifts the repair configuration data into the sram macro-cell. example: hw_digctl_ramctrl_set(bm_digctl_ramctrl_repair_transmit); // start the efuse state machine 7.6.5. on-chip ram repair data 0 register description the on-chip ram repair data 0 register holds repair data for the on-chip sram. hw_digctl_ramrepair0 0x8001c040 hw_digctl_ramrepair0_set 0x8001c044 hw_digctl_ramrepair0_clr 0x8001c048 hw_digctl_ramrepair0_tog 0x8001c04c 2 ref_clk_gate rw 0x0 gate the 32-khz reference clock. this should be left at 0. normal = 0x0 normal operation, provide reference clock to the macro (default). off = 0x1 turn off the refresh clock. 1 repair_status ro 0x0 sram repair transmission in progress. do not access the sram while this bit is set. idle = 0x0 e_fuse transfer complete. busy = 0x1 e_fuse transer in progress. 0 repair_transmit rw 0x0 transmit repair data to on-chip ram. serially sends the ram repair data to the on-chip ram. the on-chip ram should not be accessed while the repair data is being transmitted. idle = 0x0 no transfer. send = 0x1 send e_fuse data serially to the on-chip ram. table 117. hw_digctl_ramrepair0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd4 efuse3 rsvd3 efuse2 rsvd2 efuse1 rsvd1 efuse0 table 118. hw_digctl_ramrep air0 bit field descriptions bits label rw reset definition 31 rsvd4 ro 0x0 reserved, always set to zero. 30:24 efuse3 rw 0x0 sram repair efuse register bits 6 through 0 for segment 1 efuse 1. this data and the data field in sram_repair1 are shifted to the sram controller when the repair_transmit bit in sram_ctrl is set. 23 rsvd3 ro 0x0 reserved, always set to zero. table 116. hw_digctl_ramctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 134 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 description: this register contains the efuse repair configuration information that can be shifted into the lower two 64-kbyte banks of the on-chip ram. example: hw_digctl_ramrepair0.efuse0= 0x2a; // read modify write is ok 7.6.6. on-chip ram repair data 1 register description the on-chip ram repair data 1 register holds repair data for the on-chip sram hw_digctl_ramrepair1 0x8001c050 hw_digctl_ramrepair1_set 0x8001c054 hw_digctl_ramrepair1_clr 0x8001c058 hw_digctl_ramrepair1_tog 0x8001c05c 22:16 efuse2 rw 0x0 sram repair efuse register bits 6 through 0 for segment 1 efuse 0. this data and the data field in sram_repair1 are shifted to the sram controller when the repair_transmit bit in sram_ctrl is set. 15 rsvd2 ro 0x0 reserved, always set to zero. 14:8 efuse1 rw 0x0 sram repair efuse register bits 6 through 0 for segment 0 efuse 1. this data and the data field in sram_repair1 are shifted to the sram controller when the repair_transmit bit in sram_ctrl is set. 7 rsvd1 ro 0x0 reserved, always set to zero. 6:0 efuse0 rw 0x0 sram repair efuse register bits 6 through 0 for segment 0 efuse 0. this data and the data field in sram_repair1 are shifted to the sram controller when the repair_transmit bit in sram_ctrl is set. table 119. hw_digctl_ramrepair1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd4 efuse3 rsvd3 efuse2 rsvd2 efuse1 rsvd1 efuse0 table 118. hw_digctl_ramrep air0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 135 description: this register contains the efuse repair configuration information that can be shifted into the upper two 64-kbyte banks of the on-chip ram. example: hw_digctl_ramrepair1.efuse0= 0x37; // read modify write is ok 7.6.7. software write-once register description the software write once register hold the value used in software certification man- agement. hw_digctl_writeonce 0x8001c060 table 120. hw_digctl_ramre pair1 bit field descriptions bits label rw reset definition 31 rsvd4 ro 0x0 reserved, always set to zero. 30:24 efuse3 rw 0x0 sram repair efuse register bits 6 through 0 for segment 3 efuse 1. this data and the data field in sram_repair1 are shifted to the sram controller when the repair_transmit bit in sram_ctrl is set. 23 rsvd3 ro 0x0 reserved, always set to zero. 22:16 efuse2 rw 0x0 sram repair efuse register bits 6 through 0 for segment 3 efuse 0. this data and the data field in sram_repair1 are shifted to the sram controller when the repair_transmit bit in sram_ctrl is set. 15 rsvd2 ro 0x0 reserved, always set to zero. 14:8 efuse1 rw 0x0 sram repair efuse register bits 6 through 0 for segment 2 efuse 1. this data and the data field in sram_repair1 are shifted to the sram controller when the repair_transmit bit in sram_ctrl is set. 7 rsvd1 ro 0x0 reserved, always set to zero. 6:0 efuse0 rw 0x0 sram repair efuse register bits 6 through 0 for segment 2 efuse 0. this data and the data field in sram_repair1 are shifted to the sram controller when the repair_transmit bit in sram_ctrl is set. table 121. hw_digctl_writeonce 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits free datasheet http:/// STMP36XX official product documentation 5/3/06 136 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 description: this register is used to hold a portion of a certificate that is not mutable after soft- ware initialization. example: hw_digctl_writeonce.u = my_certificate; 7.6.8. ahb transfer count register description the ahb transfer count register counts the number of transfers made on the ahb. hw_digctl_ahbcycles 0x8001c070 description: this counter increments on ahb cycl es when the arbiter sees hready and a master has an active htrans code in pr ocess, i.e., a clock in which data was read or written between a master and a slave. it ignores cycles in which a master was granted access but the slave was not ready. the master selects in hw_digctl_ctrl_master_select are used in the arbiter to mask which master's cycles are actually recorded here. example: starttime = hw_digctl_hclkcount_rd(); while(hw_digctl_ahbcycles.count less than 1000000) { // wait for a specific number of xfers } elapsedtime = hw_digctl_hclkcount_rd() - starttime; 7.6.9. ahb performance metric for sta lled bus cycles register description used for ahb bus utilization measuremen ts, the ahb performance metric for stalled bus cycles register counts the number of stalled ahb cycles. hw_digctl_ahbstalled 0x8001c080 table 122. hw_digctl_writeonce bit field descriptions bits label rw reset definition 31:0 bits rw 0xa5a5a5a5 this field can be written only one time. the contents are not used by hardware. table 123. hw_digctl_ahbcycles 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 count table 124. hw_digctl_ahbcycles bit field descriptions bits label rw reset definition 31:0 count rw 0x0 this field contains t he count of ahb bus cycles during which data was actually transferred from a master to a slave or from a slave to a master. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 137 description: this field counts the number of ahb cy cles in which a master was requesting a transfer, and the slave had not responded. this includes cycles in which it was requesting transfers but was not granted them, as well as cycles in which it was granted and driving the bus but the ta rgeted slave was not ready. the master selects in hw_digctl_ctrl_master_selec t are used in the arbiter to mask which master's cycles are actually recorded here. example: numberstalledcycles = hw_digctl_ahbstalled_count_rd(); 7.6.10. entropy register description the entropy register is a read-only test value register. hw_digctl_entropy 0x8001c090 description: empty description. example: while(hw_digctl_status.pswitch != 0) { //wait for pswitch to go away } hw_digctl_writeonce.bits = rand(hw_digctl_entropy.value); table 125. hw_digctl_ahbstalled 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 count table 126. hw_digctl_ahbstalled bit field descriptions bits label rw reset definition 31:0 count rw 0x0 this field counts the nu mber of ahb cycles in which a master was stalled. table 127. hw_digctl_entropy 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 value table 128. hw_digctl_entropy bit field descriptions bits label rw reset definition 31:0 value ro 0x0 this read-only bit field always reads back the results of an entropy calculation. it is used to randomize the seeds for random number generators. free datasheet http:/// STMP36XX official product documentation 5/3/06 138 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 7.6.11. digital control rom shield read enable register description the digital control rom shield read enab le register is a writ e-once register for disabling key set reads from the on-chip rom. hw_digctl_romshield 0x8001c0a0 description: the rom shield is raised before the boot loader loads external code. it is also automatically raised when the jtag debugger is detected. example: hw_digctl_romshield_set(bm_digctl_romshield_set_write_once); 7.6.12. digital control microseconds counter register description the digital control microseconds counter register is a read-only test value regis- ter. hw_digctl_microseconds 0x8001c0b0 hw_digctl_microseconds_set 0x8001c0b4 hw_digctl_microseconds_clr 0x8001c0b8 hw_digctl_microseconds_tog 0x8001c0bc table 129. hw_digctl_romshield 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 write_once table 130. hw_digctl_roms hield bit field descriptions bits label rw reset definition 31:1 rsvd1 ro 0x0 always write zeroes to this bit field. 0 write_once rw 0x0 set this bit to one to disable reading the boot loader encryption keys, whic h occupy rom addresses 0xffff0800 - 0xffff0fff. this bit can written once only. it is written from wit hin rom code, so that access to the boot loader keys are denied to all loaded code. any attempt to read this shielded memory will return 0xbebebebe (which represents a debugger breakpoint). table 131. hw_digctl_microseconds 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 value free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 139 description: this fixed-rate timer always increments at 24.0 mhz divided by 24 or 1.0 mhz. it does not generate an interrupt. example: starttime = hw_digctl_microseconds_rd(); endtime = hw_digctl_microseconds_rd(); elapsedtime = starttime - endtime; // warning, handle rollover in real software 7.6.13. digital control debug read test register description the digital control debug read test regi ster is a read-only test value register. hw_digctl_dbgrd 0x8001c0c0 description: this register is used for debugging purposes. example: debug_value = hw_digctl_dbgrd_rd(); 7.6.14. digital control debug register description the digital control debug register is a read-only test value register. hw_digctl_dbg 0x8001c0d0 table 132. hw_digctl_microsec onds bit field descriptions bits label rw reset definition 31:0 value rw 0x0 this register maintains a 32-bit counter that increments at a one-microsecond rate. the 1-mhz clock driving this counter is derived from the 24.0-mhz crystal osillator. the count value is not preserved over power downs. the 32-bit value wraps in less than two hours. note that the digital control microseconds counter register does not reliably increment when hclk is set to less than 3 mhz. table 133. hw_digctl_dbgrd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 complement table 134. hw_digctl_dbg rd bit field descriptions bits label rw reset definition 31:0 complement ro 0x789abcde this read-only bit field always reads back the ones complement of the value in hw_digctl_dbg. table 135. hw_digctl_dbg 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 value free datasheet http:/// STMP36XX official product documentation 5/3/06 140 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 description: this register is used for debugging purposes. example: debug_value = hw_digctl_dbg_rd(); 7.6.15. sram bist control and status register description the sram bist control and status register provides overall control of the inte- grated bist engine. hw_digctl_1tram_bist_csr 0x8001c0e0 hw_digctl_1tram_bist_csr_set 0x8001c0e4 hw_digctl_1tram_bist_csr_clr 0x8001c0e8 hw_digctl_1tram_bist_csr_tog 0x8001c0ec description: this register is used to start off the bi st operation on two rams in the dma block. the status signals are returned after the bist operation is completed to this regis- ter. example: to start the bist operation, set hw_digctl_1tram_bist_csr = 0x00000001. after the bist is completed and the test passes, the contents of hw_digctl_1tram_bist_csr will be 0x00000007, as the done and pass flags will be set. 7.6.16. sram bist repair register 0 description the sram bist repair register 0 contains the repair data for blocks 0 and 1 hw_digctl_1tram_bist_repair0 0x8001c0f0 table 136. hw_digctl_dbg bit field descriptions bits label rw reset definition 31:0 value ro 0x87654321 this read-only bit field always reads back the fixed value 0x87654321. table 137. hw_digctl_1tram_bist_csr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 fail pass done start table 138. hw_digctl_1tram_bi st_csr bit field descriptions bits label rw reset definition 31:4 rsvd0 ro 0x0 reserved 3 fail ro 0x0 bist has failed 2 pass ro 0x0 bist has passed 1 done ro 0x0 bist has completed 0 start rw 0x0 initiate bist of internal memory when high free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 141 hw_digctl_1tram_bist_repair0_set 0x8001c0f4 hw_digctl_1tram_bist_repair0_clr 0x8001c0f8 hw_digctl_1tram_bist_repair0_tog 0x8001c0fc description: this register contains the repair information for blocks 0 and 1 for the sram. it needs to be just loaded into the ram repair register 0. example: register will contain 0x00000000 for no repair. register will contain 0x00000042 for a repair on bank address 1 and col lsb 0, for block 0. register will contain 0x00004942 for a repair to bank address 4 and col lsb 1, for block 0 in addition. 7.6.17. sram bist repair register 1 description the sram bist repair register 1 contains the repair data for blocks 2 and 3 hw_digctl_1tram_bist_repair1 0x8001c100 hw_digctl_1tram_bist_repair1_set 0x8001c104 hw_digctl_1tram_bist_repair1_clr 0x8001c108 hw_digctl_1tram_bist_repair1_tog 0x8001c10c description: this register contains the repair information for blocks 2 and 3 for the sram. it needs to be just loaded into the ram repair register 1. example: register will contain 0x00000000 for no repair. register will contain 0x00000042 for a repair on bank address 1 and col lsb 0, for block 2. register will contain 0x00004942 for a repair to bank address 4 and col lsb 1, for block 2 in addition. table 139. hw_digctl_1tram_bist_repair0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 table 140. hw_digctl_1tram_bist _repair0 bit field descriptions bits label rw reset definition 31:0 rsvd0 ro 0x0 this bit will always be set to 0 table 141. hw_digctl_1tram_bist_repair1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 table 142. hw_digctl_1tram_bist _repair1 bit field descriptions bits label rw reset definition 31:0 rsvd0 ro 0x0 this bit will always be set to 0 free datasheet http:/// STMP36XX official product documentation 5/3/06 142 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 7.6.18. sram status register 0 description the sram status register 0 is a read-only fail data register. hw_digctl_1tram_status0 0x8001c110 hw_digctl_1tram_status0_set 0x8001c114 hw_digctl_1tram_status0_clr 0x8001c118 hw_digctl_1tram_status0_tog 0x8001c11c description: this register will contain fail data for the first fail in block 0. example: fail_data = hw_digctl_1tram_status0_rd(); 7.6.19. sram status register 1 description the sram status register 1 is a read-only fail data register. hw_digctl_1tram_status1 0x8001c120 hw_digctl_1tram_status1_set 0x8001c124 hw_digctl_1tram_status1_clr 0x8001c128 hw_digctl_1tram_status1_tog 0x8001c12c description: this register will contain fail data for the second fail in block 0. example: fail_data = hw_digctl_1tram_status1_rd(); table 143. hw_digctl_1tram_status0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 faildata00 table 144. hw_digctl_1tram_status0 bit field descriptions bits label rw reset definition 31:0 faildata00 ro 0x0 this read-only bit field will contain the fail data for the first fail in block 0. table 145. hw_digctl_1tram_status1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 faildata01 table 146. hw_digctl_1tram_status1 bit field descriptions bits label rw reset definition 31:0 faildata01 ro 0x0 this read-only bit field will contain the fail data for the second fail in block 0. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 143 7.6.20. sram status register 2 description sram status register 2 is a read-only fail data register. hw_digctl_1tram_status2 0x8001c130 hw_digctl_1tram_status2_set 0x8001c134 hw_digctl_1tram_status2_clr 0x8001c138 hw_digctl_1tram_status2_tog 0x8001c13c description: this register will contain fail data for the first fail in block 1. example: fail_data = hw_digctl_1tram_status2_rd(); 7.6.21. sram status register 3 description ram status register 3 is a read-only fail data register. hw_digctl_1tram_status3 0x8001c140 hw_digctl_1tram_status3_set 0x8001c144 hw_digctl_1tram_status3_clr 0x8001c148 hw_digctl_1tram_status3_tog 0x8001c14c description: this register will contain fail data for the second fail in block 1. example: fail_data = hw_digctl_1tram_status3_rd(); table 147. hw_digctl_1tram_status2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 faildata10 table 148. hw_digctl_1tram_status2 bit field descriptions bits label rw reset definition 31:0 faildata10 ro 0x0 this read-only bit field will contain the fail data for the first fail in block 1. table 149. hw_digctl_1tram_status3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 faildata11 table 150. hw_digctl_1tram_status3 bit field descriptions bits label rw reset definition 31:0 faildata11 ro 0x0 this read-only bit field will contain the fail data for the second fail in block 1. free datasheet http:/// STMP36XX official product documentation 5/3/06 144 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 7.6.22. sram status register 4 description sram status register 4 is a read-only fail data register. hw_digctl_1tram_status4 0x8001c150 hw_digctl_1tram_status4_set 0x8001c154 hw_digctl_1tram_status4_clr 0x8001c158 hw_digctl_1tram_status4_tog 0x8001c15c description: this register will contain fail data for the first fail in block 2. example: fail_data = hw_digctl_1tram_status4_rd(); 7.6.23. sram status register 5 description sram status register 5 is a read-only fail data register. hw_digctl_1tram_status5 0x8001c160 hw_digctl_1tram_status5_set 0x8001c164 hw_digctl_1tram_status5_clr 0x8001c168 hw_digctl_1tram_status5_tog 0x8001c16c description: this register will contain fail data for the second fail in block 2. example: fail_data = hw_digctl_1tram_status5_rd(); table 151. hw_digctl_1tram_status4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 faildata20 table 152. hw_digctl_1tram_status4 bit field descriptions bits label rw reset definition 31:0 faildata20 ro 0x0 this read-only bit field will contain the fail data for the first fail in block 2. table 153. hw_digctl_1tram_status5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 faildata21 table 154. hw_digctl_1tram_status5 bit field descriptions bits label rw reset definition 31:0 faildata21 ro 0x0 this read-only bit field will contain the fail data for the second fail in block 2. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 145 7.6.24. sram status register 6 description sram status register 6 is a read-only fail data register. hw_digctl_1tram_status6 0x8001c170 hw_digctl_1tram_status6_set 0x8001c174 hw_digctl_1tram_status6_clr 0x8001c178 hw_digctl_1tram_status6_tog 0x8001c17c description: this register will contain fail data for the first fail in block 3. example: fail_data = hw_digctl_1tram_status6_rd(); 7.6.25. sram status register 7 description sram status register 7 is a read-only fail data register. hw_digctl_1tram_status7 0x8001c180 hw_digctl_1tram_status7_set 0x8001c184 hw_digctl_1tram_status7_clr 0x8001c188 hw_digctl_1tram_status7_tog 0x8001c18c description: this register will contain fail data for the second fail in block 3. example: fail_data = hw_digctl_1tram_status7_rd(); table 155. hw_digctl_1tram_status6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 faildata30 table 156. hw_digctl_1tram_status6 bit field descriptions bits label rw reset definition 31:0 faildata30 ro 0x0 this read-only bit field will contain the fail data for the first fail in block 3. table 157. hw_digctl_1tram_status7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 faildata31 table 158. hw_digctl_1tram_status7 bit field descriptions bits label rw reset definition 31:0 faildata31 ro 0x0 this read-only bit field will contain the fail data for the second fail in block 3. free datasheet http:/// STMP36XX official product documentation 5/3/06 146 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 7.6.26. sram status register 8 description sram status register 8 is a read-only fail address register. hw_digctl_1tram_status8 0x8001c190 hw_digctl_1tram_status8_set 0x8001c194 hw_digctl_1tram_status8_clr 0x8001c198 hw_digctl_1tram_status8_tog 0x8001c19c description: this register will contai n fail data for the first and second failure s in block 0. example: fail_data = hw_digctl_1tram_status8_rd(); 7.6.27. sram status register 9 description sram status register 9 is a read-only fail address register. hw_digctl_1tram_status9 0x8001c1a0 hw_digctl_1tram_status9_set 0x8001c1a4 hw_digctl_1tram_status9_clr 0x8001c1a8 hw_digctl_1tram_status9_tog 0x8001c1ac table 159. hw_digctl_1tram_status8 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 failaddr01 failaddr00 table 160. hw_digctl_1tram_status8 bit field descriptions bits label rw reset definition 31:16 failaddr01 ro 0x0 this read-only bit field will contain the failing address for the second fail in block 0. 15:0 failaddr00 ro 0x0 this read-only bit field will contain the failing address for the first fail in block 0. table 161. hw_digctl_1tram_status9 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 failaddr11 failaddr10 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 147 description: this register will contain fail data for the first second failures in block 1. example: fail_data = hw_digctl_1tram_status9_rd(); 7.6.28. sram status register 10 description sram status register 10 is a read-only fail address register. hw_digctl_1tram_status10 0x8001c1b0 hw_digctl_1tram_status10_set 0x8001c1b4 hw_digctl_1tram_status10_clr 0x8001c1b8 hw_digctl_1tram_status10_tog 0x8001c1bc description: this register will contai n fail data for the first and second failure s in block 2. example: fail_data = hw_digctl_1tram_status10_rd(); 7.6.29. sram status register 11 description sram status register 11 is a read-only fail address register. hw_digctl_1tram_status11 0x8001c1c0 hw_digctl_1tram_status11_set 0x8001c1c4 hw_digctl_1tram_status11_clr 0x8001c1c8 table 162. hw_digctl_1tram_status9 bit field descriptions bits label rw reset definition 31:16 failaddr11 ro 0x0 this read-only bit field will contain the failing address for the second fail in block 1. 15:0 failaddr10 ro 0x0 this read-only bit field will contain the failing address for the first fail in block 1. table 163. hw_dig ctl_1tram_status10 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 failaddr21 failaddr20 table 164. hw_digctl_1tram_status10 bit field descriptions bits label rw reset definition 31:16 failaddr21 ro 0x0 this read-only bit field will contain the failing address for the second fail in block 2. 15:0 failaddr20 ro 0x0 this read-only bit field will contain the failing address for the first fail in block 2. free datasheet http:/// STMP36XX official product documentation 5/3/06 148 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 hw_digctl_1tram_status11_tog 0x8001c1cc description: this register will contai n fail data for the first and second failure s in block 3. example: fail_data = hw_digctl_1tram_status11_rd(); 7.6.30. sram status register 12 description sram status register 12 is a read-only fail state register. hw_digctl_1tram_status12 0x8001c1d0 hw_digctl_1tram_status12_set 0x8001c1d4 hw_digctl_1tram_status12_clr 0x8001c1d8 hw_digctl_1tram_status12_tog 0x8001c1dc table 165. hw_digctl_1tram_status11 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 failaddr31 failaddr30 table 166. hw_digctl_1tram_s tatus11 bit field descriptions bits label rw reset definition 31:16 failaddr31 ro 0x0 this read-only bit field will contain the failing address for the second fail in block 3. 15:0 failaddr30 ro 0x0 this read-only bit field will contain the failing address for the first fail in block 3. table 167. hw_dig ctl_1tram_status12 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd3 failstate11 rsvd2 failstate10 rsvd1 failstate01 rsvd0 failstate00 table 168. hw_digctl_1tram_status12 bit field descriptions bits label rw reset definition 31:29 rsvd3 ro 0x0 this field is unused. 28:24 failstate11 ro 0x0 this read-only bit field will contain the failing state for the second fail in block 1. 23:21 rsvd2 ro 0x0 this field is unused. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 149 description: this register will contain fail data for t he first and second failu res in blocks 0 and 1. example: fail_data = hw_digctl_1tram_status12_rd(); 7.6.31. sram status register 13 description sram status register 13 is a read-only fail state register. hw_digctl_1tram_status13 0x8001c1e0 hw_digctl_1tram_status13_set 0x8001c1e4 hw_digctl_1tram_status13_clr 0x8001c1e8 hw_digctl_1tram_status13_tog 0x8001c1ec 20:16 failstate10 ro 0x0 this read-only bit field will contain the failing state for the first fail in block 1. 15:13 rsvd1 ro 0x0 this field is unused. 12:8 failstate01 ro 0x0 this read-only bit field will contain the failing state for the second fail in block 0. 7:5 rsvd0 ro 0x0 this field is unused. 4:0 failstate00 ro 0x0 this read-only bit field will contain the failing state for the first fail in block 0. table 169. hw_dig ctl_1tram_status13 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd3 failstate31 rsvd2 failstate30 rsvd1 failstate21 rsvd0 failstate20 table 170. hw_digctl_1tram_status13 bit field descriptions bits label rw reset definition 31:29 rsvd3 ro 0x0 this field is unused. 28:24 failstate31 ro 0x0 this read-only bit field will contain the failing state for the second fail in block 3. 23:21 rsvd2 ro 0x0 this field is unused. 20:16 failstate30 ro 0x0 this read-only bit field will contain the failing state for the first fail in block 3. 15:13 rsvd1 ro 0x0 this field is unused. 12:8 failstate21 ro 0x0 this read-only bit field will contain the failing state for the second fail in block 2. table 168. hw_digctl_1tram_status12 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 150 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 description: this register will contain fail data for t he first and second failu res in blocks 2 and 3. example: fail_data = hw_digctl_1tram_status0_rd(); 7.6.32. digital control scratch register 0 description scratch register 0. hw_digctl_scratch0 0x8001c290 description: scratch pad register 0. example: scratch_pad = (*void)hw_digctl_scratch0.ptr; 7.6.33. digital control scratch register 1 description scratch register 1. hw_digctl_scratch1 0x8001c2a0 description: 7:5 rsvd0 ro 0x0 this field is unused. 4:0 failstate20 ro 0x0 this read-only bit field will contain the failing state for the first fail in block 2. table 171. hw_digctl_scratch0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ptr table 172. hw_digctl_scratch0 bit field descriptions bits label rw reset definition 31:0 ptr rw 0x0 scratch pad register. table 173. hw_digctl_scratch1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ptr table 174. hw_digctl_scratch1 bit field descriptions bits label rw reset definition 31:0 ptr rw 0x0 scratch pad register. table 170. hw_digctl_1tram_status13 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 151 scratch pad register 1. example: scratch_pad = (*void)hw_digctl_scratch1.ptr; 7.6.34. digital control arm cache register description cache ram controls. hw_digctl_armcache 0x8001c2b0 description: arm cache control register. example: cache_timing = hw_digctl_armcache.cache_ss; 7.6.35. sigmatel copyright identifier register description read-only sigmatel copyri ght identifier register. hw_digctl_sgtl 0x8001c300 table 175. hw_digctl_armcache 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 cache_ss rsvd1 dtag_ss rsvd0 itag_ss table 176. hw_digctl_armc ache bit field descriptions bits label rw reset definition 31:10 rsvd2 ro 0x0 reserved. 9:8 cache_ss rw 0x1 timing control for 512x32x2 rams (cache). 7:6 rsvd1 ro 0x0 reserved. 5:4 dtag_ss rw 0x1 timing control for 128x22x4 ram (dtag). 3:2 rsvd0 ro 0x0 reserved. 1:0 itag_ss rw 0x1 timing control for 64x22x4 ram (itag). table 177. hw_digctl_sgtl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 copyright table 178. hw_digctl_sgtl bit field descriptions bits label rw reset definition 31:0 copyright ro 0x6d676953 this read-only bit field contains the four bytes of the sigmatel copyright identification string. free datasheet http:/// STMP36XX official product documentation 5/3/06 152 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 description: this register provides read-only access to the zero-terminated twelve-byte sigma- tel copyright identification string. this register behaves somewhat differently from all other apb registers in that it provides different read-back values at its four suc- cessive sct bus addresses. the followi ng binary values are read back at 0x8001c300, 0x8001c304, an d 0x8001c308 respectively: 0x6d676953 m,g,i,s at 0x8001c300 0x6c655461 l,e,t,a at 0x8001c304 0x00aea92d 0x00, regist ered trademark symbol;, ?, hyphen at 0x8001c308 0x00aea92d 0xba, 0xd0, i, s at 0x8001c30c the debugger does a string compare on these 12 successive little endian bytes. any chip that reads back these values is eit her a sigmatel chip or it is a competitors chip that is violating sigmatel registered trademarks and or copyrights. example: printf("%s", (char *)hw_digctl_sgtl_addr); 7.6.36. digital control chip revision register description read-only chip revision register. hw_digctl_chipid 0x8001c310 description: table 179. hw_digctl_chipid 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 product_code rsvd1 revision table 180. hw_digctl_chipid bit field descriptions bits label rw reset definition 31:16 product_code ro 0x3600 this read-only bit field always reads back the chip id. the lower eight bits of the ch ip id are constructed from laser fuse values. 15:8 rsvd1 ro 0x00 always write zero es to this bit field. 7:0 revision ro 0x00 this read-only bit field always reads back the mask revision level of the chip. ta1 = 0x0 ta2 = 0x1 ta3/ta3a/1.3 = 0x2 1.4 = 0x3 1.5 = 0x4 b1/2.0 = 0x5 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 7: dig ital control and on-chip ram 153 chip identification register. example: formatandprintchipid(hw_digctl_chipid_product_code,hw_digctl_chipid_revision ); digctl xml revision: 1.79 free datasheet http:/// STMP36XX official product documentation 5/3/06 154 chapter 7: digital control and on-chip ram 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 8: usb high-speed on-the-go (host/device) controller 155 8. usb high-speed on-the-go (host/device) controller this chapter describes the usb high-spe ed on-the-go controller included on the STMP36XX. it includes sections on the pi o, dma, and utmi interfaces, along with usb controller flowcharts. descriptions for programmable registers mentioned in this chapter can be found in section 4.9 on page 56 , section 7.6 on page 128 , section 9.6 on page 169 , and section 31.8 on page 759 . 8.1. overview the STMP36XX includes a universal serial bus (usb) version 2.0 controller capa- ble of operating as either a usb device or a usb host, as shown in figure 23 . in addition, it contains supp orting circuitry for usb on -the-go (otg). the usb con- troller is used to download digital music data or program code into external memory and to upload voice recordings from memory to the pc. program updates can also be loaded into the flash memory area using the usb interface. as a host controller, it can enumerate and control usb devices attached to it. using the otg features, it can negotiate with a nother otg system to be either the host or the device in a peer connection. the usb controller operates either in full-speed mode or high-speed mode. refer to the usb implementer?s forum website www.usb.org for detailed specifica- tions and information on the usb protocol, timing and electrical characteristics. the usb 2.0 controller comprises both a programmed i/o (pio) interface and a dma interface. both of these interfaces, as implemented in the arc (transdimen- sion) high-speed usb core, are designed to meet an arm ltd. amba hardware bus (ahb). the ahb is used by the u sb controller as a slave (pio register accesses) and as a master (dma memory accesses). the usb 2.0 phy is fully integrated on-chip and is described in chapter 9 , begin- ning on page 161 . the phy is controlled over the apbx peripheral bus. 8.2. usb controller core the usb controller is an inst antiation of the arc usb controller core. this propri- etary core, the intellectual property it represents, an d the copyrighted documenta- tion for the core are the property of arc international. for detailed information about the controller core, refer to the td243 usb host/perip heral/otg controller datasheet ( http://www.transdimension.com/downloads/index.html ). free datasheet http:/// STMP36XX official product documentation 5/3/06 156 chapter 8: usb high-speed on-the-go (host/device) controller 5-36xx-d1-1.02-050306 apbx usb dma interface usb xcvr phy regs. arc usb 2.0 device/host/otg controller integrated usb 2.0 phy usb pio interface 480-mhz pll ? asynchronous clock domain crossing ? transceiver interface logic port controller protocol engine ? interval timers ? error handling ? crc handling on-chip dual port synchronous sram dual port ram controller ? virtual fifo channels ? dma contexts dma engine ? bus interface ? endpoint priming state machine ? data movement programmed i/o target inteface ? bus interface ? control and status ? interrupts sigmatel usb interface block usb utmi interface arm core ahb master ahb on chip ram ahb slave apbx master ahb-to-apbx bridge ahb slave figure 23. usb 2.0 device controller block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 8: usb high-speed on-the-go (host/device) controller 157 8.3. usb programmed i/o (pio) target interface the pio interface is on an ahb slave of the tdi controller. it allows the arm pro- cessor to access the configuration, control, and status registers. there are identifi- cation registers for hardware configuration parameters and operational registers for control and status. 8.4. usb dma interface the dma is a master ahb interface that a llows usb data to be transferred to/from the system memory. the data in memory is structured to implement a software framework supported by the co ntroller. for a device controller, this structure is a link-list interface that consis ts of queue heads and pointers that are transfer descrip- tors. the queue head is where transfers are managed. it has status information and location of the data buffers. the hardware controller?s pio registers enable the entire data structure, and once usb data is transferred in between the host, the sta- tus of the transfer is updated in the queue head, with minimal latency to the system. for a host controller, there is also a link-list interface. it consists of a periodic frame list and pointers to transfer descriptors. th e period frame list is a schedule of trans- fers. the frame list points to the data buf fers through the transfer descriptors. the hardware controller?s pio registers enable the data structure and manage the trans- fers within a usb frame. the period frame list works as a sliding window of host transfers over time. as each transfer is completed, the status information is updated in the frame list. for high-speed usb transmissions, use on- chip ram (oc-ram) as the data source instead of sdram. sdram does not have the bandwidth needed to supply the usb dma engine at the required rate of 60 mbytes per second (480 mbits/s usb high-speed bit rate). for full-speed trans missions, the STMP36XX has the bandwidth to handle the data buffers in sdram. however, the queue heads (dqh, as described in the arc manual) must be placed in oc-ram. a design limitation on burst size does not allow the queue heads to be placed in sdram. 8.5. usb utmi interface the sigmatel-developed test mode logic allows the integrated usb phy to be exported for standalone use. in addition, the test modes include both digital and analog loopback tests. 8.5.1. exporting the phy the STMP36XX usb phy interface can be configured to be a standalone usb phy. in this mode, the utmi interface is exposed on the pins. this mode only supports two 16-bit unidirectional data buses. 8.5.2. digital/analog loopback test mode since the utmi has to operate at high fr equencies (480 mhz), it has a capacity to self-test. a pseudo-random number generator transmits data to the receive path, and data is compared for validity. in the digital loopback, the data transfer only resides in the utmi. it checks for sync, eop, and bit-stuffing generation and data integrity. the analog loopback is the same as the digital loopback, but involves the analog phy. this allows for checking of the high-speed (hs) and full-speed (fs) comparators and transmitters. free datasheet http:/// STMP36XX official product documentation 5/3/06 158 chapter 8: usb high-speed on-the-go (host/device) controller 5-36xx-d1-1.02-050306 8.6. usb controller flowcharts start hw_usbphy_ctrl_ sftrst hw_power_sts_ vdd5v_gt_vddio no check for 5-v input set hw_usbphy_debug_enhstpulldown yes play_startup clear hw_usbphy_debug_hstpulldown set hw_usbphy_ctrl_endevplugindetect wait for 1 microsecond hw_usbphy_ status_devplugin _status done no figure 24. usb 2.0 check_usb_plugged_in flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 8: usb high-speed on-the-go (host/device) controller 159 hw_clkctrl_ pllctrl1_ lock==1 device and host operation not otg phy startup clear hw_usbphy_ctrl_sftrst clear hw_usbphy_ctrl_clkgate clear hw_usbphy_pwd clear hw_power_ctrl_clkgate set hw_power_debug_vbusvalidpiolock set hw_power_debug_avalidpiolock set hw_power_debug_bvalidpiolock set hw_power_sts_bvalid set hw_power_sts_avalid set hw_power_sts_vbusvalid set hw_clkctrl_cpuclkctrl_wait_pll_lock set hw_clkctrl_cpuclkctrl_div=400 set hw_clkctrl_gpmiclkctrl_wait_pll_lock set hw_clkctrl_gpmiclkctrl_div=400 set cpu clock to 1.2 mhz set gpmi clock to 1.2 mhz make sure xbus is lower than hbus hw_clkctrl_xbusclkctrl_power hw_clkctrl_pllctrl0_div=20 power on pll hw_clkctrl_pllctrl0_freq=480 program to 480 mhz clear hw_clkctrl_pllctrl0_bypass hw_clkctrl_xbusclkctrl_div=1 set hw_clkctrl_pllctrl0_en_usb_clks clear hw_clkctrl_utmiclkctrl_utmi_clk30m_gate switch to pll from crystal clear hw_clkctrl_utmiclkctrl_utmi_clk120m_gate no yes figure 25. usb 2.0 usb phy startup flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 160 chapter 8: usb high-speed on-the-go (host/device) controller 5-36xx-d1-1.02-050306 yes arc suspend interrupt? no arc irq to other arc isr set hw_usbphy_ctrl_enirqresumedetect set all power-down bits in hw_usbphy_pwd play shut down set hw_digctrl_ctrl_usb_clkgate set hw_clkctrl_pllctrl0_bypass set hw_clkctrl_pllctrl0_power pll bypass, switches to xtal figure 26. usb 2.0 phy pll suspend flowchart clear hw_clkctrl_utmiclkctrl_utmi_clk120m_gate clear hw_clkctrl_utmiclkctrl_utmi_clk30m_gate clear hw_digctl_ctrl_usb_clkgate clear hw_usbphy_ctrl_sftrst clear hw_usbphy_ctrl_clkgate hw_usbctrl_usbcmd=0x00080000; set hw_clkctrl_utmiclkctrl_utmi_clk120m_gate set hw_clkctrl_utmiclkctrl_utmi_clk30m_gate set hw_digctl_ctrl_usb_clkgate set all power-down bits in hw_usbphy_pwd prepare usb controller to deassert utmi_reset figure 27. utmi powerdown free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 161 9. integrated usb 2.0 phy this chapter describes the integrated usb 2.0 full-speed and high-speed phy available on the STMP36XX. it includes sect ions on external signals, the utmi and digital circuits, and the analog transceiver. programmable registers are described in section 9.6 . 9.1. overview the STMP36XX contains an integrated usb 2.0 phy macrocell capable of connect- ing to pc host systems at the usb full-speed (fs) rate of 12 mbits/s or at the usb 2.0 high-speed (hs) rate of 480 mbits/s. see figure 28 for a block diagram of the phy. the integrated phy provides a stand ard utmi interface. this allows the STMP36XX to alternatively connect to an external utmi-compliant usb 2.0 control- ler chip. the following subsections describe the exter nal interfaces, internal interfaces, major blocks, and programable registers that comprise the integrated usb 2.0 phy. 9.2. external signals ? dp, dn : these pins connect directly to a usb device connector. ? precision calibration resistor : this pin connects a 620 ? 1% resistor to ground. the key on-chip resistor?the 45 ? high-speed termination resistor? contains digitally controlled trimming and calibration circuits to match its impedance to the external precision resistor for usb 2.0 specification on-chip ram arm bus interface utmi digital analog rx/tx ahb master bus ahb slave bus external usb 2.0 utmi controller usb 2.0 controller dp dn digital rx digital tx integrated usb 2.0 phy (utmi macrocell) system pll crystal oscillator dclk apbx bridge figure 28. usb 2.0 phy block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 162 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 compliance in device operation. a 15k ? pulldown on the dp and dn pins allows for compliance in host operation. 9.3. utmi and digital circuits the utmi provides a 16-bit interface to the usb controller. this interface is clocked at 30 mhz. there are four parts to the ut mi/digital circuits block: the utmi block, the digital transmitter, the digital rece iver, and the programmable registers block. 9.3.1. utmi block this block handles the line_state bits, rese t buffering, suspend distribution, trans- ceiver speed selection, and transceiver termination selection. the pll supplies a 120-mhz signal to all of the digital logic. the utmi block does a final divide by four to develop the 30-mhz clo ck used in the interface. 9.3.2. digital transmitter block the digital transmitter block receives the 16-bit transmit data from the usb control- ler, and handles the tx_valid, tx_validh a nd tx_ready handshake. in addition, it con- tains the transmit serializer that converts the 16-bit parallel words at 30 mhz to a single bitstream at 480 mbit for high-speed or 12 mbit for fu ll-speed. it does this while implementing the bit-stuffing algorith m and the nrzi encoder that are used to remove the dc component from the serial bitstream. the output of this encoder is sent to the full-speed (fs) or high-speed (hs) drivers in the analog transceiver sec- tion?s transmitter block. 9.3.3. digital receiver block the digital receiver block receives the raw serial bitstream either from the hs differ- ential transceiver or from the fs differenti al transceiver. the hs input goes to a very fast dll that uses one of eight identica lly spaced phases of the 480-mhz clock to pick a sample point. as the phase of the usb host transmitter shifts relative to the local pll, the receiver section?s hs dll tracks these changes to give a reliable sample of the incoming 480-mbit/s bitstream . since this sample point shifts relative to the pll phase used by the digital logic, a rate-matching elastic buffer is provided to cross this clock domain bo undary. once the bitstream is in the local clock domain, an nrzi decoder and bit unstuffer restore the original payload data bitstream and pass it to a deserializer and holding register. the receive state machine handles the rx_valid, rx_validh, and handshake with the usb controller. the handshake is not interlocked, in that there is no rx_ready signal coming from the controller. the con- troller must take each 16-bit value as presented by the phy. the receive state machine provides an rx_active signal to the controller that indicate s when it is inside a valid packet (sync detected, etc.). 9.3.4. programmable registers block the phy contains four 24 bit programmabl e registers, which are fully described in section 9.6 . free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 163 9.4. analog transceiver the analog transceiver section comprises an analog receiver and an analog trans- mitter, as shown in figure 29 . 9.4.1. analog receiver the analog receiver comprises five differential receivers and two single-ended receivers, described below. 9.4.1.1. hs differential receiver the high-speed differential receiver is both a differential analog receiver and thresh- old comparator. its output is a one if the differential signal is greater than a 0-v threshold. its output is zero otherwise. it s purpose is to discriminate the 400-mv differential voltage resulting from the hi gh-speed drivers current flow into the dual dn dp usb cable hs differential rcvr squelch fs differential rcvr hs_disconnect_detect single-ended detector se_dp single-ended detector se_dm fs datadrive assert se0 hs current source enable hs data drive hs drive enable fs edge mode select fs driver output enable vddio (3.3v) 1500 ? rpu enable transmitter receiver test, calibration, and discrete power-down controls usb_plugged_in_detect 15000 ? 15000 ? figure 29. usb 2.0 phy anal og transceiver block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 164 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 45 ? terminations found on each leg of the differential pair. the envelope or squelch detector, described below, ensures that the differential signal has sufficient magni- tude to be valid. the hs differential rece iver tolerates up to 500 mv of common mode offset. 9.4.1.2. squelch detector the squelch detector is a differential analog receiver and threshold comparator. its output is a one if the differential magnitud e is less than a nominal 100-mv threshold. its output is zero otherwise. its purpose is to invalidate the hs differential receiver when the incoming signal is simp ly too low to receive reliably. 9.4.1.3. fs differential receiver the full-speed differential receiver is both a differential analog receiver and thresh- old comparator. the crossover voltage falls between 1.3 v and 2.0 v. its output is a one when the d p line is above the crossover point and the d n line is below the crossover point. 9.4.1.4. hs disconnect detector this host-side function is not used in STMP36XX applications, but is included to make a complete utmi macrocell. it is a differential analog receiver and threshold comparator. its output is a one if the diff erential magnitude is greater than a nominal 575-mv threshold. its output is zero, otherwise. 9.4.1.5. usb plugged-in detector the usb plugged-in detector looks for both d p and d n to be high. there is a pair of large on-chip pullup resistors (200k ? ) that hold both d p and d n high when the usb cable is not attached. the usb plugged-in detector signals a zero in this case. when in device mode, the host/hub interface that is upstream from the STMP36XX contains a 15k ? pulldown resistor that easily overrides the 200k ? pullup. when plugged in, at least one signal in the pair will be low, which will force the plugged-in detector?s output high. 9.4.1.6. single ended d p receiver the single ended d p receiver output is high whenever the d p input is above its nominal 1.8-v threshold. 9.4.1.7. single ended d n receiver the single ended d n receiver output is high whenever the d n input is above its nominal 1.8-v threshold. 9.4.2. analog transmitter the analog transmitter comprises two differ ential drivers: one for high-speed signal- ing and one for full-speed signaling. it also contains the switchable1.5k ? pullup resistor. 9.4.2.1. switchable high-speed 45 ? termination resistors high-speed current mode differential signaling requires good 90 ? differential termi- nation at each end of the usb cable. this results from switching in 45 ? terminating resistors from each signal line to ground at each end of the cable. because each signal is parallel terminated with 45 ? at each end, each driver sees a 22.5 ? load. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 165 this is much too low of a load impedance for full-speed signaling levels?hence the need for switchable high-speed terminating resistors. switchable trimming resistors are provided to tune the actual terminat ion resistance of each device, as shown in figure 30 . the hw_usbphytx_txcal45dp bit fiel d, for example, allows one of 16 trimming resistor values to be placed in parallel with the 45 ? terminator on the d p signal. the calibration operation is described in section 9.4.2.6 . 9.4.2.2. full-speed differential driver the full-speed differential drivers are e ssentially ?open drain? low-impedance pull- down devices that are switched in a differ ential mode for full-sp eed signaling, i.e., either one or the other device is turned on to signal the ?j? state or the ?k? state. these drivers are both turned on, simultaneo usly, for high-speed signaling. this has the effect of switching in both 45 ? terminating resistors. the tx_fs_hiz signal origi- nates in the digital transmitter section. the hs_term signal that also controls these drivers comes from the utmi. 9.4.2.3. high-speed differential driver the high-speed differential driver receiv es a 17.78-ma current from the constant current source and essentially steers it down either the d p signal or the d n signal or alternatively to ground. this current w ill produce approximately a 400-mv drop across the 22.5 ? termination seen by the driver wh en it is steered onto one of the signal lines. the approximately 17.78-ma current source is referenced back to the integrated voltage-band-gap circuit. the iref , ibias, and v to i circuits are shared with the integrated battery charger. 9.4.2.4. switchable 1.5k ? dp pullup resistor the STMP36XX contains a switchable 1.5k ? pullup resistor on the d p signal. this resistor is switched on to tell the host/h ub controller that a full-speed-capable device is on the usb cable, powered on, and read y. this resistor is switched off at power-on reset so the host does not recognize a usb device until processor soft- ware enables the announcement of a full-speed device. 9.4.2.5. switchable 15k ? dp pulldown resistor the STMP36XX contains a switchable 15k ? pulldown resistor on both d p and d n signals. this is used in host mode to tell the device controller that a host is present. free datasheet http:/// STMP36XX official product documentation 5/3/06 166 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 table 181 summarizes the response of the phy analog transmitter to various states of utmi input and key transmit/receive state machine states. current switch 45 ? fs drvr current switch 45 ? fs drvr current steering 17.78ma dn dp usb cable v to i 620 ? 1% data_p,hs_xcvr data_n,hs_xcvr vbg to battery charger calibration comparator hw_usbphy_tx_ txcal45dn hw_usbphy_tx_ txcal45dp hw_usbphy_pwd: txpwdvbg, txpwdv2i, txpwdibias hw_usbphy_tx_ txcmpout hw_usbphy_tx: txencal45dp, txencal45dn, txcalibrate data_p,data_n, fs_hiz, hs_term ibias hw_usbphy_tx: txencal45dp,dn ref_res figure 30. usb 2.0 phy transmitter block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 167 9.4.2.6. resistor calibration mode the analog transmitter section includes a calibration comparator that can monitor the d p or d n voltage, as desired. setting hw_usbphy_tx_txencal45dp selects the d p signal. the comparator output is visible in hw_usbphy_tx_txcmpout_status. to calibrate the 45 ? d p terminator, first set the field hw_usbphy_tx_txcal45dp to all ones. the flowchart in figure 31 shows how to search for the proper trimming resistor to calibrate the d p terminator. in general, follow thes e steps to perform a similar oper- ation. ? put the chip into termination resistor calibration mode for the d p terminator. ? start with the largest value of trimming select, i.e., all ones. ? make several precise minimum delay calculations to allow the mixed signal components to stabilize. ? the comparator output is sampled and then checked. if the comparator has not tripped, reduce the value of the trimming select field and try again. repeat these steps until the trip point is reached. table 181. usb phy terminator states utmi opmode utmi term utmi xcvr t/r function 45 ? hiz 1500 ? hiz 00=normal 0 0 x hs 0 1 1 1 t fs 0 0 1 1 r fs 1 0 suspend 1 0 r chirp 1 0 1 0 t chirp 1 0 0 1 x disconnect 1 1 01=nodrive 0 0 t hs 1 1 0 0 r hs 1 1 1 1 x fs 1 1 1 0 x chirp 1 1 0 1 x disconnect 1 1 por 10=nonrzi nobitstuff 0 0 x hs 0 1 1 1 t fs 0 0 1 1 r fs 1 0 1 0 r chirp 1 0 1 0 t chirp 1 0 0 1 x disconnect 1 1 11= invalid 0 0 t hs 1 1 0 0 r hs 1 1 1 1 x fs 1 1 1 0 x chirp 1 1 0 1 x disconnect 1 1 free datasheet http:/// STMP36XX official product documentation 5/3/06 168 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 while the flowchart in figure 31 shows how to calibrate the d p terminator, calibra- tion of the d n terminator is accomplished in a similar manner, substituting *dn bit fields for *dp bit fields. note: the txcal45dp and txcal45dn bit fields are represented in the register description for hw_usbphy_tx as 5-bit fiel ds. however, the flowchart indicates and uses only four bits, which is correct for the STMP36XX. for resistor calibration on the STMP36XX, the most significant bit (5th bit) should always be 0, else an alias- ing effect will occur. set hw_usbphy_tx_txcalibrate=1 hw_usbphy_tx_ cmpout_status == 1? set hw_usbphy_tx_txcalibrate=0 set hw_usbphy_tx_txcal45dp=1111 set hw_usbphy_tx_txencal45dp=1 set hw_usbphy_tx_txencal45dp=0 yes stop start decrement hw_usbphy_tx_txcal45dp hw_usbphy_tx_ txcal45dp == 0000? no yes no power up for calibration. set hw_usbphy_pwd_txpwdvbg=0 set hw_usbphy_pwd_txpwdv2i=0 set hw_usbphy_pwd_txpwdibias=0 set hw_usbphy_pwd_txpwdfs=0 set hw_usbphy_pwd_txpwdcomp=0 hw_usbphy_tx_pwd = txpwdcomp | txpwdfs for normal operation. allow 1.5 s (45 30-mhz cycles) for analog circuitry to stabilize. allow 1 s (30 30-mhz cycles) for analog circuitry to stabilize. set hw_usbphy_ctrl_sftrst=0 set hw_usbphy_ctrl_clkgate=0 figure 31. 45 ? calibration flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 169 9.5. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 9.6. programmable registers the usb 2.0 integrated phy contains the fo llowing directly programmable registers. 9.6.1. usb phy power-down register description the usb phy power-down re gister provides overall control of the phy power state. hw_usbphy_pwd 0x8007c000 hw_usbphy_pwd_set 0x8007c004 hw_usbphy_pwd_clr 0x8007c008 hw_usbphy_pwd_tog 0x8007c00c table 182. hw_usbphy_pwd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd3 rxpwdrx rxpwddiff rxpwd1pt1 rxpwdenv rsrvd2 txpwdcomp txpwdvbg txpwdv2i txpwdibias txpwdfs rsrvd1 rsrvd0 table 183. hw_usbphy_pwd bit field descriptions bits label rw reset definition 31:21 rsrvd3 ro 0x0 reserved 20 rxpwdrx rw 0x1 set to one to power down the entire usb phy receiver block, except for the full-speed differential receiver. set to zero for normal operation. 19 rxpwddiff rw 0x1 set to one to power down the usb high-speed differential receiver. set to zero for normal operation. 18 rxpwd1pt1 rw 0x1 set to one to power down the usb full-speed differential receiver. set to zero for normal operation. 17 rxpwdenv rw 0x1 set to one to power down the usb high-speed receiver envelope detector (squelch signal). set to zero for normal operation. 16:15 rsrvd2 ro 0x0 reserved 14 txpwdcomp rw 0x1 set to one to power down the usb phy transmit calibration comparator. set to zero during calibration, and set to one after calibration is complete. free datasheet http:/// STMP36XX official product documentation 5/3/06 170 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 9.6.2. usb phy transmitter control register description the usb phy transmitter control register handles the transmit calibration controls and other transmit controls. hw_usbphy_tx 0x8007c010 hw_usbphy_tx_set 0x8007c014 hw_usbphy_tx_clr 0x8007c018 hw_usbphy_tx_tog 0x8007c01c 13 txpwdvbg rw 0x1 set to one to power down the usb phy transmit voltage bandgap buffer amplifier, as well as the v-to-i converter and the current mirror. note that these circuits are shared with t he battery charge circuit. setting this to one will not power down these circuits, unless the corresponding bit in the battery charger is also set for power down. set to zero for normal operation and for calibration. 12 txpwdv2i rw 0x1 set to one to power down the usb phy transmit v-to- i converter and the current mirror. note these circuits are shared with the battery charge circuit. setting this to one will not power down these circuits, unless the corresponding bit in the battery charger is also set for pow er down. set to zero for normal operation and for calibration. 11 txpwdibias rw 0x1 set to one to power down the usb phy current bias block for the transmitter. this bit should only be set when the usb is in suspend mode. this effectively powers down the entire usb transmit path. note these circuits are shared with t he battery charge circuit. setting this to one will not power down these circuits, unless the corresponding bit in the battery charger is also set for power down. set to zero for normal operation and for calibration. 10 txpwdfs rw 0x1 set to one to power down the usb full-speed drivers. this turns off the current starvation sources and puts the drivers into high-z output. set to zero during calibration and set to one after calibration is complete. 9:5 rsrvd1 ro 0x0 reserved 4:0 rsrvd0 ro 0x0 reserved table 183. hw_usbphy_pwd bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 171 table 184. hw_usbphy_tx 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd6 txcmpout_status rsrvd5 txencal45dp txcal45dp rsrvd3 txencal45dn txcal45dn txcalibrate rsrvd1 table 185. hw_usbphy_tx bit field descriptions bits label rw reset definition 31:24 rsrvd6 ro 0x0 reserved 23 txcmpout_status rw 0x0 the calibration comparator output is latched to this bit. this bit should be erased for every new calibration. this bit can be set to zero or set to one by normal write from the cpu. in addition, it is loaded with the state of the calibration comparator's output whenever hw_usbphy_txcalibrate is set to one. it continously copies the comparator to this bit as long txcalibrate is set to one, i.e., when txcalibrate is one, writing to this bit has no effect. 22 rsrvd5 ro 0x0 reserved 21 txencal45dp rw 0x0 set to one for time during compare of the 45-ohm dp termination resistor to the reference resistor. this bit should be set to one each time a new value of hw_usbphy_tx_txcal45dp is set in order to compare the resulting resistance. note: only one of the following bits can be set to one for any calibration operation: hw_usbphy_tx_txencal45dn or hw_usbphy_tx_txencal45dp. set to zero when the dp calibration is completed. the result of the comparison can be seen in hw_usbphy_tx_txcmpout. 20:16 txcal45dp rw 0x6 decode to select a 45-ohm resistance to the dp output pin. maximum resistance = 0000. resistance is centered by design at 0110. perform calibration routine by initially setting to 1111 and counting down until comparator trips. note that while this field is 5 bits, the msb is not used on the stmp360xx and should be 0. 15:14 rsrvd3 ro 0x0 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 172 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 9.6.3. usb phy receiver control register description the usb phy receiver control register handles receive path controls. hw_usbphy_rx 0x8007c020 hw_usbphy_rx_set 0x8007c024 hw_usbphy_rx_clr 0x8007c028 hw_usbphy_rx_tog 0x8007c02c 13 txencal45dn rw 0x0 set to one for time during compare of the 45-ohm dn termination resistor to the reference resistor. this bit should be set to one each time a new value of hw_usbphy_tx_txcal45dp is set in order to compare the resulting resistance. note: only one of the following bits can be set to one for any calibration operation: hw_usbphy_tx_txencal45dn or hw_usbphy_tx_txencal45dp. set to zero when the dp calibration is completed. the result of the comparison can be seen in hw_usbphy_tx_txcmpout. 12:8 txcal45dn rw 0x6 decode to select a 45 ohm resistance to the dn output pin. maximum resistance = 0000. resistance is centered by design at 0110. perform calibration routine by initially setting to 1111 and counting down until comparator trips. note that while this field is 5 bits, the msb is not used on the stmp360xx and should be 0. 7 txcalibrate rw 0x0 set to one to effect calibration of any of the three precision resistances and set back to zero to read the results of calibration in hw_usbphy_tx_txcmpout. when set to one, it causes the calibration comparator output to continously update the state of hw_usbphy_tx_txcmpout. set to zero for normal operation. note: only one of the following bits can be set to one for any calibration operation: hw_usbphy_tx_txencal45dn or hw_usbphy_tx_txencal45dp. 6:0 rsrvd1 ro 0x0 reserved table 185. hw_usbphy_tx bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 173 description: empty description. example: empty example. 9.6.4. usb phy general control register description the usb phy general control register handles otg and host controls. this regis- ter also includes interrupt enables and connectivity detect enables and results. hw_usbphy_ctrl 0x8007c030 table 186. hw_usbphy_rx 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd5 rxdbypass rsrvd3 rsrvd4 rsrvd1 disconadj rsrvd0 envadj table 187. hw_usbphy_rx bit field descriptions bits label rw reset definition 31:23 rsrvd5 ro 0x0 reserved 22 rxdbypass rw 0x0 set to one to use the output of the dp single-ended receiver in place of the full-speed differential receiver. this test mode is intended for lab use only. set to zero for normal operation. 21:16 rsrvd3 ro 0x0 reserved 15:8 rsrvd4 ro 0x0 reserved 7:6 rsrvd1 ro 0x0 reserved 5:4 disconadj rw 0x0 the disconadj field adjusts the trip point for the disconnect detector. trip level voltage 0.57500 v = 0000. trip level voltage 0.56875 v = 0001. trip level voltage 0.58125 v = 0010. trip level voltage 0.58750 v = 0011. reserved = 01xx. reserved = 1xxx. 3:2 rsrvd0 ro 0x0 reserved 1:0 envadj rw 0x0 the envadj field adjusts the trip point for the envelope detector. trip level voltage 0.10000 v = 0000. trip level voltage 0.10625 v = 0001. trip level voltage 0.11225 v = 0010. trip level voltage 0.12500 v = 0011. reserved = 01xx. reserved = 1xxx. free datasheet http:/// STMP36XX official product documentation 5/3/06 174 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 hw_usbphy_ctrl_set 0x8007c034 hw_usbphy_ctrl_clr 0x8007c038 hw_usbphy_ctrl_tog 0x8007c03c table 188. hw_usbphy_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate utmi_suspendm rsrvd5 resume_irq enirqresumedetect rsrvd3 enotgiddetect rsrvd2 endevplugindetect hostdiscondetect_irq enirqhostdiscon enhostdiscondetect enhsprechargexmit table 189. hw_usbphy_ctrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 writing a one to this bit will soft-reset the hw_usbphy_pwd, hw_usbphy_tx, hw_usbphy_rx, and hw_usbphy_ctrl registers. 30 clkgate rw 0x1 gate utmi clocks. set to 1 to gate clocks. set to 0 for running clocks. set this to save power while the usb is not actively being used. co nfiguration state is kept while the clock is gated. 29 utmi_suspendm ro 0x0 used by the phy to indi cate a powered-down state. if all the power-down bits in the hw_usbphy_pwd are enabled, utmi_suspendm will be 0, otherwise 1. utmi_suspendm is negative logic, as required by the utmi specification. 28:11 rsrvd5 ro 0x0 reserved 10 resume_irq rw 0x0 indicates that the host is sending a wake-up after suspend. it is reset by software by writing a zero to the bit position or by writing a one to the sct clear address space. 9 enirqresumedetect rw 0x0 enables interrupt for detection of a non-j state on the usb line. this should only be enabled after the device has entered suspend mode. 8 rsrvd3 ro 0x0 reserved 7 enotgiddetect rw 0x0 enables circuit to detect resistance of miniab id pin. 6:5 rsrvd2 ro 0x0 reserved 4 endevplugindetect rw 0x0 for device mode, enables 200-kohm pullups for detecting connectivity to host. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 175 description: empty description. example: empty example. 9.6.5. usb phy status register description the usb phy status register holds results of irq and other detects. hw_usbphy_status 0x8007c040 3 hostdiscondetect_irq rw 0x0 indicates that the device has disconnected in high- speed mode. it is reset by software by writing a zero to the bit position or by writing a one to the sct clear address space. 2 enirqhostdiscon rw 0x0 enables interrupt for detection of disconnection to device when in high-speed host mode. this should be enabled after endevplugindetect is enabled. 1 enhostdiscondetect rw 0x0 for host mode, enables high-speed disconnect detector. this signal allows the override of enabling the detection, which is no rmally done in the utmi controller. the utmi controller will enable this circuit whenever the host sends a start-of-frame packet. 0 enhsprechargexmit rw 0x1 set to one to enable the high-speed transmit precharge circuit . table 190. hw_usbphy_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd6 resume_status rsrvd5 otgid_status rsrvd4 devplugin_status rsrvd3 hostdiscondetect_status rsrvd2 table 189. hw_usbphy_ctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 176 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 9.6.6. usb phy debug register description this register is used to debug the usb phy. hw_usbphy_debug 0x8007c050 hw_usbphy_debug_set 0x8007c054 hw_usbphy_debug_clr 0x8007c058 hw_usbphy_debug_tog 0x8007c05c table 191. hw_usbphy_status bit field descriptions bits label rw reset definition 31:11 rsrvd6 ro 0x0 reserved 10 resume_status ro 0x0 indicates that the host is sending a wake-up after suspend and has triggered an interrupt. 9 rsrvd5 ro 0x0 reserved 8 otgid_status rw 0x0 indicates the results of id pin on miniab plug. false (0) is when id resistance is less than ra_plug_id, thus indicating host (a) side. true (1) is when id resistance is greater than rb_plug_id, thus indicating device (b) side. 7 rsrvd4 ro 0x0 reserved 6 devplugin_status ro 0x0 indicates that the device has been connected on the d plus and d minus lines. 5:4 rsrvd3 ro 0x0 reserved 3 hostdiscondetect_stat us ro 0x0 indicates that the device has disconnected while in high-speed host mode. 2:0 rsrvd2 ro 0x0 reserved table 192. hw_usbphy_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd5 clkgate rsrvd4 squelchresetlength ensquelchreset rsrvd3 squelchresetcount rsrvd2 entx2rxcount tx2rxcount rsrvd1 enhstpulldown hstpulldown debug_interface_hold otgidpiolock free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 177 description: empty description. example: empty example. 9.6.7. utmi debug status register 0 description the utmi debug status register 0 holds re sults of running counters of error cases. hw_usbphy_debug0_status 0x8007c060 table 193. hw_usbphy_debug bit field descriptions bits label rw reset definition 31 rsrvd5 ro 0x0 reserved 30 clkgate rw 0x1 gate test clocks. set to 1 to gate clocks. set to 0 for running clocks. set this to save power while the usb is not actively being used. co nfiguration state is kept while the clock is gated. 29 rsrvd4 ro 0x0 reserved 28:25 squelchresetlength rw 0xf duration of reset in terms of the number of 480- mhz cycles. 24 ensquelchreset rw 0x1 set bit to allow squelch to reset high-speed receive. 23:21 rsrvd3 ro 0x0 reserved 20:16 squelchresetcount rw 0x18 delay in between the detection of squelch to the reset of high-speed receive. 15:13 rsrvd2 ro 0x0 reserved 12 entx2rxcount rw 0x0 set bit to allow a count down to transistion in between tx and rx. 11:8 tx2rxcount rw 0x0 delay in between end of transmit to the begin of receive. this is a johnson count value; thus, it will count to 8. 7:6 rsrvd1 ro 0x0 reserved 5:4 enhstpulldown rw 0x0 set bit 5 to 1 to override the arc control of the d plus 15kohm pulldown. set bit 4 to 1 to override the arc control of the d minus 15kohm pulldown. set to 0 to disable. 3:2 hstpulldown rw 0x0 set bit 3 to 1 to pull down 15kohm on d plus line. set bit 2 to 1 to pull down 15kohm on d minus line. set to 0 to disable. 1 debug_interface_hold rw 0x0 use holding registers to assist in timing for external utmi interface . 0 otgidpiolock rw 0x0 once otg id from hw_usbphy_status.otgid_status, use this to hold the value. this is to save power for the comparators that are used to determine the id status. free datasheet http:/// STMP36XX official product documentation 5/3/06 178 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 9.6.8. utmi debug status register 1 description the utmi debug status register 1 holds the observation of utmi_tx_data and utmi_rx_data. hw_usbphy_debug1_status 0x8007c070 table 194. hw_usbphy_debug0_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 squelch_count utmi_rxerror_fail_count loop_back_fail_count table 195. hw_usbphy_debug0 _status bit field descriptions bits label rw reset definition 31:26 squelch_count ro 0x0 running count of the squelch reset instead of normal end for high-speed receive. 25:16 utmi_rxerror_fail_cou nt ro 0x0 running count of the utmi_rxerror. 15:0 loop_back_fail_count ro 0x900d running count of the failed pseudo-random generator loopback. table 196. hw_usbphy_debug1_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 utmi_tx_data utmi_rx_data free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 179 description: empty description. example: empty example. 9.6.9. utmi debug status register 2 description the utmi debug status register 2 holds the observation of the utmi pins. hw_usbphy_debug2_status 0x8007c080 table 197. hw_usbphy_debug1 _status bit field descriptions bits label rw reset definition 31:16 utmi_tx_data ro 0x0 snapshot of the utmi transmit data bus. 15:0 utmi_rx_data ro 0x0 snapshot of the utmi receive data bus. table 198. hw_usbphy_debug2_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 utmi_txvalidh utmi_txvalid utmi_termselect utmi_xcvrselect utmi_opmode rsrvd0 utmi_linestate utmi_suspendm utmi_rxvalidh utmi_rxvalid utmi_rxactive utmi_rxerror utmi_txready table 199. hw_usbphy_debug2 _status bit field descriptions bits label rw reset definition 31:23 rsrvd1 ro 0x0 reserved 22 utmi_txvalidh ro 0x0 snapshot of the utmi txvalidh signal. 21 utmi_txvalid ro 0x0 snapshot of the utmi txvalid signal. 20 utmi_termselect ro 0x0 snapshot of the utmi term select signal. 19:18 utmi_xcvrselect ro 0x0 snapshot of the utmi xcvr select signal. 17:16 utmi_opmode ro 0x0 snapshot of the utmi opmode bus. 15:8 rsrvd0 ro 0x0 reserved 7:6 utmi_linestate ro 0x0 snapshot of the utmi linestate bus. 5 utmi_suspendm ro 0x0 snapshot of the utmi suspendm signal. 4 utmi_rxvalidh ro 0x0 snapshot of the utmi rxvalidh signal. 3 utmi_rxvalid ro 0x0 snapshot of the utmi rxvalid signal. 2 utmi_rxactive ro 0x0 snapshot of the utmi rxactive signal. 1 utmi_rxerror ro 0x0 snapshot of the utmi rxerror signal. 0 utmi_txready ro 0x0 snapshot of the utmi txready signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 180 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 9.6.10. utmi debug status register 3 description the utmi debug status register 3 holds the observation of internal state machines of the high speed receive. this inclu des the unstuff counter, main fsm, bit counter, squelch-detect fsm, and bit-start fsm. hw_usbphy_debug3_status 0x8007c090 description: empty description. example: empty example. table 200. hw_usbphy_debug3_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 b_cnt_fsm rsrvd1 sq_unlock_fsm rsrvd0 bit_cnt main_hs_rx_fsm unstuff_bit_cnt table 201. hw_usbphy_debug3 _status bit field descriptions bits label rw reset definition 31 rsrvd2 ro 0x0 reserved 30:28 b_cnt_fsm ro 0x0 snapshot of the state ma chine that determines of the count starts at 0 or 1 after the completion of sync. 27:26 rsrvd1 ro 0x0 reserved 25:23 sq_unlock_fsm ro 0x0 snapshot of the stat e machine that detects the removal of squelch and waits for the last transfer to complete. 22 rsrvd0 ro 0x0 reserved 21:12 bit_cnt ro 0x0 snapshot of the bit coun ter that resets at the end of sync and allows the other fsm to know the byte alignment. 11:8 main_hs_rx_fsm ro 0x0 snapshot of the main high-speed fsm. 7:0 unstuff_bit_cnt ro 0x0 snapshot of the unstuff bit counter. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 181 9.6.11. utmi debug status register 4 description the utmi debug status register 4 holds the observation of internal state machines of the high-speed receive. this includes the byte fsm and fifo-send fsm. hw_usbphy_debug4_status 0x8007c0a0 description: empty description. example: empty example. 9.6.12. utmi debug status register 5 description the utmi debug status register 5 holds the observation of internal state machines of the high-speed transmit. this includes the byte fsm and fifo-send fsm. hw_usbphy_debug5_status 0x8007c0b0 table 202. hw_usbphy_debug4_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 byte_fsm rsrvd0 snd_fsm table 203. hw_usbphy_debug4 _status bit field descriptions bits label rw reset definition 31:29 rsrvd1 ro 0x0 reserved 28:16 byte_fsm ro 0x0 snapshot of the stat e machine that determines the number of bytes extracted from the data stream. 15:14 rsrvd0 ro 0x0 reserved 13:0 snd_fsm ro 0x0 snapshot of the stat e machine that controls the byte/word transfer to the fifo. table 204. hw_usbphy_debug5_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 main_fsm rsrvd3 sync_fsm rsrvd2 precharge_fsm rsrvd1 shift_fsm rsrvd0 sof_fsm free datasheet http:/// STMP36XX official product documentation 5/3/06 182 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 9.6.13. utmi debug status register 6 description the utmi debug status register 6 holds the observation of internal state machines of the high-speed transmit. this includes the first eop fsm and eop fsm. hw_usbphy_debug6_status 0x8007c0c0 table 205. hw_usbphy_debug5 _status bit field descriptions bits label rw reset definition 31:28 rsrvd4 ro 0x0 reserved 27:24 main_fsm ro 0x0 snapshot of the main state machine that determines start of transmission. 23:22 rsrvd3 ro 0x0 reserved 21:16 sync_fsm ro 0x0 snapshot of the stat e machine that controls the transmit of sync. 15 rsrvd2 ro 0x0 reserved 14:12 precharge_fsm ro 0x0 snapshot of the stat e machine that controls the transmit of precharge. 11 rsrvd1 ro 0x0 reserved 14:12 shift_fsm ro 0x0 snapshot of the stat e machine that controls the loading of the shift register. 7:5 rsrvd0 ro 0x0 reserved 4:0 sof_fsm ro 0x0 snapshot of the state ma chine that controls the long transmission of the eop for sof. table 206. hw_usbphy_debug6_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd0 first_eop_fsm eop_fsm table 207. hw_usbphy_debug6 _status bit field descriptions bits label rw reset definition 31:11 rsrvd0 ro 0x0 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 9: integrated usb 2.0 phy 183 description: empty description. example: empty example. 9.6.14. utmi debug status register 7 description the utmi debug status register 7 holds the observation of internal state machines of the full-speed receive. th is includes the first eop fsm, main fsm, fifo control fsm, load fifo fsm, unstuff count, bi t count, first data fsm, and eop fsm. hw_usbphy_debug7_status 0x8007c0d0 10:8 first_eop_fsm ro 0x0 snapshot of the st ate machine that determines transition of data to eop. 7:0 eop_fsm ro 0x0 snapshot of the stat e machine that controls the transmit of eop. table 208. hw_usbphy_debug7_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd3 first_data_fsm bit_cnt rsrvd2 unstuff_cnt rsrvd1 ld_fsm rsrvd0 fifo_fsm main_fsm eop_fsm table 209. hw_usbphy_debug7 _status bit field descriptions bits label rw reset definition 31:30 rsrvd3 ro 0x0 reserved 29:28 first_data_fsm ro 0x0 snapshot of the st ate machine that determines transition of sync to data. 27:24 bit_cnt ro 0x0 snapshot of the bit count. 23 rsrvd2 ro 0x0 reserved 22:20 unstuff_cnt ro 0x0 snapshot of the unstuff bit count. 19:18 rsrvd1 ro 0x0 reserved 17:16 ld_fsm ro 0x0 snapshot of the fifo load fsm. 15:14 rsrvd0 ro 0x0 reserved 13:8 fifo_fsm ro 0x0 snapshot of the fifo fsm. 7:4 main_fsm ro 0x0 snapshot of the main fsm. 3:0 eop_fsm ro 0x0 snapshot of the transmission of eop fsm. table 207. hw_usbphy_debug6 _status bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 184 chapter 9: integrated usb 2.0 phy 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 9.6.15. utmi debug status register 8 description the utmi debug status register 8 holds the observation of internal state machines of the full-speed transmit and sie state ma chines. this includes the full-speed main transmit fsm, full-speed shift fsm, receive sie fsm, and transmit sie fsm. hw_usbphy_debug8_status 0x8007c0e0 description: empty description. example: empty example. usbphy xml revision: 1.54 table 210. hw_usbphy_debug8_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rx_sie_fsm tx_sie_fsm rsrvd2 shift_fsm rsrvd1 fs_tx_main_fsm table 211. hw_usbphy_debug8_ status bit field descriptions bits label rw reset definition 31:28 rx_sie_fsm ro 0x0 snapshot of the sie rx fsm. 27:24 tx_sie_fsm ro 0x0 snapshot of the sie tx fsm. 23:10 rsrvd2 ro 0x0 reserved 9:8 shift_fsm ro 0x0 snapshot of the transmit shift fsm. 7 rsrvd1 ro 0x0 reserved 6:0 fs_tx_main_fsm ro 0x0 snapshot of the fifo load fsm. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 185 10. ahb-to-apbh bridge with dma this chapter describes the ahb-to-apbh br idge on the STMP36XX, along with its central dma function and implementation examples. programmable registers are described in section 10.5 . 10.1. overview the ahb-to-apbh bridge provides the st mp36xx with an inexpensive peripheral attachment bus running on the ahb?s hclk. (the ?h? in apbh denotes that the apb h is synchronous to hclk, as compared to apb x , which runs on the crystal- derived xclk.) as shown in figure 32 , the ahb-to-apbh bridge includes the ahb-to-apb pio bridge for memory-mapped i/o to the apb de vices, as well as a central dma facility for devices on this bus and a vectored interrupt controller for the arm926 core. each one of the apb peripherals, including the vectored interr upt controller, are documented in their own chapters elsewhere in this document. ahb-to-apbh dma ahb slave apbh master ahb master ahb apbh ata_nand0 ata_nand1 ata_nand2 ahb-to-apbh bridge interrupt collector spi/sdio/ms hwecc ata_nand3 memcpy figure 32. ahb-to-apbh br idge dma block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 186 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 the dma controller uses the apbh bus to tr ansfer read and write data to and from each peripheral. there is no separate dma bus for these devices. contention between the dma?s use of the apbh bus and the ahb-to-apb bridge functions? use of the apbh is mediated by internal arbitration logic. for contention between these two units, the dma is favored and th e ahb slave will report ?not ready? via its hready output until the bridge transfer can complete. the arbiter tracks repeated lockouts and inverts the priority, guaranteeing the cpu every fourth transfer on the apb. 10.2. ahbh dma the dma supports eight channels of dma services, as shown in table 212 . the shared dma resource allows each independent channel to follow a simple chained command list. command chains are built up using the general structure, as shown in figure 33 . a single command structure or channel command word specifies a number of oper- ations to be performed by the dma in support of a given device. thus, the cpu can set up large units of work, chaining together many dma channel command words, pass them off to the dma, and have no fu rther concern for the device until the dma completion interrupt occurs. the goal here, as with the entire design of the STMP36XX, is to have enoug h intelligence in the dma and the devices to keep the interrupt frequency from any device below 1-khz (arrival intervals longer than one ms). thus, a single command structure can issue 32-bit pio write oper ations to key reg- isters in the associated devic e using the same apb bus and controls that it uses to write dma data bytes to the device. for example, this allows a chain of operations to be issued to the atanand control- ler to send nand command bytes, address bytes, and data transfers where the command and address structure is completely under software control, but the administration of that transfer is handled autonomously by the dma. each dma structure can have from 0 to 15 pio words appended to it. the #pio- words field, if non-zero, instructs the dm a engine to copy these words to the apb, beginning at paddr = 0x0000 and incrementing its paddr for each cycle. table 212. apbh dma channel assignments apbh dma channel # usage 0 hardware ecc controller 1 spi/sdio/ms controller 2 memory copy source 3 memory copy destination 4 ata_nand_device0 5 ata_nand_device1 6 ata_nand_device2 7 ata_nand_device3 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 187 during these operations, the dma drives ps el corresponding to the device associ- ated to the dma channel. the psel-to-dma channel association is defined at syn- thesis time in the STMP36XX. subsequent generations might choose to implement selectable associations for limited cases. the dma master only generates normal wr ite transfers to the apbh. it does not generate sct set, clear, or toggle transfers. once any requested pio words have been transferred to the peripheral, the dma examines the two-bit command field in the channel command structure. table 213 shows the four commands implemented by the dma. dma_write operations copy data byte s to system memory (on-chip ram or sdram) from the associated peripheral. each peripheral has a target paddr value that it expects to receive dma bytes. this association is synthesized in the dma. the dma_write transfer uses the bu ffer_adddress word in the command structure to point to the beginning byte to write data from the peripheral. table 213. apbh dma commands dma command usage 00 no_dma_xfer. perform any reques ted pio word transfers, but terminate command before any dma transfer. 01 dma_write. perform any requested pio word transfers, then perform a dma transfer from the peripheral for the specified number of bytes. 10 dma_read. perform any requested pio word transfers and then perform a dma transfer to the peri pheral for the specified number of bytes. 11 dma_sense. perform any requested pio word transfers, then perform a conditional branch to the next chained device. follow the nextcmd_addr pointer if the peripher al sense is false. follow the buffer_address as a chain pointer if the peripheral sense line is true. this command becomes a no-operation for any channel other than a gpmi channel. nextcmdaddr irqoncmplt xfer_count command cmdpiowords buffer address pioword word 0 word 1 word 2 word 3-n chain semaphore nandlock nandwait4ready wait4endcmd figure 33. ahb-to-apbh bridge dma channel command structure free datasheet http:/// STMP36XX official product documentation 5/3/06 188 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 dma_read operations copy data bytes to the apb peripheral from system mem- ory. the dma engine contains a shared by te aligner that aligns bytes from system memory to or from the peripherals. peripherals always assume little-endian-aligned data arrives or departs on their 32-bit apb. the dma_read transfer uses the buffer_address word in the command st ructure to point to the dma data buffer to be read by the dma_read command. the no_dma_xfer command is used to writ e pio words to a device without per- forming any dma data byte transfers. this command is useful in such applications as activating the atanand devices checkstatus operation. the check status command in the atanand peripheral reads a status byte from the nand device, performs an xor and mask agai nst an expected value supplied as part of the pio transfer. once the read check completes (see section 10.3.2 ), the no_dma_xfer command completes. the result in the per ipheral is that its psense line is driven by the results of the comparison. the sens e flip-flop is only updated by checksta- tus for the device that is executed. at some future point, the chain contains a dma command structure with the fourth and final command value, i.e., the dma_sense command. as each dma command completes, it triggers the dma to load the next dma com- mand structure in the chain. the normal flow list of dma commands is found by fol- lowing the nextcmd_addr pointer in the dma command structure. the dma_sense command uses the dma buffer pointer word of the command struc- ture in a slightly different way. namely, it points to an alternate dma command struc- ture chain or list. the dma_sense command examines the sense line of the associated peripheral. if the sense line is ?true,? then the dma follows the standard list found whose next command is found from the pointer in the nextcmd_addr word of the command structure. if the sense line is ?false,? then the dma follows the alternate list whose next command is found from the pointer in the dma buffer pointer word of the dma_sense command structure (see figure 35 ). the sense command ignores the chain bit, so that bo th pointers must be valid when the dma comes to sense command. if the wait-for-end-command bit (wait4en dcmd) is set in a command structure, then the dma channel waits for the device to signal completion of a command by toggling the apx_endcmcd signal before proceeding to load and execute the next command structure. the semaphore is decremented after the end command is seen. a detailed bit-field view of the dma command structure is shown in table 214 , which shows a field that specifies the number of bytes to be transferred by this dma com- mand. the transfer-count mechanism is du plicated in the associated peripheral, either as an implied or specified count in the peripheral. for example, the hwecc peripheral uses an implied size of 256 bytes for the ssfdc parity block size, while the atanand controller has a corresponding programmable field to specify the number of bytes to transfer at the interface. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 189 figure 35 also shows the chain bit in bit 2 of the second word of the command structure. this bit is set to one if the next_command_address contains a pointer to another dma command structure. if a null pointer (zero) is loaded into the next_command_address, it will not be detected by the dma hardware. only the chain bit indicates whether a valid list exists beyond the current structure. if the irq_finish bit is set in the command structure, then the last act of the dma before loading the next command is to set the interrupt status bit corresponding to the current channel. the st icky interrupt request bit in the dma csr remains set until cleared by software. it can be used to interrupt the cpu. the nand_lock bit is monitored by the dma channel arbiter. once a nand chan- nel ([7:4]) succeeds in the arbiter with its nand_lock bit set, then the arbiter will ignore the other three nand channels until a command is completed in which the nand_lock is not set. notice that the semantic here is that the nand_lock state is to limit scheduling of a non-locked dma. a dma channel can go from unlocked to locked in the arbiter at the beginning of a command when the nand_lock bit is set. when the last dma command of an atomic sequence is completed, the lock should be removed. to accomplish this, the last command does not have the nand_lock bit. it is still locked in the atomic state within the arbiter when the command starts, so that it is the only nand command that can be exe- cuted. at the end, it drops from the atomic state within the arbiter. the nand_wait4ready bit also has a spec ial use for dma channels [7:4], i.e., the atanand device channels. the atanand device supplies a sample of the ready line for the nand device. this ready value is used to hold off of a command with this bit set until the ready line is asse rted to one. once the arbiter sees a com- mand with a wait-for-ready set, it holds off that channel until ready is asserted. note : in ata mode, you must set both hw_apbh_chn_cmd(4).nandwait4ready and hw_apbh_chn_cmd(4).wait4endcmd to get the desired behavior. if you set only hw_apbh_chn_cmd(4).wait4e ndcmd in the dma command set and set hw_gpmi_ctrl0.wait_for_ready in the gpmi command, but do not set table 214. dma channel command word in system memory 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 next_command_address number dma bytes to transfer number pio words to write wait4endcmd decrement semaphore nandwait4ready nandlock irq_complete chain command dma buffer or alternate ccw zero or more pio words to write to the associated peripheral starting at its base address on the apbh bus free datasheet http:/// STMP36XX official product documentation 5/3/06 190 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 hw_apbh_chn_cmd(4).nandwait4ready, the dma channel will continue without waiting for the interrupt. each channel has an eight-bit counting semaphore that controls whether it is in the run or idle state. when the semaphore is non-zero, the channel is ready to run and process commands and dma transfers. whenever a command finishes its dma transfer, it checks the decrement_sema phore bit. if set, it decrements the counting semaphore. if the semaphore goes to zero as a result, then the channel enters the idle state and remains there unt il the semaphore is incremented by soft- ware. when the semaphore goes to non-zero and the channel is in its idle state, then it uses the value in the hw_apbhn_nxtcmdar (next command address register) to fetch a pointer to the next co mmand to process. note: this is a double indirect case. this method allows software to append to a running command list under the protection of the counting semaphore. to start processing the first time, soft ware creates the command list to be pro- cessed. it writes the address of the first command into the hw_apbhn_nxtcmdar register, and then wr ites a one to the counting sema- phore in hw_apbhn_sema. the dm a channel loads hw_apbhn_curcmdar register and then enters the normal stat e machine processing for the next com- mand. when software writes a value to the counting semaphore, it is added to the semaphore count by hardware, protecting the case where both hardware and soft- ware are trying to change the semaphore on the same clock edge. software can examine the value of hw _apbhn_curcmdar at any time to deter- mine the location of the command structure currently being processed. 10.3. implementation examples 10.3.1. hwecc example command chain the example in figure 34 shows how to bring the basic items together to make a simple dma chain to read and check a hw_ecc reed-solomon error-correction block using one dma channel. this ex ample shows three command structures linked together using their normal command-list pointers. ? the first command writes a si ngle pio word to the pioword register, selecting the rs decode operation, etc. this fi rst command also performs a 512-byte dma_read operation to read the data block bytes into the hwecc, where its error is checked. (actually two passes are required; see chapter 14 .) ? a second dma command structure also performs a dma_read operation. this time to read the nine parity bytes. ? when the hwecc computes its error-correcti on information, it writes a fixed-size nine-word error report structure to system memory, using the third dma command structure to perform a dma_write operation. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 191 10.3.2. nand read status polling example figure 35 shows a more complicated scenario. this subset of a nand device work- load shows that the first two command stru ctures are used during the data-write phase of an atanand device write operati on (cle and ale transfers omitted for clarity). ? after writing the data, one must wait until the nand device status register indicates that the write charge has been transferred. this is built into the workload using a check status command in the nand in a loop created from the next two dma command structures. ? the no_dma_transfer command is shown here performing the read check, followed by a dma_sense command to branch the dma command structure list, based on the status of a bit in the external nand device. nextcmd_addr 512 buffer address hw_ecccsr=0x00000003 nextcmd_addr 12 buffer address nextcmd_addr=0 36 buffer address 512-byte data block 9 bytes of parity in a 12-byte block 1 result word plus 8 correction words 1 0 1 10 0 1 pio, chaining, dma read no pio, chaining, dma read no pio,irq, no chaining, dma write 1 0 0 10 0 0 0 0 01 0 pointer to next ccw pointer to dma buffer 0 0 0 figure 34. ahb-to-apbh bridge dma hwecc example command chain free datasheet http:/// STMP36XX official product documentation 5/3/06 192 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 the example in figure 35 shows the workload continuing immediately to the next nand page transfer. however, one could perform a second sense operation to see if an error occurred after the write. one could then point the sense command alter- nate branch at a no_dma_xfer command with the interrupt bit set. if the chain bit is not set on this failure branch, then the cpu is interrupted immediately, and the channel process is also immediately terminated in the presence of a workload- detected nand error bit. note that each word of the three-word dma command structure corresponds to a pio register of the dma that is accessi ble on the apbh bus. normally, the dma copies the next command stru cture onto these registers for processing at the start of each command by following the value of the pointer previously loaded into the nextcmd_addr register. nextcmd_addr 512 buffer address atanand0= read data nextcmd_addr 16 buffer address nextcmd_addr 0 buffer address 512-byte data block 16-byte spare area 1 0 1 10 0 1 pio, chaining, dma read no pio, chaining, dma read 1 pio, chaining, no dma, check nand status & set sense line 1 0 0 10 0 1 0 1 00 0 no pio,irq, no chaining, dma read 0 0 0 10 1 atanand0= check status nextcmd_addr 0 buffer address no pio, chaining, no dma, conditional branch based on sense line 1 0 0 11 0 nextcmd_addr 512 buffer address atanand0= read data nextcmd_addr=0 16 buffer address 512-byte data block 16-byte spare area 1 0 1 10 0 1 pio, chaining, dma read figure 35. ahb-to-apbh bridge dma nand r ead status polling wi th dma sense command free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 193 to start dma processing for the first co mmand, initialize the pio registers of the desired channel, as follows: ? first, load the next command address regist er with a pointer to the first command to be loaded. ? then, write a one to the counting semaphore register. this causes the dma to schedule the targeted channel for dma command structure load, as if it just finished its previous command. 10.3.3. apbh dma and pio bus implementation example figure 36 shows an ahb-to-apb brid ge device interface, and table 215 defines the interface signals used in the implementation example. ahb paddr[15:0] penable pwrite pselect_dev psct[1:0] pwdata[31:0] prdata[31:0] pdmareq pendcmd pnandready hclk hreset_n pbe[3:0] pcmdkick psense ahb2apbh hwecc figure 36. ahb-to-apb bridge device interface free datasheet http:/// STMP36XX official product documentation 5/3/06 194 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 10.4. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. table 215. apbh interface signals signal i/o usage penable o strobe signal used to time all accesses on the apbh bus. the rising edge of penable indicates the beginn ing of an apbh transfer. pwrite o when high, indicates an apbh write access, and when low, a read access. pselect_dev[n:0] o one bit for each pio device on the apbh bus. the bit corresponding to the selected device is driven high when penable is asserted to select one of the pio devices. psct[1:0] o this two-bit field indicates whether the current bus is: 00?normal read, normal write cycle 01?normal read, set bits write cycle 10?normal read, clear bits write cycle 11?normal read, toggle bits write cycle if the targeted pio regist er does not support sct sp ecial cycles, then a normal write cycle is performed by the device, even though a set/clear toggle cycle was requested. these values are based on ahb haddr[3:2]. pbe[3:0] o the byte-enable signals control which by tes of a 32-bit transfer are to be written for a store half or store byte operation. if a device does not support transfers of less than a word size, then it ignores this field. this is the situation for all ip peripherals. paddr[15:0] o the apbh address driven by the apbh bridge. pwdata[31:0] o the write data bus driven by the apbh bridge during write cycles (pwrite is high). prdata[31:0] i the read data bus driven by the separate apbh device during read cycles (pwrite is low). pdmareq[7:0] i this signal is reset by the soft reset signal in each device. it is toggled once for each request. a device must not toggle th is signal until it has been serviced by the dma, a condition recogn ized by noting the pio writ e or read cycles to its various dma data ports. pdmareq[0] is driven by the hwecc. pdmareq[1] is driven by the spi block. pdmareq[3:2] are driven by the mem_cpy device pdmareq[7:4] is driven by the nand/ata pendcmd[7:0] i the device toggles this line at the end of a sense command to notify the dma that a wait4endcmd condition has been satisfied. pcmdkick[7:0] o the apb master produces a state toggle indicating that a device has been ?kicked off? by the dma command processing. pdmasense[7:0] i sense flag from each dma peripheral, used in conditional branching within dma chains. these signals are synchron ous with the apbh or apbx clock as appropriate and are synchronized to hclk within the dma. pnandrdy[7:4] i the gpmi samples the state of the na nd device-ready line and presents it on the corresponding signal. the dma arbiter synchronizes this signal and uses it to process the wait4nandready condition. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 195 10.5. programmable registers this section describes the programmable registers of the ahb-to-apbh bridge block. 10.5.1. ahb-to-apbh bridge control and status register 0 description the ahb-to-apbh bridge cont rol and status register 0 provides overall control of the ahb-to-apbh bridge and dma. hw_apbh_ctrl0 0x80004000 hw_apbh_ctrl0_set 0x80004004 hw_apbh_ctrl0_clr 0x80004008 hw_apbh_ctrl0_tog 0x8000400c table 216. hw_apbh_ctrl0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsvd2 reset_channel clkgate_channel freeze_channel table 217. hw_apbh_ctrl0 bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 set this bit to zero to enable normal apbh dma operation. set this bit to one (default) to disable clocking with the apbh dma and hold it in its reset (lowest power) state. this bit can be turned on and then off to reset the apbh dma block to its default state. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. 29:24 rsvd2 ro 0x000000 reserved , always set to zero. 23:16 reset_channel rw 0x0 setting a bit in this field causes the dma controller to take the corresponding channel through its reset state. the bit is reset after the channel resources are cleared. hwecc = 0x01 ssp = 0x02 src = 0x04 dest = 0x08 ata = 0x10 nand0 = 0x10 nand1 = 0x20 nand2 = 0x30 nand3 = 0x40 free datasheet http:/// STMP36XX official product documentation 5/3/06 196 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 10.5.2. ahb-to-apbh bridge control and status register 1 description the ahb-to-apbh bridge cont rol and status register 1 provides overall control of the interrupts generated by the ahb-to-apbh dma. hw_apbh_ctrl1 0x80004010 hw_apbh_ctrl1_set 0x80004014 hw_apbh_ctrl1_clr 0x80004018 hw_apbh_ctrl1_tog 0x8000401c 15:8 clkgate_channel rw 0x00 these bits must be set to zero for normal operation of each channel. when set to one, they gate off the individual clocks to the channels. hwecc = 0x01 ssp = 0x02 src = 0x04 dest = 0x08 ata = 0x10 nand0 = 0x10 nand1 = 0x20 nand2 = 0x30 nand3 = 0x40 7:0 freeze_channel rw 0x0 setting a bit in this field will freeze the dma channel associated with it. this field is a direct input to the dma channel arbiter. when frozen, the channel is denied access to the central dma resources. hwecc = 0x01 ssp = 0x02 src = 0x04 dest = 0x08 ata = 0x10 nand0 = 0x10 nand1 = 0x20 nand2 = 0x30 nand3 = 0x40 table 218. hw_apbh_ctrl1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 ch7_cmdcmplt_irq_en ch6_cmdcmplt_irq_en ch5_cmdcmplt_irq_en ch4_cmdcmplt_irq_en ch3_cmdcmplt_irq_en ch2_cmdcmplt_irq_en ch1_cmdcmplt_irq_en ch0_cmdcmplt_irq_en rsvd1 ch7_cmdcmplt_irq ch6_cmdcmplt_irq ch5_cmdcmplt_irq ch4_cmdcmplt_irq ch3_cmdcmplt_irq ch2_cmdcmplt_irq ch1_cmdcmplt_irq ch0_cmdcmplt_irq table 217. hw_apbh_ctrl0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 197 table 219. hw_apbh_ctrl1 bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x000000 reserved , always set to zero. 23 ch7_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbh dma channel 7. 22 ch6_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbh dma channel 6. 21 ch5_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbh dma channel 5. 20 ch4_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbh dma channel 4. 19 ch3_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbh dma channel 3. 18 ch2_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbh dma channel 2. 17 ch1_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbh dma channel 1. 16 ch0_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbh dma channel 0. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7 ch7_cmdcmplt_irq rw 0x0 interrupt request status bit for apbh dma channel 7. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 6 ch6_cmdcmplt_irq rw 0x0 interrupt request status bit for apbh dma channel 6. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 5 ch5_cmdcmplt_irq rw 0x0 interrupt request status bit for apbh dma channel 5. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 4 ch4_cmdcmplt_irq rw 0x0 interrupt request status bit for apbh dma channel 4. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 3 ch3_cmdcmplt_irq rw 0x0 interrupt request status bit for apbh dma channel 3. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 2 ch2_cmdcmplt_irq rw 0x0 interrupt request status bit for apbh dma channel 2. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. free datasheet http:/// STMP36XX official product documentation 5/3/06 198 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register contains the per-channel interrupt status bits and the per-channel interrupt enable bits. each channel has a dedicated interrupt vector in the vectored interrupt controller. example: bf_wr(apbh_ctrl1, ch5_cmdcmplt_irq, 0); // use bitfield write macro bf_apbh_ctrl1.ch5_cmdcmplt_irq = 0; // or, assign to register struct's bitfield 10.5.3. ahb-to-apbh dma device assignment register description this register allows reas signment of the apbh device connected to the dma chan- nels. hw_apbh_devsel 0x80004020 description: this register contains the per channel interrupt status bits and the per channel interrupt enable bits. each channel has a dedicated interrupt vector in the vectored interrupt controller. 1 ch1_cmdcmplt_irq rw 0x0 interrupt request status bit for apbh dma channel 1. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 0 ch0_cmdcmplt_irq rw 0x0 interrupt request status bit for apbh dma channel 0. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. table 220. hw_apbh_devsel 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 table 221. hw_apbh_devsel bit field descriptions bits label rw reset definition 31:28 ch7 ro 0x0 reserved. 27:24 ch6 ro 0x0 reserved. 23:20 ch5 ro 0x0 reserved. 19:16 ch4 ro 0x0 reserved. 15:12 ch3 ro 0x0 reserved. 11:8 ch2 ro 0x0 reserved. 7:4 ch1 ro 0x0 reserved. 3:0 ch0 ro 0x0 reserved. table 219. hw_apbh_ctrl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 199 example: empty example. 10.5.4. apbh dma channel 0 current command address register description the apbh dma channel 0 curr ent command address regist er points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbh_ch0_curcmdar 0x80004030 description: apbh dma channel 0 is controlled by a variable-sized comm and structure. this register points to the command structure currently being executed. example: pcurcmd = (hw_apbh_chn_cmd_t *) hw_apbh_chn_curcmdar_rd(0); // read the whole register, since there is only one field pcurcmd = (hw_apbh_chn_cmd_t *) bf_rdn(apbh_chn_curcmdar, 0, cmd_addr); // or, use multi- register bitfield read macro pcurcmd = (hw_apbh_chn_cmd_t *) hw_apbh_chn_curcmdar(0).cmd_addr; // or, assign from bit- field of indexed register's struct 10.5.5. apbh dma channel 0 next command address register description the apbh dma channel 0 next command address register contains the address of the next multiword command to be executed. commands are threaded on the command address. set chain to 1 in the dma command word to process com- mand lists. hw_apbh_ch0_nxtcmdar 0x80004040 table 222. hw_apbh_ch0_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 223. hw_apbh_ch0_curcmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 0. table 224. hw_apbh_ch0_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 225. hw_apbh_ch0_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 0. free datasheet http:/// STMP36XX official product documentation 5/3/06 200 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: apbh dma channel 0 is controlled by a variable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 0 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: hw_apbh_chn_nxtcmdar_wr(0, (reg32_t) pcommandtwostructure); // write the entire register, since there is only one field bf_wrn(apbh_chn_nxtcmdar, 0, (reg32_t) pcommandtwostructure); // or, use multi-register bitfield write macro hw_apbh_chn_nxtcmdar(0).cmd_addr = (reg32_t) pcommandtwostructure; // or, assign to bit- field of indexed register's struct 10.5.6. apbh dma channel 0 command register description the apbh dma channel 0 co mmand register specifie s the dma transaction to perform for the current command chain item. hw_apbh_ch0_cmd 0x80004050 table 226. hw_apbh_ch0_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command table 227. hw_apbh_ch0_c md bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the hwecc device hw_hwecc_data register. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the hwecc, st arting with the base pio address of the hwecc (hw_hwecc_ctrl) and incrementing from there. zero means transfer no command words. 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbh device to the dma before starting the next dma command. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 201 description: the command register controls the overall operation of each dma command for this channel. it includes the number of by tes to transfer to or from the device, the number of apb pio command words included with this command structure, whether to interrupt at command completion, whether to chain an additional com- mand to the end of this one and whether th is transfer is a read or write dma trans- fer. example: hw_apbh_chn_cmd_t dma_cmd; dma_cmd.xfer_count = 512; // transfer 512 bytes 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5 nandwait4ready ro 0x0 a value of one indicates that the ata/nand dma channel will wait until the ata/nand device reports 'ready' before executing the command. it is ignored for non-ata/nand dma channels. 4 nandlock ro 0x0 a value of one indicates that the ata/nand dma channel will remain "locked" in the arbiter at the expense of other ata/nand dma channels. it is ignored for non-ata/nand dma channels. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbh_ch0_cmdar to find the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the hwecc (apb pio read) to the system memory (ahb master write) 10- read transfer 11- sense no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. dma_sense = 0x3 perform any requested pio word transfers and then perform a conditional branch to the next chained device. follow the nexcmd_addr pointer if the per pheral sense is true. follow the buffer_address as a chain pointer if the peripheral sense line is false. table 227. hw_apbh_ch0_c md bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 202 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 dma_cmd.command = bv_apbh_chn_cmd_command__dma_write; // transfer to system memory from peripheral device dma_cmd.chain = 1; // chain an additional command structure on to the list dma_cmd.irqoncmplt = 1; // generate an interrupt on completion of this command structure 10.5.7. apbh dma channel 0 buffer address register description the apbh dma channel 0 buffer address re gister contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address, which means transfers can start on any byte boundary. hw_apbh_ch0_bar 0x80004060 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: hw_apbh_chn_bar_t dma_data; dma_data.address = (reg32_t) pdatabuffer; 10.5.8. apbh dma channel 0 semaphore register description the apbh dma channel 0 sema phore register is used to synchronize the cpu instruction stream and the dma chain processing state. hw_apbh_ch0_sema 0x80004070 table 228. hw_apbh_ch0_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 229. hw_apbh_ch0_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 230. hw_apbh_ch0_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 203 description: each dma channel has an 8-bit counting semaphore that is used to synchronize between the program stream and and the dma chain processing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is stalled until software increments the semaphore count. example: bf_wr(apbh_chn_sema, 0, increment_sema, 2); // increment semaphore by two current_sema = bf_rd(apbh_chn_sema, 0, phore); // get instantaneous value 10.5.9. ahb-to-apbh dma channel 0 debug register 1 description this register gives debug visibility into the apbh dm a channel 0 state machine and controls. hw_apbh_ch0_debug1 0x80004080 table 231. hw_apbh_ch0_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. table 232. hw_apbh_ch0_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine free datasheet http:/// STMP36XX official product documentation 5/3/06 204 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 table 233. hw_apbh_ch0_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit which indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 205 description: this register allows debug vi sibility of the apbh dma channel 0. example: empty example. 10.5.10. ahb-to-apbh dma channel 0 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 0. hw_apbh_ch0_debug2 0x80004090 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 0 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 233. hw_apbh_ch0_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 206 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug vi sibility of the apbh dma channel 0. example: empty example. 10.5.11. apbh dma channel 1 current command address register description the apbh dma channel 1 curr ent command address regist er points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbh_ch1_curcmdar 0x800040a0 description: apbh dma channel 1 is controlled by a variable-sized comm and structure. this register points to the command structure currently being executed. example: pcurcmd = (hw_apbh_chn_cmd_t *) hw_apbh_chn_curcmdar_rd(1); // read the whole register, since there is only one field table 234. hw_apbh_ch0_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 235. hw_apbh_ch0_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 236. hw_apbh_ch1_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 237. hw_apbh_ch1_curcmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 1. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 207 pcurcmd = (hw_apbh_chn_cmd_t *) bf_rdn(apbh_chn_curcmdar, 1, cmd_addr); // or, use multi- register bitfield read macro pcurcmd = (hw_apbh_chn_cmd_t *) hw_apbh_chn_curcmdar(1).cmd_addr; // or, assign from bit- field of indexed register's struct 10.5.12. apbh dma channel 1 next command address register description the apbh dma channel 1 next command address register contains the address of the next multiword command to be executed. commands are threaded on the command address. set chain to 1 in the dma command word to process com- mand lists. hw_apbh_ch1_nxtcmdar 0x800040b0 description: apbh dma channel 1 is controlled by a variable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 1 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: hw_apbh_chn_nxtcmdar_wr(1, (reg32_t) pcommandtwostructure); // write the entire register, since there is only one field bf_wrn(apbh_chn_nxtcmdar, 1, (reg32_t) pcommandtwostructure); // or, use multi-register bitfield write macro hw_apbh_chn_nxtcmdar(1).cmd_addr = (reg32_t) pcommandtwostructure; // or, assign to bit- field of indexed register's struct 10.5.13. apbh dma channel 1 command register description the apbh dma channel 1 command register specifies the cycle to perform for the current command chain item. hw_apbh_ch1_cmd 0x800040c0 table 238. hw_apbh_ch1_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 239. hw_apbh_ch1_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 1. free datasheet http:/// STMP36XX official product documentation 5/3/06 208 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 table 240. hw_apbh_ch1_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command table 241. hw_apbh_ch1_c md bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate pio register in the ssp device hw_ssp_data register. a va lue of 0 indi cates a 64- kbyte transfer size. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the ssp, starting with the base pio address of the ssp (hw_ssp_ctrl0) an d incrementing from there. zero means transfer no command words. 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbh device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5 nandwait4ready ro 0x0 a value of one indicates that the ata/nand dma channel will will wait until the ata/nand device reports 'ready' before execute the command. it is ignored for non-ata/nand dma channels. 4 nandlock ro 0x0 a value of one indicates that the ata/nand dma channel will remain "locked" in the arbiter at the expense of other ata/nand dma channels. it is ignored for non-ata/nand dma channels. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 209 description: the command register controls the overall operation of each dma command for this channel. it includes the number of by tes to transfer to or from the device, the number of apb pio command words included with this command structure, whether to interrupt at command completion, whether to chain an additional com- mand to the end of this one and whether th is transfer is a read or write dma trans- fer. example: empty example. 10.5.14. apbh dma channel 1 buffer address register description the apbh dma channel 1 buffer address re gister contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address, which means transfers can start on any byte boundary. hw_apbh_ch1_bar 0x800040d0 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbh_ch1_cmdar to find the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the ssp (apb pio read) to the system memo ry (ahb master write). 10- read transfer 11- sense no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. dma_sense = 0x3 perform any requested pio word transfers and then perform a conditional branch to the next chained device. follow the nexcmd_addr pointer if the per pheral sense is true. follow the buffer_address as a chain pointer if the peripheral sense line is false. table 242. hw_apbh_ch1_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 243. hw_apbh_ch1_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 241. hw_apbh_ch1_c md bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 210 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: hw_apbh_chn_bar_t dma_data; dma_data.address = (reg32_t) pdatabuffer; 10.5.15. apbh dma channel 1 semaphore register description the apbh dma channel 1 sema phore register is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbh_ch1_sema 0x800040e0 description: each dma channel has an 8-bit counting semaphore that is used to synchronize between the program stream and and the dma chain processing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is stalled until software increments the semaphore count. table 244. hw_apbh_ch1_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema table 245. hw_apbh_ch1_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 211 example: bf_wr(apbh_chn_sema, 1, increment_sema, 2); // increment semaphore by two current_sema = bf_rd(apbh_chn_sema, 1, phore); // get instantaneous value 10.5.16. ahb-to-apbh dma channel 1 debug register 1 description this register gives debug visibility into the apbh dm a channel 1 state machine and controls. hw_apbh_ch1_debug1 0x800040f0 table 246. hw_apbh_ch1_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine table 247. hw_apbh_ch1_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflect the internal bit which indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflect the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflect the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflect the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflect the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 212 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug vi sibility of the apbh dma channel 1. example: empty example. 10.5.17. ahb-to-apbh dma channel 1 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 1. hw_apbh_ch1_debug2 0x80004100 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 1 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 247. hw_apbh_ch1_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 213 description: this register allows debug vi sibility of the apbh dma channel 1. example: empty example. 10.5.18. apbh dma channel 2 current command address register description the apbh dma channel 2 curr ent command address regist er points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbh_ch2_curcmdar 0x80004110 description: apbh dma channel 2 is controlled by a variable-sized comm and structure. this register points to the command structure currently being executed. example: empty example. table 248. hw_apbh_ch1_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 249. hw_apbh_ch1_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 250. hw_apbh_ch2_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 251. hw_apbh_ch2_curcmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 2. free datasheet http:/// STMP36XX official product documentation 5/3/06 214 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 10.5.19. apbh dma channel 2 next command address register description the apbh dma channel 2 next command address register points to the next multiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbh_ch2_nxtcmdar 0x80004120 description: apbh dma channel 2 is controlled by a variable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 2 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 10.5.20. apbh dma channel 2 command register description the apbh dma channel 2 command register specifies the cycle to perform for the current command chain item. hw_apbh_ch2_cmd 0x80004130 table 252. hw_apbh_ch2_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 253. hw_apbh_ch2_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 2. table 254. hw_apbh_ch2_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 215 table 255. hw_apbh_ch2_c md bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the memcpy device hw_memcpy_data register. a value of 0 indicates a 64-kbyte transfer size. 15:12 cmdwords ro 0x00 this field contains the number of command words to send to the memcpy, starting with the base pio address of the memcpy (hw_memcpy_ctrl) and incrementing from there. zero means transfer no command words. 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbh device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5 nandwait4ready ro 0x0 a value of one indicates that the ata/nand dma channel will will wait until the ata/nand device reports 'ready' before execute the command. it is ignored for non-ata/nand dma channels. 4 nandlock ro 0x0 a value of one indicates that the ata/nand dma channel will remain "locked" in the arbiter at the expense of other ata/nand dma channels. it is ignored for non-ata/nand dma channels. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. free datasheet http:/// STMP36XX official product documentation 5/3/06 216 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: the command register controls the overall operation of each dma command for this channel. it includes the number of by tes to transfer to or from the device, the number of apb pio command words included with this command structure, whether to interrupt at command completion, whether to chain an additional com- mand to the end of this one and whether th is transfer is a read or write dma trans- fer. example: empty example. 10.5.21. apbh dma channel 2 buffer address register description the apbh dma channel 2 buffer address re gister contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address, which means transfers can start on any byte boundary. hw_apbh_ch2_bar 0x80004140 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbh_ch2_cmdar to find the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbh device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- sense no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. dma_sense = 0x3 perform any requested pio word transfers and then perform a conditional branch to the next chained device. follow the nexcmd_addr pointer if the per pheral sense is true. follow the buffer_address as a chain pointer if the peripheral sense line is false. table 256. hw_apbh_ch2_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 255. hw_apbh_ch2_c md bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 217 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 10.5.22. apbh dma channel 2 semaphore register description the apbh dma channel 2 sema phore register is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbh_ch2_sema 0x80004150 description: table 257. hw_apbh_ch2_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 258. hw_apbh_ch2_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema table 259. hw_apbh_ch2_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. free datasheet http:/// STMP36XX official product documentation 5/3/06 218 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 each dma channel has an 8-bit counting semaphore that is used to synchronize between the program stream and and the dma chain processing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is stalled until software increments the semaphore count. example: empty example. 10.5.23. ahb-to-apbh dma channel 2 debug register 1 description this register gives debug visibility into the apbh dm a channel 2 state machine and controls. hw_apbh_ch2_debug1 0x80004160 table 260. hw_apbh_ch2_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine table 261. hw_apbh_ch2_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflect the internal bit which indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflect the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflect the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflect the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflect the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 219 description: this register allows debug vi sibility of the apbh dma channel 2. example: empty example. 10.5.24. ahb-to-apbh dma channel 2 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 2. hw_apbh_ch2_debug2 0x80004170 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 2 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 261. hw_apbh_ch2_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 220 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug vi sibility of the apbh dma channel 2. example: empty example. 10.5.25. apbh dma channel 3 current command address register description the apbh dma channel 3 curr ent command address regist er points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbh_ch3_curcmdar 0x80004180 description: apbh dma channel 3 is controlled by a variable-sized comm and structure. this register points to the command structure currently being executed. example: empty example. table 262. hw_apbh_ch2_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 263. hw_apbh_ch2_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 264. hw_apbh_ch3_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 265. hw_apbh_ch3_curcmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 3. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 221 10.5.26. apbh dma channel 3 next command address register description the apbh dma channel 3 next command address register points to the next multiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbh_ch3_nxtcmdar 0x80004190 description: apbh dma channel 3 is controlled by a variable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 3 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 10.5.27. apbh dma channel 3 command register description the apbh dma channel 3 command register specifies the cycle to perform for the current command chain item. hw_apbh_ch3_cmd 0x800041a0 table 266. hw_apbh_ch3_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 267. hw_apbh_ch3_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 3. table 268. hw_apbh_ch3_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 222 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 table 269. hw_apbh_ch3_c md bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the memcpy device hw_memcpy_data register. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the memcpy, starting with the base pio address of the memcpy (hw_memcpy_ctrl) and incrementing from there. zero means transfer no command words. 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbh device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5 nandwait4ready ro 0x0 a value of one indicates that the ata/nand dma channel will will wait until the ata/nand device reports 'ready' before execute the command. it is ignored for non-ata/nand dma channels. 4 nandlock ro 0x0 a value of one indicates that the ata/nand dma channel will remain "locked" in the arbiter at the expense of other ata/nand dma channels. it is ignored for non-ata/nand dma channels. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 223 description: the command register controls the overall operation of each dma command for this channel. it includes the number of by tes to transfer to or from the device, the number of apb pio command words included with this command structure, whether to interrupt at command completion, whether to chain an additional com- mand to the end of this one and whether th is transfer is a read or write dma trans- fer. example: empty example. 10.5.28. apbh dma channel 3 buffer address register description the apbh dma channel 3 buffer address re gister contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address, which means transfers can start on any byte boundary. hw_apbh_ch3_bar 0x800041b0 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbh_ch3_cmdar to find the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbh device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- sense no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. dma_sense = 0x3 perform any requested pio word transfers and then perform a conditional branch to the next chained device. follow the nexcmd_addr pointer if the per pheral sense is true. follow the buffer_address as a chain pointer if the peripheral sense line is false. table 270. hw_apbh_ch3_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 269. hw_apbh_ch3_c md bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 224 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 10.5.29. apbh dma channel 3 semaphore register description the apbh dma channel 3 sema phore register is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbh_ch3_sema 0x800041c0 description: table 271. hw_apbh_ch3_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 272. hw_apbh_ch3_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema table 273. hw_apbh_ch3_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 225 each dma channel has an 8-bit counting semaphore that is used to synchronize between the program stream and and the dma chain processing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is stalled until software increments the semaphore count. example: empty example. 10.5.30. ahb-to-apbh dma channel 3 debug register 1 description this register gives debug visibility into the apbh dm a channel 3 state machine and controls. hw_apbh_ch3_debug1 0x800041d0 table 274. hw_apbh_ch3_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine table 275. hw_apbh_ch3_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflect the internal bit which indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflect the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflect the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflect the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflect the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 226 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug vi sibility of the apbh dma channel 3. example: empty example. 10.5.31. ahb-to-apbh dma channel 3 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 3. hw_apbh_ch3_debug2 0x800041e0 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 3 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 275. hw_apbh_ch3_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 227 description: this register allows debug vi sibility of the apbh dma channel 3. example: empty example. 10.5.32. apbh dma channel 4 current command address register description the apbh dma channel 4 curr ent command address regist er points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbh_ch4_curcmdar 0x800041f0 description: apbh dma channel 4 is controlled by a variable-sized comm and structure. this register points to the command structure currently being executed. example: empty example. table 276. hw_apbh_ch3_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 277. hw_apbh_ch3_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 278. hw_apbh_ch4_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 279. hw_apbh_ch4_curcmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 4. free datasheet http:/// STMP36XX official product documentation 5/3/06 228 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 10.5.33. apbh dma channel 4 next command address register description the apbh dma channel 4 next command address register points to the next multiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbh_ch4_nxtcmdar 0x80004200 description: apbh dma channel 4 is controlled by a variable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 4 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 10.5.34. apbh dma channel 4 command register description the apbh dma channel 4 command register specifies the cycle to perform for the current command chain item. hw_apbh_ch4_cmd 0x80004210 table 280. hw_apbh_ch4_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 281. hw_apbh_ch4_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 4. table 282. hw_apbh_ch4_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 229 table 283. hw_apbh_ch4_c md bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the gpmi atanand_0 device hw_gpmi_data register. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the gpmi, starti ng with the base pio address of the gpmi (hw_gpmi_ctrl0) and incrementing from there. zero means transfer no command words. 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbh device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5 nandwait4ready ro 0x0 a value of one indicates that the ata/nand dma channel will will wait until the ata/nand device reports 'ready' before execute the command. it is ignored for non-ata/nand dma channels. 4 nandlock ro 0x0 a value of one indicates that the ata/nand dma channel will remain "locked" in the arbiter at the expense of other ata/nand dma channels. it is ignored for non-ata/nand dma channels. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. free datasheet http:/// STMP36XX official product documentation 5/3/06 230 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: the command register controls the overall operation of each dma command for this channel. it includes the number of by tes to transfer to or from the device, the number of apb pio command words included with this command structure, whether to interrupt at command completion, whether to chain an additional com- mand to the end of this one and whether th is transfer is a read or write dma trans- fer. example: empty example. 10.5.35. apbh dma channel 4 buffer address register description the apbh dma channel 4 buffer address re gister contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address, which means transfers can start on any byte boundary. hw_apbh_ch4_bar 0x80004220 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbh_ch4_cmdar to find the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the gpmi (apb pio read) to the system memory (ahb master write). 10- read transfer 11- sense no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. dma_sense = 0x3 perform any requested pio word transfers and then perform a conditional branch to the next chained device. follow the nexcmd_addr pointer if the per pheral sense is true. follow the buffer_address as a chain pointer if the peripheral sense line is false. table 284. hw_apbh_ch4_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 283. hw_apbh_ch4_c md bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 231 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 10.5.36. apbh dma channel 4 semaphore register description the apbh dma channel 4 sema phore register is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbh_ch4_sema 0x80004230 description: table 285. hw_apbh_ch4_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 286. hw_apbh_ch4_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema table 287. hw_apbh_ch4_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. free datasheet http:/// STMP36XX official product documentation 5/3/06 232 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 each dma channel has an 8-bit counting semaphore that is used to synchronize between the program stream and and the dma chain processing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is stalled until software increments the semaphore count. example: empty example. 10.5.37. ahb-to-apbh dma channel 4 debug register 1 description this register gives debug visibility into the apbh dm a channel 4 state machine and controls. hw_apbh_ch4_debug1 0x80004240 table 288. hw_apbh_ch4_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end sense ready lock nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine table 289. hw_apbh_ch4_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27 sense ro 0x0 this bit reflects the current state of the gpmi sense signal sent from the apb gpmi device. 26 ready ro 0x0 this bit reflects the current state of the gpmi ready signal sent from the apb gpmi device. 25 lock ro 0x0 this bit reflects the current state of the dma channel lock for a gpmi channel. 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit which indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 233 description: this register allows debug vi sibility of the apbh dma channel 4. example: empty example. 10.5.38. ahb-to-apbh dma channel 4 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 4. hw_apbh_ch4_debug2 0x80004250 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 4 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 289. hw_apbh_ch4_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 234 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug vi sibility of the apbh dma channel 4. example: empty example. 10.5.39. apbh dma channel 5 current command address register description the apbh dma channel 5 curr ent command address regist er points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbh_ch5_curcmdar 0x80004260 description: apbh dma channel 5 is controlled by a variable-sized comm and structure. this register points to the command structure currently being executed. example: empty example. table 290. hw_apbh_ch4_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 291. hw_apbh_ch4_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 292. hw_apbh_ch5_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 293. hw_apbh_ch5_curcmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 5. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 235 10.5.40. apbh dma channel 5 next command address register description the apbh dma channel 5 next command address register points to the next multiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbh_ch5_nxtcmdar 0x80004270 description: apbh dma channel 5 is controlled by a variable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 5 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 10.5.41. apbh dma channel 5 command register description the apbh dma channel 5 command register specifies the cycle to perform for the current command chain item. hw_apbh_ch5_cmd 0x80004280 table 294. hw_apbh_ch5_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 295. hw_apbh_ch5_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 5. table 296. hw_apbh_ch5_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 236 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 table 297. hw_apbh_ch5_c md bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the gpmi atanand_1 device hw_gpmi_data register. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the gpmi, starti ng with the base pio address of the gpmi (hw_gpmi_ctrl0) and incrementing from there. zero means transfer no command words. 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbh device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5 nandwait4ready ro 0x0 a value of one indicates that the ata/nand dma channel will will wait until the ata/nand device reports 'ready' before execute the command. it is ignored for non-ata/nand dma channels. 4 nandlock ro 0x0 a value of one indicates that the ata/nand dma channel will remain "locked" in the arbiter at the expense of other ata/nand dma channels. it is ignored for non-ata/nand dma channels. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 237 description: the command register controls the overall operation of each dma command for this channel. it includes the number of by tes to transfer to or from the device, the number of apb pio command words included with this command structure, whether to interrupt at command completion, whether to chain an additional com- mand to the end of this one and whether th is transfer is a read or write dma trans- fer. example: empty example. 10.5.42. apbh dma channel 5 buffer address register description the apbh dma channel 5 buffer address re gister contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address, which means transfers can start on any byte boundary. hw_apbh_ch5_bar 0x80004290 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbh_ch5_cmdar to find the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the gpmi (apb pio read) to the system memory (ahb master write). 10- read transfer 11- sense no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. dma_sense = 0x3 perform any requested pio word transfers and then perform a conditional branch to the next chained device. follow the nexcmd_addr pointer if the per pheral sense is true. follow the buffer_address as a chain pointer if the peripheral sense line is false. table 298. hw_apbh_ch5_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 297. hw_apbh_ch5_c md bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 238 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 10.5.43. apbh dma channel 5 semaphore register description the apbh dma channel 5 sema phore register is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbh_ch5_sema 0x800042a0 description: table 299. hw_apbh_ch5_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 300. hw_apbh_ch5_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema table 301. hw_apbh_ch5_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 239 each dma channel has an 8-bit counting semaphore that is used to synchronize between the program stream and and the dma chain processing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is stalled until software increments the semaphore count. example: empty example. 10.5.44. ahb-to-apbh dma channel 5 debug register 1 description this register gives debug visibility into the apbh dm a channel 5 state machine and controls. hw_apbh_ch5_debug1 0x800042b0 table 302. hw_apbh_ch5_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end sense ready lock nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine table 303. hw_apbh_ch5_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27 sense ro 0x0 this bit reflects the current state of the gpmi sense signal sent from the apb gpmi device. 26 ready ro 0x0 this bit reflects the current state of the gpmi ready signal sent from the apb gpmi device. 25 lock ro 0x0 this bit reflects the current state of the dma channel lock for a gpmi channel. 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit which indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 240 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug vi sibility of the apbh dma channel 5. example: empty example. 10.5.45. ahb-to-apbh dma channel 5 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 5. hw_apbh_ch5_debug2 0x800042c0 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 5 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 303. hw_apbh_ch5_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 241 description: this register allows debug vi sibility of the apbh dma channel 5. example: empty example. 10.5.46. apbh dma channel 6 current command address register description the apbh dma channel 6 curr ent command address regist er points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbh_ch6_curcmdar 0x800042d0 description: apbh dma channel 6 is controlled by a variable-sized comm and structure. this register points to the command structure currently being executed. example: empty example. table 304. hw_apbh_ch5_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 305. hw_apbh_ch5_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 306. hw_apbh_ch6_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 307. hw_apbh_ch6_curcmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 6. free datasheet http:/// STMP36XX official product documentation 5/3/06 242 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 10.5.47. apbh dma channel 6 next command address register description the apbh dma channel 6 next command address register points to the next multiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbh_ch6_nxtcmdar 0x800042e0 description: apbh dma channel 6 is controlled by a variable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 6 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 10.5.48. apbh dma channel 6 command register description the apbh dma channel 6 command register specifies the cycle to perform for the current command chain item. hw_apbh_ch6_cmd 0x800042f0 table 308. hw_apbh_ch6_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 309. hw_apbh_ch6_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 6. table 310. hw_apbh_ch6_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 243 table 311. hw_apbh_ch6_c md bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the gpmi atanand_2 device hw_gpmi_data register. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the gpmi, starti ng with the base pio address of the gpmi (hw_gpmi_ctrl0) and incrementing from there. zero means transfer no command words. 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbh device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5 nandwait4ready ro 0x0 a value of one indicates that the ata/nand dma channel will will wait until the ata/nand device reports 'ready' before execute the command. it is ignored for non-ata/nand dma channels. 4 nandlock ro 0x0 a value of one indicates that the ata/nand dma channel will remain "locked" in the arbiter at the expense of other ata/nand dma channels. it is ignored for non-ata/nand dma channels. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. free datasheet http:/// STMP36XX official product documentation 5/3/06 244 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: the command register controls the overall operation of each dma command for this channel. it includes the number of by tes to transfer to or from the device, the number of apb pio command words included with this command structure, whether to interrupt at command completion, whether to chain an additional com- mand to the end of this one and whether th is transfer is a read or write dma trans- fer. example: empty example. 10.5.49. apbh dma channel 6 buffer address register description the apbh dma channel 6 buffer address re gister contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address, which means transfers can start on any byte boundary. hw_apbh_ch6_bar 0x80004300 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbh_ch6_cmdar to find the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the gpmi (apb pio read) to the system memory (ahb master write). 10- read transfer 11- sense no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. dma_sense = 0x3 perform any requested pio word transfers and then perform a conditional branch to the next chained device. follow the nexcmd_addr pointer if the per pheral sense is true. follow the buffer_address as a chain pointer if the peripheral sense line is false. table 312. hw_apbh_ch6_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 311. hw_apbh_ch6_c md bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 245 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 10.5.50. apbh dma channel 6 semaphore register description the apbh dma channel 6 sema phore register is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbh_ch6_sema 0x80004310 description: table 313. hw_apbh_ch6_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 314. hw_apbh_ch6_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema table 315. hw_apbh_ch6_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. free datasheet http:/// STMP36XX official product documentation 5/3/06 246 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 each dma channel has an 8-bit counting semaphore that is used to synchronize between the program stream and and the dma chain processing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is stalled until software increments the semaphore count. example: empty example. 10.5.51. ahb-to-apbh dma channel 6 debug register 1 description this register gives debug visibility into the apbh dm a channel 6 state machine and controls. hw_apbh_ch6_debug1 0x80004320 table 316. hw_apbh_ch6_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end sense ready lock nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine table 317. hw_apbh_ch6_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27 sense ro 0x0 this bit reflects the current state of the gpmi sense signal sent from the apb gpmi device. 26 ready ro 0x0 this bit reflects the current state of the gpmi ready signal sent from the apb gpmi device. 25 lock ro 0x0 this bit reflects the current state of the dma channel lock for a gpmi channel. 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit which indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 247 description: this register allows debug vi sibility of the apbh dma channel 6. example: empty example. 10.5.52. ahb-to-apbh dma channel 6 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 6. hw_apbh_ch6_debug2 0x80004330 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 6 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 317. hw_apbh_ch6_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 248 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug vi sibility of the apbh dma channel 6. example: empty example. 10.5.53. apbh dma channel 7 current command address register description the apbh dma channel 7 curr ent command address regist er points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbh_ch7_curcmdar 0x80004340 description: apbh dma channel 7 is controlled by a variable-sized comm and structure. this register points to the command structure currently being executed. example: empty example. table 318. hw_apbh_ch6_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 319. hw_apbh_ch6_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 320. hw_apbh_ch7_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 321. hw_apbh_ch7_curcmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 7. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 249 10.5.54. apbh dma channel 7 next command address register description the apbh dma channel 7 next command address register points to the next multiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbh_ch7_nxtcmdar 0x80004350 description: apbh dma channel 7 is controlled by a variable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 7 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 10.5.55. apbh dma channel 7 command register description the apbh dma channel 7 command register specifies the cycle to perform for the current command chain item. hw_apbh_ch7_cmd 0x80004360 table 322. hw_apbh_ch7_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 323. hw_apbh_ch7_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 7. table 324. hw_apbh_ch7_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore nandwait4ready nandlock irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 250 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 table 325. hw_apbh_ch7_c md bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the gpmi atanand_3 device hw_gpmi_data register. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the gpmi, starti ng with the base pio address of the gpmi (hw_gpmi_ctrl0) and incrementing from there. zero means transfer no command words. 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbh device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5 nandwait4ready ro 0x0 a value of one indicates that the ata/nand dma channel will will wait until the ata/nand device reports 'ready' before execute the command. it is ignored for non-ata/nand dma channels. 4 nandlock ro 0x0 a value of one indicates that the ata/nand dma channel will remain "locked" in the arbiter at the expense of other ata/nand dma channels. it is ignored for non-ata/nand dma channels. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 251 description: the command register controls the overall operation of each dma command for this channel. it includes the number of by tes to transfer to or from the device, the number of apb pio command words included with this command structure, whether to interrupt at command completion, whether to chain an additional com- mand to the end of this one and whether th is transfer is a read or write dma trans- fer. example: empty example. 10.5.56. apbh dma channel 7 buffer address register description the apbh dma channel 7 buffer address re gister contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address, which means transfers can start on any byte boundary. hw_apbh_ch7_bar 0x80004370 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbh_ch7_cmdar to find the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the gpmi (apb pio read) to the system memory (ahb master write). 10- read transfer 11- sense no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. dma_sense = 0x3 perform any requested pio word transfers and then perform a conditional branch to the next chained device. follow the nexcmd_addr pointer if the per pheral sense is true. follow the buffer_address as a chain pointer if the peripheral sense line is false. table 326. hw_apbh_ch7_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 325. hw_apbh_ch7_c md bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 252 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 10.5.57. apbh dma channel 7 semaphore register description the apbh dma channel 7 sema phore register is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbh_ch7_sema 0x80004380 description: table 327. hw_apbh_ch7_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 328. hw_apbh_ch7_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema table 329. hw_apbh_ch7_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 253 each dma channel has an 8-bit counting semaphore that is used to synchronize between the program stream and and the dma chain processing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is stalled until software increments the semaphore count. example: empty example. 10.5.58. ahb-to-apbh dma channel 7 debug register 1 description this register gives debug visibility into the apbh dm a channel 7 state machine and controls. hw_apbh_ch7_debug1 0x80004390 table 330. hw_apbh_ch7_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end sense ready lock nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine table 331. hw_apbh_ch7_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27 sense ro 0x0 this bit reflects the current state of the gpmi sense signal sent from the apb gpmi device. 26 ready ro 0x0 this bit reflects the current state of the gpmi ready signal sent from the apb gpmi device. 25 lock ro 0x0 this bit reflects the current state of the dma channel lock for a gpmi channel. 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit which indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 254 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug vi sibility of the apbh dma channel 7. example: empty example. 10.5.59. ahb-to-apbh dma channel 7 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 7. hw_apbh_ch7_debug2 0x800043a0 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 7 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 331. hw_apbh_ch7_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 10: ahb-to-apbh bridge with dma 255 description: this register allows debug vi sibility of the apbh dma channel 7. example: empty example. apbh xml revision: 1.58 table 332. hw_apbh_ch7_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 333. hw_apbh_ch7_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. free datasheet http:/// STMP36XX official product documentation 5/3/06 256 chapter 10: ahb-to-apbh bridge with dma 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 257 11. ahb-to-apbx bridge with dma this chapter describes the ahb-to-apbx br idge on the STMP36XX, along with its central dma function and implementation examples. programmable registers are described in section 11.5 . 11.1. overview the ahb-to-apbx bridge provides the st mp36xx with an inex pensive peripheral attachment bus running on the ahb?s xc lk. (the ?x? in apbx denotes that the apb x runs on a crystal-derived clock, as compared to apb h , which is synchronous to hclk.) as shown in figure 37 , the ahb-to-apbx bridge in cludes the ahb-to-apb pio bridge for memory-mapped i/o to the apb devices, as well a central dma facility for devices on this bus and a vectored interrupt controller for the arm926 core. each one of the apb peripherals are documented in their own chapters elsewhere in this document. ahb-to-apbx dma ahb slave apbx master ahb master ahb apbx uart rx, irda rx uart tx, irda tx digital radio interface ahb-to-apbx bridge spdif transmit audioin audioout i 2 c lcd interface figure 37. ahb-to-apbx bridge dma block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 258 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 the dma controller uses the apbx bus to transfer read and write data to and from each peripheral. there is no separate dma bus for these devices. contention between the dma?s use of the apbx bus and ahb-to-apb bridge functions? use of the apbx is mediated by internal arbitration logic. for contention between these two units, the dma is favored and the ahb slave will report not ready via its hready output until the bridge transfer completes. the arbiter tracks repeated lockouts and inverts the priority, so that the cpu is gu aranteed every fourth transfer on the apb. 11.2. apbx dma the dma supports eight channels of dma services as shown in table 334 . the shared dma resource allows each independent channel to follow a simple chained command list. command chains are built up using the dma command structure, as shown in figure 38 . a single command structure or channel command word specifies a number of oper- ations to be performed by the dma in support of a given device. thus, the cpu can set up large units of work, chaining together many dma channel command words, pass them off to the dma and have no further concern for the device until the dma completion interrup t occurs. the STMP36XX is desi gned to have enough intelli- gence in the dma and the devices to keep the interrupt frequency from any device below 1 khz (arrival intervals longer than one ms). thus, a single command structure can issue 32-bit pio write oper ations to key reg- isters in the associated device using the sa me apb bus and controls it uses to write dma data bytes to the device. for example, this allows a chain of operations to be issued to the lcd interface to send command bytes, address bytes, an d data transfers to the lcd, where the command and address structure is completely under software control, but the administration of that transfer is handled autonomously by the dma. each dma structure can have from 0 to 15 pio words appended to it. the #pio- words field, if non-zero, instructs the dma engine to copy these words to the apb beginning at paddr = 0x0000 and increm enting its paddr for each cycle. (note that for apbx dma channel 6, which is t he uart/irda rx channel, the first pio word in the dma command is ctrl1. however, for apbx dma channel 7, which is the uart/irda tx, the first pio word in a dma command is ctrl1.) table 334. apbx dma channel assignments apbx dma channel # usage 0 audio adcs 1 audio dacs 2 spdif tx 3 i 2 c 4 lcd interface 5 digital radio interface 6 uart rx, irda rx 7 uart tx, irda tx free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 259 during these operations, the dma drives ps el corresponding to the device associ- ated to the dma channel. the psel-to-dma channel association is defined at syn- thesis time in the STMP36XX. subsequent generations might choose to implement selectable associations for limited cases. the dma master only generat es normal write transfers to the apbx. it does not generate set, clear, or toggle sct transfers. once any requested pio words have been transferred to the peripheral, the dma examines the two-bit command field in the channel command structure. table 335 shows the four commands implemented by the dma. dma_write operations copy data byte s to system memory (on-chip ram or sdram) from the associated peripheral. each peripheral has a target paddr value that it expects to receive dma bytes. this association is synthesized in the dma. the dma uses the xml-derived rtl address in clude files to make this association, so that the dma will synthesize to the th en current address pa rametrics extracted from the xml data base. the dma_write transfer uses the buffer_adddress word in the command st ructure to point to the beginning byte to write data from the peripheral. dma_read operations copy data bytes to the apb peripheral from system mem- ory. the dma engine contains a shared by te aligner that aligns bytes from system table 335. apbx dma commands dma command usage 00 no_dma_xfer. perform any requested pio word transfers, but terminate command before any dma transfer. 01 dma_write. perform any requested pio word tran sfers, and then perform a dma transfer from the peripheral for the spec ified number of bytes. 10 dma_read. perform any requested pio word transf ers, and then perform a dma transfer to the peripheral for the spec ified number of bytes. 11 reserved nextcmdaddr irqoncmplt xfer_count command cmdwords buffer address pioword value word 0 word 1 word 2 word 3-n chain semaphore wait4endcmd figure 38. ahb-to-apbx bridge dma channel command structure free datasheet http:/// STMP36XX official product documentation 5/3/06 260 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 memory to or from the peripherals. peripherals always assume little-endian-aligned data arrives or departs on their 32-bit apb. the dma_read transfer uses the buffer_address word in the command st ructure to point to the dma data buffer to be read by the dma_read command. the no_dma_xfer command is used to writ e pio words to a device without per- forming any dma data byte transfers. as each dma command completes, it triggers the dma to load the next dma com- mand structure in the chain. the normal flow list of dma commands is found by fol- lowing the nextcmd_addr pointer in the dma command structure. if the wait-for- end-command bit (wait4endcmd) is set in a command structure, then the dma channel will wait for the devi ce to signal completion of a command by toggling the apx_endcmcd signal before proceeding to load and execute the next command structure. the semaphore is decremented after the end command is seen. a detailed bit-field view of the dma command structure is shown in table 336 , which shows a field that specifies the number of bytes to be transferred by this dma com- mand. the transfer count mechanism is duplicated in the associated peripheral, either as an implied or specified count in the peripheral. figure 39 shows the chain bit in bit 2 of the second word of the command struc- ture. this bit is set to one if the next_command_address contains a pointer to another dma command structure. if a null pointer (zero) is loaded into the next_command_address, it will not be detected by the dma hardware. only the chain bit indicates whether a valid list exists beyond the current structure. if the irq_finish bit is set in the command structure, then the last act of the dma before loading the next command is to set the interrupt status bit corresponding to the current channel. the st icky interrupt request bit in the dma csr remains set until cleared by software. it can be used to interrupt the cpu. each channel has an eight-bit counting semaphore that controls whether it is in the run or idle state. when the semaphore is non-zero, the channel is ready to run and process commands and dma transfers. whenever a command finishes its dma transfer, it checks the decrement_sema phore bit. if set, it decrements the table 336. dma channel command word in system memory 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 next_command_address number dma bytes to transfer number pio words to write reserved wait4endcmd decrement semaphore irq_finish chain command dma buffer or alternate ccw zero or more pio words to write to the associated peripheral starting at its base address on the apbx bus free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 261 counting semaphore. if the semaphore goes to zero as a result, then the channel enters the idle state and remains there unt il the semaphore is incremented by soft- ware. when the semaphore goes to non-zero and the channel is in its idle state, then it uses the value in the hw_ apbx_chn_nxtcmdar (next command address register) to fetch a pointer to the next command to process. note: this is a double indirect case. this method allows software to append to a running command list under the protection of the counting semaphore. to start processing the first time, soft ware creates the command list to be pro- cessed. it writes the address of the first command into the hw_apbx_chn_nxtcmdar register, and t hen writes a one to the counting semaphore in hw_apbx_chn_sem a. the dma channel loads hw_apbx_chn_curcmdar register and then enters the normal state machine processing for the next command. when software writes a value to the counting semaphore, it is added to the semaphor e count by hardware, protecting the case where both hardware and software are trying to change the semaphore on the same clock edge. software can examine the value of hw_apbxn_curcmdar at any time to deter- mine the location of the command struct ure that is currently being processed. 11.3. dma chain example the example in figure 39 shows how to bring the basic items together to make a simple dma chain to read pcm samples and send them out the audio output (dac) using one dma channel. this example shows three command structures linked together using their normal command list pointers. the first command writes a single pio word to the hw_audioout_ctrl0 register with a new word count for the dac. this first command also per forms a 512 byte dma_read operation to read the data block bytes into the dac. a second and a third dma command struc- ture also performs a dma_read operation to handle circular buffer style outputs. the completion of each command structure generates an interrupt request. in addi- tion, each command structure decrements the semaphore. if the decompression software has not provided a buff er in a timely fashion, then the dma will stall. with- out the decrement semaphore interlocking, then the dma will continue to output a stream of samples. in this mode, it is up to software to use the interrupts to synchro- nize outputs so that underruns do not occur. free datasheet http:/// STMP36XX official product documentation 5/3/06 262 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 note that each word of the three-word dma command structure corresponds to a pio register of the dma th at is accessible on the apbx bus. normally, the dma copies the next command stru cture onto these registers for processing at the start of each command by following the value of the pointer previously loaded into the nextcmd_addr register. in order to star t dma processing, for the first command, one must initialize the pio registers of th e desired channel. first load the next com- mand address register with a pointer to the first command to be loaded. then write a one to the counting semaphore register. th is causes the dma to schedule the tar- geted channel for dma command structure lo ad, as if it just finished its previous command. 11.4. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. hw_audioout_ctrl0 hw_audioout_ctrl0 nextcmd_addr buffer address hw_audioout_ctrl0 nextcmd_addr buffer address nextcmd_addr buffer address 512-byte data block (64 pcm stereo samples) (1.33 ms @ 48 khz) 1 pio, irq, decsema chaining, dma read 1 pio, irq, decsema, chaining, dma read 1 pio,irq, decsema, chaining, dma read pointer to next ccw pointer to dma buffer 512-byte data block (64 pcm stereo samples) (1.33 ms @ 48 khz) 512-byte data block (64 pcm stereo samples) (1.33 ms @ 48 khz) 512=0x200 0x104e 512=0x200 0x104e 512=0x200 0x104e figure 39. ahb-to-apbx bridge dma audioout (dac) exam ple command chain free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 263 11.5. programmable registers this section describes the programmabl e registers of the ahb-to-apbx bridge block. 11.5.1. ahb-to-apbx bridge control and status register 0 description the ahb-to-apbx bridge control and status register 0 provides overall control of the ahb-to-apbx bridge and dma. hw_apbx_ctrl0 0x80024000 hw_apbx_ctrl0_set 0x80024004 hw_apbx_ctrl0_clr 0x80024008 hw_apbx_ctrl0_tog 0x8002400c table 337. hw_apbx_ctrl0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsvd2 reset_channel rsvd1 freeze_channel table 338. hw_apbx_ctrl0 bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 set this bit to zero to enable normal apbx dma operation. set this bit to one (default) to disable clocking with the apbx dma and hold it in its reset (lowest power) state. this bit can be turned on and then off to reset the apbx dma block to its default state. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. 29:24 rsvd2 ro 0x000000 reserved , always set to zero. 23:16 reset_channel rw 0x0 setting a bit in this field causes the dma controller to take the corresponding channel through its reset state. the bit is reset after the channel resources are cleared. reference the hw_apbx_devsel register to select between the uart and irda devices. audioin = 0x01 audioout = 0x02 spdif_tx = 0x04 i2c = 0x08 lcdif = 0x10 dri = 0x20 uart_rx = 0x30 irda_rx = 0x30 uart_tx = 0x40 irda_tx = 0x40 free datasheet http:/// STMP36XX official product documentation 5/3/06 264 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 11.5.2. ahb-to-apbx bridge control and status register 1 description the ahb-to-apbx bridge control and status register 1 provides overall control of the interrupts generated by the ahb-to-apbx dma. hw_apbx_ctrl1 0x80024010 hw_apbx_ctrl1_set 0x80024014 hw_apbx_ctrl1_clr 0x80024018 hw_apbx_ctrl1_tog 0x8002401c 15:8 rsvd1 ro 0x000000 reserved , always set to zero. 7:0 freeze_channel rw 0x0 setting a bit in this field will freeze the dma channel associated with it. this field is a direct input to the dma channel arbiter. when frozen, the channel is denied access to the central dma resources. audioin = 0x01 audioout = 0x02 spdif_tx = 0x04 i2c = 0x08 lcdif = 0x10 dri = 0x20 uart_rx = 0x30 irda_rx = 0x30 uart_tx = 0x40 irda_tx = 0x40 table 339. hw_apbx_ctrl1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 ch7_cmdcmplt_irq_en ch6_cmdcmplt_irq_en ch5_cmdcmplt_irq_en ch4_cmdcmplt_irq_en ch3_cmdcmplt_irq_en ch2_cmdcmplt_irq_en ch1_cmdcmplt_irq_en ch0_cmdcmplt_irq_en rsvd1 ch7_cmdcmplt_irq ch6_cmdcmplt_irq ch5_cmdcmplt_irq ch4_cmdcmplt_irq ch3_cmdcmplt_irq ch2_cmdcmplt_irq ch1_cmdcmplt_irq ch0_cmdcmplt_irq table 340. hw_apbx_ctrl1 bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x000000 reserved , always set to zero. 23 ch7_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbx dma channel 7. table 338. hw_apbx_ctrl0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 265 22 ch6_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbx dma channel 6. 21 ch5_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbx dma channel 5. 20 ch4_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbx dma channel 4. 19 ch3_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbx dma channel 3. 18 ch2_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbx dma channel 2. 17 ch1_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbx dma channel 1. 16 ch0_cmdcmplt_irq_en rw 0x0 setting this bit enables the generation of an interrupt request for apbx dma channel 0. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7 ch7_cmdcmplt_irq rw 0x0 interrupt request stat us bit for apbx dma channel 7. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 6 ch6_cmdcmplt_irq rw 0x0 interrupt request stat us bit for apbx dma channel 6. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 5 ch5_cmdcmplt_irq rw 0x0 interrupt request stat us bit for apbx dma channel 5. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 4 ch4_cmdcmplt_irq rw 0x0 interrupt request stat us bit for apbx dma channel 4. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 3 ch3_cmdcmplt_irq rw 0x0 interrupt request stat us bit for apbx dma channel 3. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 2 ch2_cmdcmplt_irq rw 0x0 interrupt request stat us bit for apbx dma channel 2. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. table 340. hw_apbx_ctrl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 266 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: this register contains the per-channel interrupt status bits and the per-channel interrupt enable bits. each channel has a dedicated interrupt vector in the vectored interrupt controller. example: bf_wr(apbx_ctrl1, ch5_cmdcmplt_irq, 0); // use bitfield write macro bf_apbx_ctrl1.ch5_cmdcmplt_irq = 0; // or, assign to register struct's bitfield 11.5.3. ahb-to-apbx dma device assignment register description this register allows reassignment of the apbx device connected to the dma chan- nels. hw_apbx_devsel 0x80024020 1 ch1_cmdcmplt_irq rw 0x0 interrupt request stat us bit for apbx dma channel 1. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. 0 ch0_cmdcmplt_irq rw 0x0 interrupt request stat us bit for apbx dma channel 0. this sticky bit is set by dma hardware and reset by software. it is anded with its corresponding enable bit to generate an interrupt. table 341. hw_apbx_devsel 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 table 342. hw_apbx_devsel bit field descriptions bits label rw reset definition 31:28 ch7 rw 0x0 these bits allow reassignment of the dma channel 7 from the default of the uart transmit device to the irda transmit device. use_uart = 0x0 use the default assignment of uart transmit dma channel for dma channel 7. use_irda = 0x1 replace the uart transmit channel with the irda transmit channel for dma channel 7. 27:24 ch6 rw 0x0 these bits allow reassignment of the dma channel 6 from the default of the ua rt receive device to the irda receive device. use_uart = 0x0 use the default assignment of uart receive dma channel for dma channel 6. use_irda = 0x1 replace the uart receive channel with the uart receive channel for dma channel 6. 23:20 ch5 ro 0x0 reserved. 19:16 ch4 ro 0x0 reserved. 15:12 ch3 ro 0x0 reserved. table 340. hw_apbx_ctrl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 267 description: this register provides a mechanism for assigning dma channels 6 and 7 to either the uart or irda devices. example: empty example. 11.5.4. apbx dma channel 0 current command address register description the apbx dma channel 0 curren t command address register points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbx_ch0_curcmdar 0x80024030 description: apbx dma channel 0 is controlled by a variable-sized command structure. this register points to the command structure currently being executed. example: pcurcmd = (hw_apbh_chn_cmd_t *) hw_apbx_chn_curcmdar_rd(0); // read the whole register, since there is only one field pcurcmd = (hw_apbh_chn_cmd_t *) bf_rdn(apbx_chn_curcmdar, 0, cmd_addr); // or, use multi- register bitfield read macro pcurcmd = (hw_apbh_chn_cmd_t *) hw_apbx_chn_curcmdar(0).cmd_addr; // or, assign from bit- field of indexed register's struct 11.5.5. apbx dma channel 0 next command address register description the apbx dma channel 0 next command addre ss register points to the next mul- tiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbx_ch0_nxtcmdar 0x80024040 11:8 ch2 ro 0x0 reserved. 7:4 ch1 ro 0x0 reserved. 3:0 ch0 ro 0x0 reserved. table 343. hw_apbx_ch0_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 344. hw_apbx_ch0_cur cmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 0. table 342. hw_apbx_devsel bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 268 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: apbx dma channel 0 is controlled by a va riable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 0 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: hw_apbx_chn_nxtcmdar_wr(0, (reg32_t) pcommandtwostructure); // write the entire register, since there is only one field bf_wrn(apbx_chn_nxtcmdar, 0, (reg32_t) pcommandtwostructure); // or, use multi-register bitfield write macro hw_apbx_chn_nxtcmdar(0).cmd_addr = (reg32_t) pcommandtwostructure; // or, assign to bit- field of indexed register's struct 11.5.6. apbx dma channel 0 command register description the apbx dma channel 0 command register specifies the dma transaction to perform for the current command chain item. hw_apbx_ch0_cmd 0x80024050 table 345. hw_apbx_ch0_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 346. hw_apbx_ch0_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 0. table 347. hw_apbx_ch0_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore rsvd0 irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 269 description: the apbx dma channel 0 command regist er controls the overall operation of each dma command for this channel. it in cludes the number of bytes to transfer to or from the device, the number of apb pi o command words includ ed with this com- mand structure, whether to interrupt at command completion, whether to chain an table 348. hw_apbx_ch0_cmd bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate pio register in the adc device hw_audioin_data. a value of 0 indicates a 64- kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the adc, starting with the base pio address of the adc (hw_audioin_ct rl) and incrementing from there. zero means transfer no command words 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the abpx device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5:4 rsvd0 ro 0x0 reserved, always set to zero. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbx_ch0_cmdar to fi nd the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbx device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- reserved no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. free datasheet http:/// STMP36XX official product documentation 5/3/06 270 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 additional command to the end of this on e and whether this tr ansfer is a read or write dma transfer. example: hw_apbh_chn_cmd_t dma_cmd; dma_cmd.xfer_count = 512; // transfer 512 bytes dma_cmd.command = bv_apbx_chn_cmd_command__dma_write; // transfer to system memory from peripheral device dma_cmd.chain = 1; // chain an additional command structure on to the list dma_cmd.irqoncmplt = 1; // generate an interrupt on completion of this command structure 11.5.7. apbx dma channel 0 buffer address register description the apbx dma channel 0 buffer address register contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address which means transfe rs can start on any byte boundary. hw_apbx_ch0_bar 0x80024060 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: hw_apbh_chn_bar_t dma_data; dma_data.address = (reg32_t) pdatabuffer; 11.5.8. apbx dma channel 0 semaphore register description the apbx dma channel 0 semaphore regist er is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbx_ch0_sema 0x80024070 table 349. hw_apbx_ch0_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 350. hw_apbx_ch0_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 271 description: each dma channel has an 8-bit counti ng semaphore used to synchronize between the program stream and the dma chain proc essing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is st alled until software incre- ments the semaphore count. example: bf_wr(apbx_chn_sema, 0, increment_sema, 2); // increment semaphore by two current_sema = bf_rd(apbx_chn_sema, 0, phore); // get instantaneous value 11.5.9. ahb-to-apbx dma channel 0 debug register 1 description this register gives debug visibility in to the apbx dma channel 0 state machine and controls. hw_apbx_ch0_debug1 0x80024080 table 351. hw_apbx_ch0_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema table 352. hw_apbx_ch0_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. free datasheet http:/// STMP36XX official product documentation 5/3/06 272 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 table 353. hw_apbx_ch0_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine table 354. hw_apbx_ch0_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit that indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 273 description: this register allows debug visibility of the apbx dma channel 0. example: empty example. 11.5.10. ahb-to-apbx dma channel 0 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 0. hw_apbx_ch0_debug2 0x80024090 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 0 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 354. hw_apbx_ch0_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 274 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug visibility of the apbx dma channel 0. example: empty example. 11.5.11. apbx dma channel 1 current command address register description the apbx dma channel 1 curren t command address register points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbx_ch1_curcmdar 0x800240a0 description: apbx dma channel 1 is controlled by a variable-sized command structure. this register points to the command structure currently being executed. example: pcurcmd = (hw_apbh_chn_cmd_t *) hw_apbx_chn_curcmdar_rd(1); // read the whole register, since there is only one field table 355. hw_apbx_ch0_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 356. hw_apbx_ch0_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 357. hw_apbx_ch1_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 358. hw_apbx_ch1_cur cmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 1. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 275 pcurcmd = (hw_apbh_chn_cmd_t *) bf_rdn(apbx_chn_curcmdar, 1, cmd_addr); // or, use multi- register bitfield read macro pcurcmd = (hw_apbh_chn_cmd_t *) hw_apbx_chn_curcmdar(1).cmd_addr; // or, assign from bit- field of indexed register's struct 11.5.12. apbx dma channel 1 next command address register description the apbx dma channel 1 next command addre ss register points to the next mul- tiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbx_ch1_nxtcmdar 0x800240b0 description: apbx dma channel 1 is controlled by a va riable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 1 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: hw_apbx_chn_nxtcmdar_wr(1, (reg32_t) pcommandtwostructure); // write the entire register, since there is only one field bf_wrn(apbx_chn_nxtcmdar, 1, (reg32_t) pcommandtwostructure); // or, use multi-register bitfield write macro hw_apbx_chn_nxtcmdar(1).cmd_addr = (reg32_t) pcommandtwostructure; // or, assign to bit- field of indexed register's struct 11.5.13. apbx dma channel 1 command register description the apbx dma channel 1 comman d register specifies the cycle to perform for the current command chain item. hw_apbx_ch1_cmd 0x800240c0 table 359. hw_apbx_ch1_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 360. hw_apbx_ch1_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 1. table 361. hw_apbx_ch1_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore rsvd0 irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 276 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: the apbx dma channel 1 command regist er controls the overall operation of each dma command for this channel. it in cludes the number of bytes to transfer to or from the device, the number of apb pi o command words includ ed with this com- mand structure, whether to interrupt at command completion, whether to chain an table 362. hw_apbx_ch1_cmd bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate pio register in the dac device hw_audioout_data. a value of 0 indicates a 64- kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the dac, starting with the base pio address of the dac (hw_audioout_c trl) and incrementing from there. zero means transfer no command words 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbx device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5:4 rsvd0 ro 0x0 reserved, always set to zero. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbx_ch1_cmdar to fi nd the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbx device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- reserved no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 277 additional command to the end of this on e and whether this tr ansfer is a read or write dma transfer. example: empty example. 11.5.14. apbx dma channel 1 buffer address register description the apbx dma channel 1 buffer address register contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address which means transfe rs can start on any byte boundary. hw_apbx_ch1_bar 0x800240d0 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: hw_apbh_chn_bar_t dma_data; dma_data.address = (reg32_t) pdatabuffer; 11.5.15. apbx dma channel 1 semaphore register description the apbx dma channel 1 semaphore regist er is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbx_ch1_sema 0x800240e0 table 363. hw_apbx_ch1_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 364. hw_apbx_ch1_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 365. hw_apbx_ch1_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema free datasheet http:/// STMP36XX official product documentation 5/3/06 278 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: each dma channel has an 8-bit counti ng semaphore used to synchronize between the program stream and the dma chain proc essing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is st alled until software incre- ments the semaphore count. example: bf_wr(apbx_chn_sema, 1, increment_sema, 2); // increment semaphore by two current_sema = bf_rd(apbx_chn_sema, 1, phore); // get instantaneous value 11.5.16. ahb-to-apbx dma channel 1 debug register 1 description this register gives debug visibility in to the apbx dma channel 1 state machine and controls. hw_apbx_ch1_debug1 0x800240f0 table 366. hw_apbx_ch1_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. table 367. hw_apbx_ch1_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 279 table 368. hw_apbx_ch1_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit that indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 280 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug visibility of the apbx dma channel 1. example: empty example. 11.5.17. ahb-to-apbx dma channel 1 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 1. hw_apbx_ch1_debug2 0x80024100 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 1 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 368. hw_apbx_ch1_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 281 description: this register allows debug visibility of the apbx dma channel 1. example: empty example. 11.5.18. apbx dma channel 2 current command address register description the apbx dma channel 2 curren t command address register points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbx_ch2_curcmdar 0x80024110 description: apbx dma channel 2 is controlled by a variable-sized command structure. this register points to the command structure currently being executed. example: empty example. table 369. hw_apbx_ch1_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 370. hw_apbx_ch1_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 371. hw_apbx_ch2_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 372. hw_apbx_ch2_cur cmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 2. free datasheet http:/// STMP36XX official product documentation 5/3/06 282 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 11.5.19. apbx dma channel 2 next command address register description the apbx dma channel 2 next command addre ss register points to the next mul- tiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbx_ch2_nxtcmdar 0x80024120 description: apbx dma channel 2 is controlled by a va riable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 2 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 11.5.20. apbx dma channel 2 command register description the apbx dma channel 2 comman d register specifies the cycle to perform for the current command chain item. hw_apbx_ch2_cmd 0x80024130 table 373. hw_apbx_ch2_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 374. hw_apbx_ch2_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 2. table 375. hw_apbx_ch2_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore rsvd0 irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 283 description: the apbx dma channel 2 command regist er controls the overall operation of each dma command for this channel. it in cludes the number of bytes to transfer to or from the device, the number of apb pi o command words includ ed with this com- mand structure, whether to interrupt at command completion, whether to chain an table 376. hw_apbx_ch2_cmd bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the spdif device hw_spdif_data register. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the spdif, starting with the base pio address of the spdif (hw_spdif_ctrl) and incrementing from there. zero means transfer no command words 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbx device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5:4 rsvd0 ro 0x0 reserved, always set to zero. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbx_ch2_cmdar to fi nd the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbx device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- reserved no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. free datasheet http:/// STMP36XX official product documentation 5/3/06 284 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 additional command to the end of this on e and whether this tr ansfer is a read or write dma transfer. example: empty example. 11.5.21. apbx dma channel 2 buffer address register description the apbx dma channel 2 buffer address register contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address which means transfe rs can start on any byte boundary. hw_apbx_ch2_bar 0x80024140 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 11.5.22. apbx dma channel 2 semaphore register description the apbx dma channel 2 semaphore regist er is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbx_ch2_sema 0x80024150 table 377. hw_apbx_ch2_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 378. hw_apbx_ch2_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 379. hw_apbx_ch2_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 285 description: each dma channel has an 8-bit counti ng semaphore used to synchronize between the program stream and the dma chain proc essing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is st alled until software incre- ments the semaphore count. example: empty example. 11.5.23. ahb-to-apbx dma channel 2 debug register 1 description this register gives debug visibility in to the apbx dma channel 2 state machine and controls. hw_apbx_ch2_debug1 0x80024160 table 380. hw_apbx_ch2_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. table 381. hw_apbx_ch2_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine free datasheet http:/// STMP36XX official product documentation 5/3/06 286 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 table 382. hw_apbx_ch2_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit that indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 287 description: this register allows debug visibility of the apbx dma channel 2. example: empty example. 11.5.24. ahb-to-apbx dma channel 2 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 2. hw_apbx_ch2_debug2 0x80024170 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 2 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 382. hw_apbx_ch2_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 288 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug visibility of the apbx dma channel 2. example: empty example. 11.5.25. apbx dma channel 3 current command address register description the apbx dma channel 3 curren t command address register points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbx_ch3_curcmdar 0x80024180 description: apbx dma channel 3 is controlled by a variable-sized command structure. this register points to the command structure currently being executed. example: empty example. table 383. hw_apbx_ch2_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 384. hw_apbx_ch2_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 385. hw_apbx_ch3_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 386. hw_apbx_ch3_cur cmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 3. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 289 11.5.26. apbx dma channel 3 next command address register description the apbx dma channel 3 next command addre ss register points to the next mul- tiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbx_ch3_nxtcmdar 0x80024190 description: apbx dma channel 3 is controlled by a va riable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 3 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 11.5.27. apbx dma channel 3 command register description the apbx dma channel 3 comman d register specifies the cycle to perform for the current command chain item. hw_apbx_ch3_cmd 0x800241a0 table 387. hw_apbx_ch3_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 388. hw_apbx_ch3_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 3. table 389. hw_apbx_ch3_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore rsvd0 irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 290 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: the apbx dma channel 3 command regist er controls the overall operation of each dma command for this channel. it in cludes the number of bytes to transfer to or from the device, the number of apb pi o command words includ ed with this com- mand structure, whether to interrupt at command completion, whether to chain an table 390. hw_apbx_ch3_cmd bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate pio register in the i2c device hw_i2c_data. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the i2c, starting with the base pio address of the i2c (hw_i2c_ctrl0) and incrementing from there. zero means transfer no command words 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbx device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5:4 rsvd0 ro 0x0 reserved, always set to zero. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbx_ch3_cmdar to fi nd the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbx device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- reserved no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 291 additional command to the end of this on e and whether this tr ansfer is a read or write dma transfer. example: empty example. 11.5.28. apbx dma channel 3 buffer address register description the apbx dma channel 3 buffe r address register contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address which means transfe rs can start on any byte boundary. hw_apbx_ch3_bar 0x800241b0 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 11.5.29. apbx dma channel 3 semaphore register description the apbx dma channel 3 semaphore regist er is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbx_ch3_sema 0x800241c0 table 391. hw_apbx_ch3_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 392. hw_apbx_ch3_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 393. hw_apbx_ch3_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema free datasheet http:/// STMP36XX official product documentation 5/3/06 292 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: each dma channel has an 8-bit counti ng semaphore used to synchronize between the program stream and the dma chain proc essing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is st alled until software incre- ments the semaphore count. example: empty example. 11.5.30. ahb-to-apbx dma channel 3 debug register 1 description this register gives debug visibility in to the apbx dma channel 3 state machine and controls. hw_apbx_ch3_debug1 0x800241d0 table 394. hw_apbx_ch3_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. table 395. hw_apbx_ch3_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 293 table 396. hw_apbx_ch3_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit that indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 294 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug visibility of the apbx dma channel 3. example: empty example. 11.5.31. ahb-to-apbx dma channel 3 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 3. hw_apbx_ch3_debug2 0x800241e0 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 3 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 396. hw_apbx_ch3_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 295 description: this register allows debug visibility of the apbx dma channel 3. example: empty example. 11.5.32. apbx dma channel 4 current command address register description the apbx dma channel 4 curren t command address register points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbx_ch4_curcmdar 0x800241f0 description: apbx dma channel 4 is controlled by a variable-sized command structure. this register points to the command structure currently being executed. example: empty example. table 397. hw_apbx_ch3_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 398. hw_apbx_ch3_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 399. hw_apbx_ch4_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 400. hw_apbx_ch4_cur cmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 4. free datasheet http:/// STMP36XX official product documentation 5/3/06 296 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 11.5.33. apbx dma channel 4 next command address register description the apbx dma channel 4 next command addre ss register points to the next mul- tiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbx_ch4_nxtcmdar 0x80024200 description: apbx dma channel 4 is controlled by a va riable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 4 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 11.5.34. apbx dma channel 4 command register description the apbx dma channel 4 comman d register specifies the cycle to perform for the current command chain item. hw_apbx_ch4_cmd 0x80024210 table 401. hw_apbx_ch4_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 402. hw_apbx_ch4_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 4. table 403. hw_apbx_ch4_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore rsvd0 irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 297 description: the apbx dma channel 4 command regist er controls the overall operation of each dma command for this channel. it in cludes the number of bytes to transfer to or from the device, the number of apb pi o command words includ ed with this com- mand structure, whether to interrupt at command completion, whether to chain an table 404. hw_apbx_ch4_cmd bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the lcdif device hw_lcdif_data. a value of 0 indicates a 64- kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the lcdif, starting with the base pio address of the lcdif (hw_lcdif_ctrl) and incrementing from there. zero means transfer no command words 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbx device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5:4 rsvd0 ro 0x0 reserved, always set to zero. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbx_ch4_cmdar to fi nd the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbx device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- reserved no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. free datasheet http:/// STMP36XX official product documentation 5/3/06 298 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 additional command to the end of this on e and whether this tr ansfer is a read or write dma transfer. example: empty example. 11.5.35. apbx dma channel 4 buffer address register description the apbx dma channel 4 buffer address register contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address which means transfe rs can start on any byte boundary. hw_apbx_ch4_bar 0x80024220 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device associate with this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 11.5.36. apbx dma channel 4 semaphore register description the apbx dma channel 4 semaphore regist er is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbx_ch4_sema 0x80024230 table 405. hw_apbx_ch4_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 406. hw_apbx_ch4_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 407. hw_apbx_ch4_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 299 description: each dma channel has an 8-bit counti ng semaphore used to synchronize between the program stream and the dma chain proc essing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is st alled until software incre- ments the semaphore count. example: empty example. 11.5.37. ahb-to-apbx dma channel 4 debug register 1 description this register gives debug visibility in to the apbx dma channel 4 state machine and controls. hw_apbx_ch4_debug1 0x80024240 table 408. hw_apbx_ch4_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. table 409. hw_apbx_ch4_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine free datasheet http:/// STMP36XX official product documentation 5/3/06 300 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 table 410. hw_apbx_ch4_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit that indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 301 description: this register allows debug visibility of the apbx dma channel 4. example: empty example. 11.5.38. ahb-to-apbx dma channel 4 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 4. hw_apbx_ch4_debug2 0x80024250 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 4 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 410. hw_apbx_ch4_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 302 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug visibility of the apbx dma channel 4. example: empty example. 11.5.39. apbx dma channel 5 current command address register description the apbx dma channel 5 curren t command address register points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbx_ch5_curcmdar 0x80024260 description: apbx dma channel 5 is controlled by a variable-sized command structure. this register points to the command structure currently being executed. example: empty example. table 411. hw_apbx_ch4_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 412. hw_apbx_ch4_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 413. hw_apbx_ch5_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 414. hw_apbx_ch5_cur cmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 5. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 303 11.5.40. apbx dma channel 5 next command address register description the apbx dma channel 5 next command addre ss register points to the next mul- tiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbx_ch5_nxtcmdar 0x80024270 description: apbx dma channel 5 is controlled by a va riable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 5 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 11.5.41. apbx dma channel 5 command register description the apbx dma channel 5 comman d register specifies the cycle to perform for the current command chain item. hw_apbx_ch5_cmd 0x80024280 table 415. hw_apbx_ch5_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 416. hw_apbx_ch5_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 5. table 417. hw_apbx_ch5_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore rsvd0 irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 304 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: the apbx dma channel 5 command regist er controls the overall operation of each dma command for this channel. it in cludes the number of bytes to transfer to or from the device, the number of apb pi o command words includ ed with this com- mand structure, whether to interrupt at command completion, whether to chain an table 418. hw_apbx_ch5_cmd bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate pio register in the dri device hw_dri_data register. a value of 0 indicates a 64- kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the dri, starting with the base pio address of the dri (hw_dri_ctrl) and incrementing from there. zero means transfer no command words 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbx device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5:4 rsvd0 ro 0x0 reserved, always set to zero. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbx_ch5_cmdar to fi nd the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbx device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- reserved no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 305 additional command to the end of this on e and whether this tr ansfer is a read or write dma transfer. example: empty example. 11.5.42. apbx dma channel 5 buffer address register description the apbx dma channel 5 buffer address register contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address which means transfe rs can start on any byte boundary. hw_apbx_ch5_bar 0x80024290 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 11.5.43. apbx dma channel 5 semaphore register description the apbx dma channel 5 semaphore regist er is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbx_ch5_sema 0x800242a0 table 419. hw_apbx_ch5_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 420. hw_apbx_ch5_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 421. hw_apbx_ch5_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema free datasheet http:/// STMP36XX official product documentation 5/3/06 306 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: each dma channel has an 8-bit counti ng semaphore used to synchronize between the program stream and the dma chain proc essing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is st alled until software incre- ments the semaphore count. example: empty example. 11.5.44. ahb-to-apbx dma channel 5 debug register 1 description this register gives debug visibility in to the apbx dma channel 5 state machine and controls. hw_apbx_ch5_debug1 0x800242b0 table 422. hw_apbx_ch5_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. table 423. hw_apbx_ch5_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 307 table 424. hw_apbx_ch5_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit that indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 308 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug visibility of the apbx dma channel 5. example: empty example. 11.5.45. ahb-to-apbx dma channel 5 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 5. hw_apbx_ch5_debug2 0x800242c0 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 5 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 424. hw_apbx_ch5_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 309 description: this register allows debug visibility of the apbx dma channel 5. example: empty example. 11.5.46. apbx dma channel 6 current command address register description the apbx dma channel 6 curren t command address register points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbx_ch6_curcmdar 0x800242d0 description: apbx dma channel 6 is controlled by a variable-sized command structure. this register points to the command structure currently being executed. example: empty example. table 425. hw_apbx_ch5_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 426. hw_apbx_ch5_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 427. hw_apbx_ch6_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 428. hw_apbx_ch6_cur cmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 6. free datasheet http:/// STMP36XX official product documentation 5/3/06 310 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 11.5.47. apbx dma channel 6 next command address register description the apbx dma channel 6 next command addre ss register points to the next mul- tiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbx_ch6_nxtcmdar 0x800242e0 description: apbx dma channel 6 is controlled by a va riable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 6 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 11.5.48. apbx dma channel 6 command register description the apbx dma channel 6 comman d register specifies the cycle to perform for the current command chain item. hw_apbx_ch6_cmd 0x800242f0 table 429. hw_apbx_ch6_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 430. hw_apbx_ch6_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 6. table 431. hw_apbx_ch6_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore rsvd0 irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 311 description: the apbx dma channel 6 command regist er controls the overall operation of each dma command for this channel. it in cludes the number of bytes to transfer to or from the device, the number of apb pi o command words includ ed with this com- mand structure, whether to interrupt at command completion, whether to chain an table 432. hw_apbx_ch6_cmd bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the uart device hw_uartapp_data register. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the uart, starting with the base pio address of the uart (hw_uartapp_ctrl0) and incrementing from there. zero means transfer no command words 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbx device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5:4 rsvd0 ro 0x0 reserved, always set to zero. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbx_ch6_cmdar to fi nd the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbx device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- reserved no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. free datasheet http:/// STMP36XX official product documentation 5/3/06 312 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 additional command to the end of this on e and whether this tr ansfer is a read or write dma transfer. example: empty example. 11.5.49. apbx dma channel 6 buffer address register description the apbx dma channel 6 buffer address register contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address which means transfe rs can start on any byte boundary. hw_apbx_ch6_bar 0x80024300 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 11.5.50. apbx dma channel 6 semaphore register description the apbx dma channel 6 semaphore regist er is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbx_ch6_sema 0x80024310 table 433. hw_apbx_ch6_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 434. hw_apbx_ch6_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 435. hw_apbx_ch6_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 313 description: each dma channel has an 8-bit counti ng semaphore used to synchronize between the program stream and the dma chain proc essing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is st alled until software incre- ments the semaphore count. example: empty example. 11.5.51. ahb-to-apbx dma channel 6 debug register 1 description this register gives debug visibility in to the apbx dma channel 6 state machine and controls. hw_apbx_ch6_debug1 0x80024320 table 436. hw_apbx_ch6_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. table 437. hw_apbx_ch6_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine free datasheet http:/// STMP36XX official product documentation 5/3/06 314 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 table 438. hw_apbx_ch6_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit that indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 315 description: this register allows debug visibility of the apbx dma channel 6. example: empty example. 11.5.52. ahb-to-apbx dma channel 6 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 6. hw_apbx_ch6_debug2 0x80024330 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 6 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 438. hw_apbx_ch6_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 316 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug visibility of the apbx dma channel 6. example: empty example. 11.5.53. apbx dma channel 7 current command address register description the apbx dma channel 7 curren t command address register points to the multi- word command that is currently being executed. commands are threaded on the command address. hw_apbx_ch7_curcmdar 0x80024340 description: apbx dma channel 7 is controlled by a variable-sized command structure. this register points to the command structure currently being executed. example: empty example. table 439. hw_apbx_ch6_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 440. hw_apbx_ch6_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. table 441. hw_apbx_ch7_curcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 442. hw_apbx_ch7_cur cmdar bit field descriptions bits label rw reset definition 31:0 cmd_addr ro 0x00000000 pointer to comm and structure currently being processed for channel 7. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 317 11.5.54. apbx dma channel 7 next command address register description the apbx dma channel 7 next command addre ss register points to the next mul- tiword command to be executed. commands are threaded on the command address. set chain to one to process command lists. hw_apbx_ch7_nxtcmdar 0x80024350 description: apbx dma channel 7 is controlled by a va riable-sized command structure. soft- ware loads this register with the address of the first command structure to process and increments the channel 7 semaphore to start processing. this register points to the next command structure to be executed when the current command is com- pleted. example: empty example. 11.5.55. apbx dma channel 7 command register description the apbx dma channel 7 comman d register specifies the cycle to perform for the current command chain item. hw_apbx_ch7_cmd 0x80024360 table 443. hw_apbx_ch7_nxtcmdar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_addr table 444. hw_apbx_ch7_nxtcm dar bit field descriptions bits label rw reset definition 31:0 cmd_addr rw 0x00000000 pointer to next command structure for channel 7. table 445. hw_apbx_ch7_cmd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 xfer_count cmdwords rsvd1 wait4endcmd semaphore rsvd0 irqoncmplt chain command free datasheet http:/// STMP36XX official product documentation 5/3/06 318 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: the apbx dma channel 7 command regist er controls the overall operation of each dma command for this channel. it in cludes the number of bytes to transfer to or from the device, the number of apb pi o command words includ ed with this com- mand structure, whether to interrupt at command completion, whether to chain an table 446. hw_apbx_ch7_cmd bit field descriptions bits label rw reset definition 31:16 xfer_count ro 0x0 this field indicates the number of bytes to transfer to or from the appropriate p io register in the uart device hw_uartapp_data register. a value of 0 indicates a 64-kbyte transfer. 15:12 cmdwords ro 0x00 this field indicates the number of command words to send to the uart, starting with the base pio address of the uart (hw_uartapp_ctrl0) and incrementing from there. zero means transfer no command words 11:8 rsvd1 ro 0x0 reserved, always set to zero. 7 wait4endcmd ro 0x0 a value of one indicates that the channel will wait for the end of command signal to be sent from the apbx device to the dma before starting the next dma command. 6 semaphore ro 0x0 a value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. if the semaphore decrements to zero, then this channel stalls until software increments it again. 5:4 rsvd0 ro 0x0 reserved, always set to zero. 3 irqoncmplt ro 0x0 a value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e., after the dma transfer is complete. 2 chain ro 0x0 a value of one indicates that another command is chained onto the end of the current command structure. at the completion of the current command, this channel will follow the pointer in hw_apbx_ch7_cmdar to fi nd the next command. 1:0 command ro 0x00 this bitfield indicates the type of current command: 00- no dma transfer 01- write transfers, i.e., data sent from the apbx device (apb pio read) to the system memory (ahb master write). 10- read transfer 11- reserved no_dma_xfer = 0x0 perform any requested pio word transfers but terminate command before any dma transfer. dma_write = 0x1 perform any requested pio word transfers and then perform a dma transfer from the peripheral for the specified number of bytes. dma_read = 0x2 perform any requested pio word transfers and then perform a dma transfer to the peripheral for the specified number of bytes. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 319 additional command to the end of this on e and whether this tr ansfer is a read or write dma transfer. example: empty example. 11.5.56. apbx dma channel 7 buffer address register description the apbx dma channel 7 buffer address register contains a pointer to the data buffer for the transfer. for immediate forms, the data is taken from this register. this is a byte address which means transfe rs can start on any byte boundary. hw_apbx_ch7_bar 0x80024370 description: this register holds a pointer to the data buffer in system memory. after the com- mand values have been read into the dma controller and the device controlled by this channel, then the dma transfer will begin, to or fr om the buffer pointed to by this register. example: empty example. 11.5.57. apbx dma channel 7 semaphore register description the apbx dma channel 7 semaphore regist er is used to synchronize between the cpu instruction stream and the dma chain processing state. hw_apbx_ch7_sema 0x80024380 table 447. hw_apbx_ch7_bar 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 address table 448. hw_apbx_ch7_bar bit field descriptions bits label rw reset definition 31:0 address ro 0x00000000 address of system memory buffer to be read or written over the ahb bus. table 449. hw_apbx_ch7_sema 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 phore rsvd1 increment_sema free datasheet http:/// STMP36XX official product documentation 5/3/06 320 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: each dma channel has an 8-bit counti ng semaphore used to synchronize between the program stream and the dma chain proc essing. dma processing continues until the dma attempts to decrement a semaphore that has already reached a value of zero. when the attempt is made, the dma channel is st alled until software incre- ments the semaphore count. example: empty example. 11.5.58. ahb-to-apbx dma channel 7 debug register 1 description this register gives debug visibility in to the apbx dma channel 7 state machine and controls. hw_apbx_ch7_debug1 0x80024390 table 450. hw_apbx_ch7_sem a bit field descriptions bits label rw reset definition 31:24 rsvd2 ro 0x0 reserved, always set to zero. 23:16 phore ro 0x0 this read-only field shows the current (instantaneous) value of the semaphore counter. 15:8 rsvd1 ro 0x0 reserved, always set to zero. 7:0 increment_sema rw 0x00 the value written to this field is added to the semaphore count in an atomic way, such that simultaneous software adds and dma hardware subtracts happening on the same clock are protected. this bit field reads back a value of 0x00. writing a value of 0x02 increments t he semaphore count by two, unless the dma channel decrements the count on the same clock, in which case the count is incremented by a net one. table 451. hw_apbx_ch7_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 req burst kick end rsvd2 nextcmdaddrvalid rd_fifo_empty rd_fifo_full wr_fifo_empty wr_fifo_full rsvd1 statemachine free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 321 table 452. hw_apbx_ch7_debug1 bit field descriptions bits label rw reset definition 31 req ro 0x0 this bit reflects the current state of the dma request signal from the apb device. 30 burst ro 0x0 this bit reflects the current state of the dma burst signal from the apb device. 29 kick ro 0x0 this bit reflects the current state of the dma kick signal sent to the apb device. 28 end ro 0x0 this bit reflects the current state of the dma end command signal sent from the apb device. 27:25 rsvd2 ro 0x0 reserved 24 nextcmdaddrvalid ro 0x0 this bit reflects the internal bit that indicates whether the channel's next command address is valid. 23 rd_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's read fifo empty signal. 22 rd_fifo_full ro 0x0 this bit reflects the current state of the dma channel's read fifo full signal. 21 wr_fifo_empty ro 0x1 this bit reflects the current state of the dma channel's write fifo empty signal. 20 wr_fifo_full ro 0x0 this bit reflects the current state of the dma channel's write fifo full signal. free datasheet http:/// STMP36XX official product documentation 5/3/06 322 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 description: this register allows debug visibility of the apbx dma channel 7. example: empty example. 11.5.59. ahb-to-apbx dma channel 7 debug register 2 description this register gives debug visibility for the apb and ahb byte counts for dma chan- nel 7. hw_apbx_ch7_debug2 0x800243a0 19:5 rsvd1 ro 0x0 reserved 4:0 statemachine ro 0x0 pio display of the dma channel 7 state machine state. idle = 0x00 this is the idle state of the dma state machine. req_cmd1 = 0x01 state in which the dma is waiting to receive the first word of a command. req_cmd3 = 0x02 state in which the dma is waiting to receive the third word of a command. req_cmd2 = 0x03 state in which the dma is waiting to receive the second word of a command. xfer_decode = 0x04 the state machine processes the descriptor command field in this state and branches accordingly. req_wait = 0x05 the state machine waits in this state for the pio apb cycles to complete. req_cmd4 = 0x06 state in which the dma is waiting to receive the fourth word of a command, or waiting to receive the pio words when pio count is greater than 1. pio_req = 0x07 this state determines whether another pio cycle needs to occur before starting dma transfers. read_flush = 0x08 during read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the apb. read_wait = 0x09 when an ahb read request occurs, the state machine waits in this state for the ahb transfer to complete. write = 0x0c during dma write transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. read_req = 0x0d during dma read transfers, the state machine waits in this state until the ahb master arbiter accepts the request from this channel. check_chain = 0x0e upon completion of the dma transfers, this state checks the value of the chain bit and branches accordingly. xfer_complete = 0x0f the state machine goes to this state after the dma transfers are complete, and determines what step to take next. wait_end = 0x15 when the wait for command end bit is set, the state machine enters this state until the dma device indicates that the command is complete. write_wait = 0x1c during dma write transfers, the state machine waits in this state until the ahb master completes the write to the ahb memory space. check_wait = 0x1e if the chain bit is a 0, the state machine enters this state and effectively halts. table 452. hw_apbx_ch7_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 11: ahb-to-apbx bridge with dma 323 description: this register allows debug visibility of the apbx dma channel 7. example: empty example. apbx xml revision: 1.31 table 453. hw_apbx_ch7_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 apb_bytes ahb_bytes table 454. hw_apbx_ch7_debug2 bit field descriptions bits label rw reset definition 31:16 apb_bytes ro 0x0 this value reflects the current number of apb bytes remaining to be transferred in the current transfer. 15:0 ahb_bytes ro 0x0 this value reflects the current number of ahb bytes remaining to be transferred in the current transfer. free datasheet http:/// STMP36XX official product documentation 5/3/06 324 chapter 11: ahb-to -apbx bridge with dma 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 12: ex ternal memory interface (emi) 325 12. external memory interface (emi) this chapter describes the external memory interface (emi) on the STMP36XX, including sections on the dynamic memory controller, static me mory controller, and an operation example. programma ble registers are described in section 12.6 . 12.1. overview the emi is a configurable interface to external sdram and static memories such as nor flash. the emi provides memory-mapped access to as many as four external devices utilizing chip selects. this allows a contiguous address space of 1 gbyte. the emi has native support for 16-mbit, 64-mbit, 128-mbit, 256-mbit, and 512-mbit sdrams. nor flash up to 128 mb are supported. the emi has a 16-bit external data bus and up to a 26-bit address bus. the upper 11 bits of the external address bus are shared with the general-purpose media interface (gpmi). this arrange- ment allows simultaneous access to a gpmi peripheral (such as an ata drive) and an sdram. figure 40 shows a block diagram of th e external memory interface. external memory is connected to the syst em via an ahb slave. the configuration registers are accessed via an apb slave or the apbh bus. the emi uses three clocks: hclk, emiclk, and exram_xclk1 6k. access time to asynchronous memories is programmable, with setup and hold timed defined by integer numbers of hclk cycles. emi peripherals are memory-mapped into the system?s address space and can be directly accessed by the cpu or anot her ahb bus master. the dma?s memcopy peripheral can automatically copy blocks of data between external memory and on- chip sram. the emi?s static memory controller allows individual slaves to be write-protected (generates bus error on writ e to write-protected slave). the emi?s dram controller has a number of power-saving and performance- increasing features, including the following: ? programmable refresh timer allows for temperature-compensated refresh. ? auto-standby mode gates the clock during periods of inactivity. ? support for self-refresh while the STMP36XX is off. ? ahb spits allow other bus masters to access on-chip memory while the emi accesses slower off-chip memory. this a llows multiple outs tanding requests to be pipelined within the controller. ? sdram clock speeds up to 66 mhz are supported. ? ahb transactions of 8, 16, or 32 bits are supported. ? the emi includes 64x32 read/write buffers to improve performance. ? programmable address mode s tune memory utilization to a specific application. free datasheet http:/// STMP36XX official product documentation 5/3/06 326 chapter 12: external memory interface (emi) 5-36xx-d1-1.02-050306 12.2. dynamic memory controller dram timing parameters are based on emic lk cycles. to avoid having to change them when emiclk changes, it is necessa ry to set them acco rding to the worst- case emiclk speed. parameters for mi nimum timings are set according to the maximum emiclk speed. the refresh timer is a special case and uses a stable clock reference rather than emiclk. to ensure correct operation, the dram is put into self-refresh (or power-down) when emiclk is lower than the minimu m necessary to perform auto-refresh. extremely low-power modes, such as usb suspend, may not be able to tolerate the dram?s self-refresh current, which can be as high as 2.5 ma per dram chip. in that case, software must put the dram into the power-down state in which it is not refreshed and loses its contents. the dram controller can be configured to always auto precharge after each burst or wait until either an out-of-row access has occurred or the maximum row-open time (typically 1 ms) has expired. the row-open timer is based on an internal counter that counts emiclk cycles. arm core ahb slave ahb apbh master apbh ahb-to-apbh bridge sram sdram ahb slave to external memories static memory controller dynamic memory controller control registers external memory interface pin mux nor flash general- purpose media interface (gpmi) general- purpose input / output (gpio) figure 40. external memo ry interface block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 12: ex ternal memory interface (emi) 327 the dram controller always uses an 8-cycle burst (16 bytes). ahb wrap8 accesses require the dram controller to perform two dram burst accesses. to support the performance enhancement of the arm926 critical word first cache load, the dram controller provides the firs t requested byte as soon as it can be read. commands given to the sdram chips are encoded on three interface signals: sdram_ras, sdram_cas, and sdram_we. on any rising edge of the sdram chip?s clock, it captures these three lines an d decodes them. when a read command is encoded, the data is available a fixed numb er of cycles later. for the STMP36XX, the mode register is always loaded with a ca s latency of two, which tells the sdram to return data on the second rising edge after a read command. many of the timing parameters specif ied in the sdram timing registers set the minimum time between various commands. sdram no-o p commands are used to fill the gaps and keep all the timing within specification. 12.2.1. dram timing most dram timing parameters are prog rammable. however, the following dram timing parameter is fixed: write recovery time ( twr )?always 2 emiclk cycles. minimum time between last write data in and precharge command. additional cycles may be inserted to meet minimum tr as requirement. 12.3. static memory controller (smc) the emi static memory controller supports external rom, nor flash, and most other asynchronous, parallel data and address devices. its primary function in the STMP36XX is to support nor flash. the static memory controller supports 16-b it external devices. most ahb accesses in the STMP36XX are bursts of four or eight 32-bit words, so the static memory con- troller will often perform si xteen sequential accesses on the external device. to increase efficiency, the smc supports page-mode access. the smc has a single pin timing controller, so if more than one type of device is connected to it, then the worst-case timing of all devices should be programmed. pin timing values are all based on emiclk cycles. if the emiclk speed is to change in the application, the timing values must either be set according to the high- est speed or adjusted when emiclk changes. sdram_clk ref pre nop command sdram_addr all banks sdram_bank act row row bank bank t rp t rfc read col bank t rcd figure 41. sdram progra mmable timing parameters free datasheet http:/// STMP36XX official product documentation 5/3/06 328 chapter 12: external memory interface (emi) 5-36xx-d1-1.02-050306 12.4. emi operation example initialization steps: 1. set the pin muxsel registers to enable emi control of the following pads. (see chapter 35 , ?pin descriptions? on page 809 .) ? sdram pads: ? emi_a[14:0] ? emi_data[15:0] ? emi_casn ? emi_rasn ? emi_wen ? emi_ce0n, emi_ce1n, emi_ce2n, emi_ce3n (as appropriate) ? emi_dqm0, emi_dqm1 ?emi_clk ? emi_cke ? nor flash pad: ? emi_a[25:0] ? emi_data[7:0] or emi_data[15:0] based upon whether flash is 8 bit or 16 bit ? emi_wen ? emi_oen ? emi_ce0n, emi_ce1n, emi_ce2n, emi_ce3n (as appropriate) 2. clear the clkgate bit and set the appropriate divisor value in the clock con- trol's emiclkctrl register. (see chapter 4 , ?clock generation and control? on page 47 for more information.) 3. bring the emi out of soft reset and clock gate. 4. set the chip enable fields in ce3_mode, ce2_mode, ce1_mode, and ce0_mode to the appropriate value. if no device is connected to one of the chip enables, leave the default of zero. if sdram is present, program the following: 1. hw_emidramctrl register must be programmed appropriately. note that emiclk_enable and emiclken_enable must be high for the sdram to function. 2. program the hw_emidramaddr with the appropriate row, column, and mode for the sdram. 3. program the timings for the sdram from the sdram's specification sheet into the hw_emidramtime and hw_emidramtime2 registers. calculate the frequency time based on the settings programmed in the clkctrl registers. the timing values represent x+1 cycle delay. for example, if the sdram requires a minimum 45 ns trc delay and the emiclk is 25 mhz (40-ns clock frequency), then round the clock cycle trc delay to two cycles (80 ns) in order to cover the 45 ns trc. the value programmed into the trc field would be 1. 4. finally, program the hw_emidrammode register. this register must be pro- grammed last, because it triggers a load mode operation to the sdram. at this point, the sdram is ready for operation. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 12: ex ternal memory interface (emi) 329 if nor flash is present, program the following: 1. program the hw_emistaticctrl regist er with the appropriate mem_width and write_protect values. 2. program the timings for the nor flash from the nor flash specification sheet into the hw_emistatictime register. note that the timing are x+1 clock cycles based off the emiclk. 3. you may reset the nor flash by appropr iately setting the reset_out field, being careful to observe the proper reset requirements of the part. at this point, the nor flash should be ready for operation. how to perform a self-refresh to the sdram: 1. wait until the busy field in regist er hw_emidramstat indicates the sdram is not busy. 2. set self_refresh to 1. this instructs the emi to place the sdram into self- refresh mode. 3. to come out of self-refresh, set self_ refresh to 0. the user must wait the requisite amount of time according to th e part's specificatio n sheet before bring- ing the sdram out of self-refresh. how to safely change the emi clock divider: 1. ensure that no device in the system is accessing the emi controller (apbh dma, apbx dma, or usb). 2. wait until the hw_emistat_busy bit is cl ear, indicating that there are no out- standing transactions for the emi to process. 3. write the new value to the hw_clkctrl_emiclkctrl_div bit field. 4. resume accesses to the emi controller. note that the code running on the arm processor to perform this function should be executing out of the on-chip ram and not from the sdram or nor flash. 12.5. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 12.6. programmable registers this section describes the programmable registers of the external memory interface (emi). 12.6.1. emi control register description hw_emictrl 0x80020000 hw_emictrl_set 0x80020004 hw_emictrl_clr 0x80020008 hw_emictrl_tog 0x8002000c free datasheet http:/// STMP36XX official product documentation 5/3/06 330 chapter 12: external memory interface (emi) 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 12.6.2. emi status register description hw_emistat 0x80020010 table 455. hw_emictrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsvd0 ce3_mode ce2_mode ce1_mode ce0_mode table 456. hw_emictrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 reset emi. 0: emi is not reset. 1: emi is reset. 30 clkgate rw 0x1 gates hclk going into emi. 0: clocks are not gated (emi on). 1: clocks are gated (emi off) 29:4 rsvd0 ro 0x0 reserved 3 ce3_mode rw 0x0 selects which controller is connected to ce3. this should only be changed during initialization. static = 0x0 ce3 is connected to an external static memory device. dram = 0x1 ce3 is connected to an external dram device. 2 ce2_mode rw 0x0 selects which controller is connected to ce2. this should only be changed during initialization. static = 0x0 ce2 is connected to an external static memory device. dram = 0x1 ce2 is connected to an external dram device. 1 ce1_mode rw 0x0 selects which controller is connected to ce1. this should only be changed during initialization. static = 0x0 ce1 is connected to an external static memory device. dram = 0x1 ce1 is connected to an external dram device. 0 ce0_mode rw 0x0 selects which controller is connected to ce0. this should only be changed during initialization. static = 0x0 ce0 is connected to an external static memory device. dram = 0x1 ce0 is connected to an external dram device. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 12: ex ternal memory interface (emi) 331 description: empty description. example: empty example. 12.6.3. emi debug register description hw_emidebug 0x80020020 table 457. hw_emistat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dram_present static_present large_dram_enabled rsvd0 write_buffer_data busy table 458. hw_emistat bit field descriptions bits label rw reset definition 31 dram_present ro 0x1 indicates that the dynamic memory controller (sdram/ddr) is present in this product. 30 static_present ro 0x1 indicates that the static memory controller is present in this product. 29 large_dram_enabled ro 0x1 indicates that the dram controller supports large dram memories in this product. a large dram is defined as being greater than 2 mb in size. 28:2 rsvd0 ro 0x0 reserved 1 write_buffer_data ro 0x0 indicates if the emi write buffer has data waiting to be written. empty = 0x0 the write data buffer is empty. not_empty = 0x1 the write buffer is not empty. 0 busy ro 0x0 indicates if the emi is busy. activity on either the dram or static memory controllers will cause this bit to be set. not_busy = 0x0 the emi is not busy. busy = 0x1 the emi is busy. free datasheet http:/// STMP36XX official product documentation 5/3/06 332 chapter 12: external memory interface (emi) 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 12.6.4. emi dram status register description hw_emidramstat 0x80020080 table 459. hw_emidebug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 static_state rsvd0 dram_state table 460. hw_emidebug bit field descriptions bits label rw reset definition 31:19 rsvd1 ro 0x0 reserved 18:16 static_state ro 0x0 represents the current state of the static memory controller. 15:5 rsvd0 ro 0x0 reserved 4:0 dram_state ro 0x0 represents the current state of the dram memory controller. table 461. hw_emidramstat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 self_refresh_ack busy ready free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 12: ex ternal memory interface (emi) 333 description: empty description. example: empty example. 12.6.5. emi dram control register description hw_emidramctrl 0x80020090 hw_emidramctrl_set 0x80020094 hw_emidramctrl_clr 0x80020098 hw_emidramctrl_tog 0x8002009c table 462. hw_emidramstat bit field descriptions bits label rw reset definition 31:3 rsvd0 ro 0x0 reserved 2 self_refresh_ack ro 0x0 indicates that the dram has entered self-refresh mode. 1 busy ro 0x0 indicates that the dram controller is busy (memory access, command, or auto refresh). this bit must be cleared before configuration changes are made or before the dram is placed into self-refresh mode. 0 ready ro 0x0 indicates that the dram controller is ready for a new command (not clock-gated or in self-refresh mode) table 463. hw_emidramctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd3 emiclk_divide auto_emiclk_gate rsvd2 emiclk_enable emiclken_enable dram_type rsvd1 precharge self_refresh rsvd0 table 464. hw_emidramctrl bit field descriptions bits label rw reset definition 31:27 rsvd3 ro 0x0 reserved 26:24 emiclk_divide ro 0x1 hclk-to-emiclk divide ratio. see hw_clkctrl_emiclkctrl_div in the clock control chapter for specifics on the valid values. note that hw_clkctrl_emiclkctrl_div cannot be changed during a transfer, or else the data in the dram may be corrupted. free datasheet http:/// STMP36XX official product documentation 5/3/06 334 chapter 12: external memory interface (emi) 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 12.6.6. emi dram address configuration register description hw_emidramaddr 0x800200a0 hw_emidramaddr_set 0x800200a4 hw_emidramaddr_clr 0x800200a8 hw_emidramaddr_tog 0x800200ac 23 auto_emiclk_gate rw 0x0 when set and the emi is not busy, emi_clk does not run and emi_cke is low. when low, the emi_clk always runs (if emiclk_enable is set) and emi_cke is always high (if emiclken_enable is set). 22 rsvd2 ro 0x0 reserved. 21 emiclk_enable rw 0x0 enables the emi_clk output. when auto_emiclk_gate is not set, this bit forces the clock to be active. when auto_emiclk_gate is set, the clock will propogate to the sdram chip when active cycles are taking place. 20 emiclken_enable rw 0x0 enabled the emi_cke output. when set, emi_cke output is high or automatic ally driven high/low based on the setting of auto_emiclk_gate. when low, emi_cke is always driven low, effectively disabling the external dram devices. 19:16 dram_type ro 0x0 controls the type of memo ry that is connected to the emi dynamic controller. 0x0: sdram, 0x1: lp- sdram, 0x2:mobile-ddr, 0x3: reserved. at this time, only the sdram type is supported. 15:3 rsvd1 ro 0x0 reserved 2 precharge rw 0x0 forces the dram state machine to close any open row at the end of a burst. otherwise, a terminate will be performed, leaving the row open. 1 self_refresh rw 0x0 places the dram into self-refresh mode. this mode must be used if the dram contents are to remain valid when emiclk is too slow, when the emi is disabled or if the STMP36XX is powered down. dram cannot be accessed while in self-refresh mode or a bus error will occur. this bit should on ly be set after the dram controller is not busy, as indicated in the emi dram status register. 0 rsvd0 ro 0x0 reserved table 464. hw_emidramctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 12: ex ternal memory interface (emi) 335 description: empty description. example: empty example. 12.6.7. emi dram mode configuration register description a write to this register forces the dr am state machine to perform a load mode operation. this is required to occur after all other dram timing and address regis- ters are programmed. for the STMP36XX, all sdram chips are set up with a cas latency of 2 and a burst length of 2. hw_emidrammode 0x800200b0 table 465. hw_emidramaddr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 mode row_bits column_bits table 466. hw_emidramaddr bit field descriptions bits label rw reset definition 31:9 rsvd0 ro 0x0 reserved 8 mode rw 0x1 this bit determines th e addressing mode. 0: rbc. 1: brc. rbc = 0x0 extract the dram address from the ahb address using row/bank/column order. brc = 0x1 extract the dram address from the ahb address using bank/row/column order. 7:4 row_bits rw 0xb determines the number of ahb address bits used for the external dram row address. valid values range between 8 and 13. the exact position of these bits in the ahb address is determined by the addressing mode (brc vs. rbc) and the number of column bits. 3:0 column_bits rw 0x8 determines the number of ahb address bits used for the external dram column address (picked from the lower bits of the ahb). valid values range between 8 and 12. free datasheet http:/// STMP36XX official product documentation 5/3/06 336 chapter 12: external memory interface (emi) 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 12.6.8. emi dram timing control register 1 description the emi dram timing control register 1 sets up timing parameters for dram memories. all timing should be set according to the fastest emiclk and slowest dram used in a system. hw_emidramtime 0x800200c0 hw_emidramtime_set 0x800200c4 hw_emidramtime_clr 0x800200c8 hw_emidramtime_tog 0x800200cc table 467. hw_emidrammode 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 cas_latency rsvd0 table 468. hw_emidrammode bit field descriptions bits label rw reset definition 31:7 rsvd1 ro 0x0 reserved 6:4 cas_latency rw 0x0 this value sets the internal latency at which the sdram read data is captured. the sdram chip is always set up with a cas late ncy of 2. th is register allows the internal latency to be changed in case of timing issues. reserved0 = 0x0 reserved. reserved1 = 0x1 reserved. cas2 = 0x2 set the cas latency to 2. cas3 = 0x3 set the cas latency to 3. reserved4 = 0x4 reserved. reserved5 = 0x5 reserved. reserved6 = 0x6 reserved. reserved7 = 0x7 reserved. 3:0 rsvd0 ro 0x0 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 12: ex ternal memory interface (emi) 337 description: empty description. example: empty example. table 469. hw_emidramtime 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 trfc trc tras trcd rsvd0 trp txsr refresh_counter table 470. hw_emidramtime bit field descriptions bits label rw reset definition 31:28 rsvd1 ro 0x0 reserved 27:24 trfc rw 0xf auto-refresh period. minimum number of emiclks between each auto-refresh cycle. 23:20 trc rw 0xf active-to-active command period. minimum number of emiclk cycles between activations of the same dram bank. 19:16 tras rw 0xf active-to-precharge command. minimum number of emiclk cycles to wait afte r activating a bank before precharging that bank. 15:12 trcd rw 0xf trcd. time between active and read/write command in emiclk cycles. 11:10 rsvd0 ro 0x0 reserved 9:8 trp rw 0x3 precharge command period (trp) in emiclk cycles. time to wait for precharge command to complete before issuing another command to the same bank. should be set according to the highest emiclk. 7:4 txsr rw 0xf number of emiclk c ycles to wait before issuing command after exit ing self-refresh (0=1 cycle; 0xf=16 cycles) 3:0 refresh_counter rw 0xf number of refresh cycles per 16-khz (62.5-us) reference clock tick. (0 = 1 refresh per tick; 0xf = 16 cycles per tick) free datasheet http:/// STMP36XX official product documentation 5/3/06 338 chapter 12: external memory interface (emi) 5-36xx-d1-1.02-050306 12.6.9. emi dram timing control register 2 description the emi dram timing control register 2 sets up timing parameters for dram memories. all timing should be set according to the fastest emiclk and slowest dram used in a system. hw_emidramtime2 0x800200d0 hw_emidramtime2_set 0x800200d4 hw_emidramtime2_clr 0x800200d8 hw_emidramtime2_tog 0x800200dc description: empty description. example: empty example. 12.6.10. emi static memory control register description hw_emistaticctrl 0x80020100 hw_emistaticctrl_set 0x80020104 hw_emistaticctrl_clr 0x80020108 hw_emistaticctrl_tog 0x8002010c table 471. hw_emidramtime2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 precharge_count table 472. hw_emidramtim e2 bit field descriptions bits label rw reset definition 31:16 rsvd1 ro 0x0 reserved 15:0 precharge_count rw 0xffff number of emi clock cycles after an activate command before we must forc e a precharge to close a bank. if no other command causes a precharge after the activate, this counter forces the precharge. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 12: ex ternal memory interface (emi) 339 description: empty description. example: empty example. 12.6.11. emi static memory timing control register description hw_emistatictime 0x80020110 hw_emistatictime_set 0x80020114 hw_emistatictime_clr 0x80020118 hw_emistatictime_tog 0x8002011c table 473. hw_emistaticctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 mem_width write_protect reset_out table 474. hw_emistaticct rl bit field descriptions bits label rw reset definition 31:3 rsvd0 ro 0x0 reserved 2 mem_width rw 0x1 0: 8-bit memory (for nor only). 1: 16-bit memory (for sdram only). 1 write_protect rw 0x0 0: writes to addresse s mapped to static memory are allowed. 1: write to the addresses mapped to the static memory are not allowed. this prevents bus contention if a rom is connected to t he static memory controller. 0 reset_out rw 0x0 0: reset ouput is low. 1: reset output is high table 475. hw_emistatictime 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd4 thz rsvd2 tdh rsvd1 tds rsvd0 tas free datasheet http:/// STMP36XX official product documentation 5/3/06 340 chapter 12: external memory interface (emi) 5-36xx-d1-1.02-050306 description: empty description. example: empty example. emi xml revision: 1.40 table 476. hw_emistatictime bit field descriptions bits label rw reset definition 31:28 rsvd4 ro 0x0 reserved 27:24 thz rw 0xf number of emiclk cycl es to wait fo r the emi to return the data bus to high-z after write-enable strobe is deasserted. set this to prevent bus contention when switching from read to write. 23:20 rsvd2 ro 0x0 reserved 19:16 tdh rw 0xf data hold. emiclk+1 cycl es that the data is held after the write strobe is dea sserted. also the time that the read/write strobe is deasserted in a cycle. 15:12 rsvd1 ro 0x0 reserved 11:8 tds rw 0xf data setup. emiclk+1 cycles that the data is valid before write strobe is deasserted. also the time that the read/write strobe is asserted in a cycle. the total cycle time is tds+tdh. 7:4 rsvd0 ro 0x0 reserved 3:0 tas rw 0xf address setup. emiclk+1 cycles between chip select and address asserti on to read/write strobe assertion. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 341 13. general-purpose media interface (gpmi) this chapter describes the general-pur pose media interface (gpmi) on the STMP36XX, including sections on both ata and nand modes. programmable reg- isters are described in section 13.5 . 13.1. overview the general-purpose media interface (gpmi) controller is a flexib le interface to an ata device or up to four nand flash. ata udma and pio modes are supported. the nand mode has configurable addres s and command behavior, providing sup- port for future devices not yet spec ified. the gpmi resides on the apbh. registers are clocked on the hclk domain. the i/o and pin timing are clocked on a dedicated gpmiclk domain. gpmiclk can be set to maximize i/o performance: (hclk / 4) <= gpmiclk <= (hclk * 4) figure 42 shows a block diagram of the gpmi controller. 13.2. gpmi ata mode the gpmi supports ata devices using ata-pio mode 4 and udma-4. it can also support compactflash devices configured for true ide mode. the gpmi is designed to support a single ata device, although additional devices can be added using gpio pins. 13.2.1. basic ata operation the gpmi supports all basic ata operations, including: ? register/data read/write ?the gpmi can repeatedly access one register address, as is done with the ata data register. or, it can increment the ata address to read/write a configuration to several ata registers. the gpmi uses a transfer counter to know how many bytes to read/write to the ata device. this allows the gpmi to properly use its receive fifo full during reads. ? wait for ata irq ?many ata commands require a significant amount of time to complete. when the device is complete, it can signal the gpmi using the irq function. the gpmi has a timeout counter that asserts an error irq to the cpu if it expires before the ata device has asserted the irq signal. ? check status ?the read and compare mode can be used to compare an ata status word against a reference. if unexpe cted status is returned, then the gpmi indicates an error to the dma controller. the dma can then branch to an alternate command descriptor, which either fixes the problem or interrupts the cpu. ? data transfer ?data can be transferred to/from an ata or atapi device using pio or udma mode. in most ca ses, udma mode is preferred. 13.2.2. gpmi ata clocking and timing the gpmi has programmable timing for the important parameters. all timing is based on gpmiclk, which is a dedicated clock. gpmiclk is derived from the pll and has its own integer divider. theref ore, gpmiclk is dependant on pll fre- quency changes, but not on other dividers . complete information about gpmiclk generation can be found in chapter 4 , ?clock generation and control? on page 47 . free datasheet http:/// STMP36XX official product documentation 5/3/06 342 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 13.2.3. gpmi ata pin sharing the STMP36XX pinout allows for simultaneous ata and sdram activity. an ata device can also be used in the same system as a nand or nor flash, but the devices cannot operate simultaneously, so software arbitration of the pins is neces- sary. the gpmi has the basic set of pins needed to support an ata device: ? cs0, cs1 chip selects ?shared with the gpmi nand controller and the emi. if ata is used, then these chip selects must not be used for another device. ? addr[2:0] address lines ?shared with the gpmi nand controller?s ale and cle lines. system clock generator gpmi state machine 0 arm core ahb slave ahb shared dma ahb master apbh master apbh ahb-to-apbh bridge sram gpmi pin state machine dma request 1 hclk gpmiclk gpmi pin arbitration gpmi state machine 1 gpmi state machine 2 gpmi state machine 3 dma request 0 dma request 2 dma request 3 hclk gpmi gpmi / memory / gpio pin mux gpio memory controller pins figure 42. general-purpose media interface controller block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 343 ? data[15:0] data bus ?shared with the gpmi nand controller. the upper data bits (15:8) are also shared with the emi?s nor flash interface. ? irq interrupt ?shared with the nand1 ready/busy. ? iordy-:ddmardy-:dstrobe i/o ready, device dma ready, and device strobe ?shared with nand0 ready/busy. ? dmack dma acknowledge? shared with nand2 ready/busy. this pin can be configured as an input for nand mode and output for ata udma. ? dior-:hdmardy-:hstrobe. pio read strobe, host dma ready and host dma strobe ?shared with the nand read strobe. ? diow-:stop pio write strobe and host dma stop ?shared with the nand write strobe. ? dmarq device dma request ?shared with nand read/busy 3. this pin is an input but the nand and ata can share th e line since they both have three-state (ata) or open-drain (nand) drivers. it is possible for an STMP36XX-based system to support an ata and one or two nand flash. however, the ata and nand cannot perform simultaneous transac- tions. 13.2.4. ata pio mode timing figure 43 illustrates the basic gpmi timing parameters in ata mode. 13.2.5. ata udma mode the gpmi supports ata udma up to mode 4, which allows bus transfers of up to 66 mb/s. udma also allows a much simpler dma descriptor chain than pio opera- tion. ata-pio requires that the host receive an interrupt and check status for each block (typically 512 bytes). ud ma allows multiple blocks, up to 64 kbytes total, to be transferred with a simp le set of descriptors. udma uses a significantly different pin arch itecture than pio. pio mode timing uses asynchronous read/write strobes that are controlled by the host. the device can slow down the data transfer within a block using the iordy signal. the device uses the intrq signal to indicate when it is ready to send/receive data between blocks. udma uses data strobes that are asserted by the side actively writing the data (hstrobe for the host, dstrobe for the de vice). the data is transferred on both the rising and falling ed ges of the strobes. data0 gpmi_oen/ gpmi_wrn gpmi_data tds tdh gpmi_rdy data1 tas gpmi_addr[2:0] / gpmi_ce[3:0] tdh trdy cycle extended by rdy tds figure 43. ata pio timing mode free datasheet http:/// STMP36XX official product documentation 5/3/06 344 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 the device has a dmarq (dma request) signal to indicate that it is ready to trans- fer data to/from the host. the host has a dmack (dma acknowledge) signal to respond to the device dmarq that it is also ready to transfer data. the host and device each have dma ready (hdmardy and ddmardy) signals used for cycle-to-cycle flow control during tr ansfers. for example, if the host is read- ing a block and its fifo becomes full, it negates hdmardy, and the device stops toggling dstrobe and sending new data until the host reasserts hdmardy. the host can abort a data transfer by asserting the stop signal. 13.2.6. udma timings figure 44 illustrates the udma data write timing . valid data is presented at tds before the rising or falling edge of each strobe and held for tdh. the cycle time per word is therefore tds+tdh, and the time for a complete strobe cycle (rising and falling edges) is 2(tds+tdh). 13.2.7. ata command/irq/check status example figure 45 illustrates a complex ata operation includin g an ata read command, wait for irq and check status. data0 gpmi_data tdh hstrobe tds data1 data2 data3 tds tdh tds+tdh tds+tdh figure 44. udma timing read cmd gpmi_wrn gpmi_data gpmi_irq gpmi_ce0 gpmi write gpmi wait for ready gpmi_rdn status gpmi read and compare cmd_reg gpmi_addr status_reg figure 45. ata command/irq/check status example free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 345 13.3. gpmi nand mode the general-purpose media interface has several features to efficiently support nand: ? individual chip select and ready/busy pins for four nands (two in 100-pin package). ? individual state machine and dma channel for each chip select. ? special command modes work with dma controller to perform all normal nand functions without cpu intervention. ? configurable timing based on a dedicated clock allows optimal balance of high nand performance and low system power. since current nand flash does not support multiple page read/write commands, the gpmi and dma have been designed to handle complex multi-page operations with- out cpu intervention. the dma uses a lin ked descriptor function with branching capability to automatically ha ndle all of the operations ne eded to read/write multiple pages: ? data/register read/write ?the gpmi can be programmed to read or write multiple cycles to the nand address, command or data registers. ? wait for nand ready ?the gpmi?s wait-for-rea dy mode can monitor the ready/busy signal of a single nand flash and signal the dma when the device has become ready. it also has a timeout counter and can indicate to the dma that a timeout error has occurred. the dmas can conditionally branch to a different descriptor in the case of an error. ? check status ?the read-and-compare mode allows the gpmi to check nand status against a reference. if an error is found, the gpmi can instruct the dma to branch to an alternate descriptor, which attempts to fix the problem or asserts a cpu irq. 13.3.1. multiple nand support the gpmi supports up to four nand chip selects, each with independent ready/busy signals. since they share a data bus and control lines, the gpmi can only actively communicate with a single nand at a time. however, all nands can concurrently perform internal read, write, or erase operations. with fast nand flash and software support for concurrent nand operations, this arch itecture allows the total throughput to approach the data bus speed, which can be as high as 66 mb/s (16-bit bus running at 33 mhz). 13.3.2. gpmi nand timing and clocking the dedicated clock, gpmiclk, is used as a timing reference for nand flash i/o. since various nands have different timing requirements, gpmiclk may need to be adjusted for each application. while the actual pin timings are limited by the nand chips used, the gpmi can support data bus speeds of up to 33 mhz x 16 bits. the actual read/write strobe timing parameters are adjusted as indicated in the register descriptions in section 13.5 . refer to chapter 4 for more information about setting gpmiclk. free datasheet http:/// STMP36XX official product documentation 5/3/06 346 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 13.3.3. basic nand timing figure 46 illustrates the operation of the timing parameters in nand mode. 13.3.4. nand command and address timing example figure 47 illustrates a command and address being sent to a nand flash. 13.3.5. nand read timing the dsample_time is a programmable field in hw_gpmi_ctrl1 register that controls when read data from a nand device is sampled in the gpmi module. this section describes how to understand the timing issues involved in order to correctly program it. in the nand read path timing shown in figure 48 , tsample represents the time from sample point ds0 (the rising edge of rdn @ host) to the middle of the window of valid data. by knowing tsample and the gpmiclk period, the correct sample point can be selected. data0 gpmi_oen/ gpmi_wrn gpmi_data tds tdh data1 tas gpmi_ce[3:0] / ale / cle tdh tds figure 46. basic nand timing gpmi_cle $00 gpmi_ale gpmi_wen gpmi_data al[7:0] al[15:8] read cmd gpmi_cen tas tds tdh tas run=1 run=0 run=1 tds tdh run=0 tdh figure 47. nand command and address timing example free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 347 in figure 48 , tvaldata is the length of the valid read data window. this and the other values shown can be calculated from the following: tvaldata = tds + trhoh - trea (apply when trc < 30 ns) tvaldata = trc + trloh ? trea (apply when trc > 30 ns) read cycle time is trc = tds + tdh. tsamplemax = toutmin + (trea ? tds) + tinmin + tvaldata tsamplemin = toutmax + (trea ? tds) + tinmax tsample = (tsamplemin + tsamplemax) / 2 dsample_time = tsample / (gpmiclk_period / 2). round to the nearest integer. note that (trea ? tds) could be negati ve, and therefore tsample could also be negative. if so, then dsampl e_time will be zero. also, parameters must be cho- sen such that tsamplemax is greater than tsamplemin. further, ensure that the following condition is met after rounding: tsamplemin < (dsample_time * gpmiclk_period/2) < tsamplemax ds3 ds2 ds1 ds0 gpmiclk tds tdh tvaldata toutmin tinmin trea trloh toutmin tinmin toutmax tinmax toutmax tinmax gpmiclk_period tsamplemin tsamplemax trea rdn @ nand (fastest) rdn @ host trloh trea trea trc data @ nand (fastest) data @ host (fastest) rdn @ nand (slowest) data @ nand (slowest) data @ host (slowest) figure 48. gpmi nand read path timing free datasheet http:/// STMP36XX official product documentation 5/3/06 348 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 note that figure 48 has been drawn approximately to scale to represent the mini- mum and maximum timings for a system using a 120-mhz gpmiclk (i.e., gpmiclk_period = 8.33 ns) with a total load between the board and the nand of 30 pf. the trea for the nand in figure 48 was 20 ns, and the trloh was 5 ns. with this kind of load, the STMP36XX timing was a worst case of toutmax of 8.5 ns and tinmax of 5 ns and a best case of toutmin of 4 ns and iinmin of 3 ns. with such fast timings as this (3 3.3-ns read cycles), the only acceptable dsample_time setting is 3. appropriat e timing values for other systems can be calculated using the timing data in table 477 . 13.4. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 13.5. programmable registers the following registers provide control for programmable elements of the gpmi module. 13.5.1. gpmi control register 0 description the gpmi control register 0 specifies the gpmi transaction to perform for the cur- rent command chain item. hw_gpmi_ctrl0 0x8000c000 hw_gpmi_ctrl0_set 0x8000c004 hw_gpmi_ctrl0_clr 0x8000c008 hw_gpmi_ctrl0_tog 0x8000c00c table 477. tout: pad_gpmi_rdn output delay (ns) load (pf) 4 ma (min) 4 ma (max) 8 ma (min) 8 ma (max) 10 4.22 8.53 3.61 7.31 20 5.14 10.16 4.00 8.04 30 6.06 11.85 4.38 8.76 40 6.98 13.53 4.75 9.46 50 7.90 15.21 5.13 10.17 60 8.80 16.86 5.50 10.87 70 9.67 18.48 5.87 11.58 80 10.49 20.03 6.24 12.28 90 11.21 21.45 6.62 12.99 100 11.93 22.88 6.99 13.69 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 349 table 478. hw_gpmi_ctrl0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate run dev_irq_en timeout_irq_en udma command_mode word_length lock_cs cs address address_increment xfer_count table 479. hw_gpmi_ctrl0 bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 set to zero for normal operation. when this bit is set to one (default), then the entire block is held in its reset state. run = 0x0 allow gpmi to operate normally. reset = 0x1 hold gpmi in reset. 30 clkgate rw 0x1 set this bit zero for normal operation. setting this bit to one (default) gates all of the block level clocks off to miniminize ac energy consumption. run = 0x0 allow gpmi to operate normally. no_clks = 0x1 do not clock gpmi gates in order to minimize power consumption. 29 run rw 0x0 the gpmi is busy running a command whenever this bit is set to '1'. the gpmi is idle whenever this bit set to zero. this can be set to one by a cpu write. in addition, the dma sets this bit each time a dma command has finished its pio transfer phase. idle = 0x0 the gpmi is idle. busy = 0x1 the gpmi is busy running a command. 28 dev_irq_en rw 0x0 when set to 1 and ata_irq pin is asserted, the gpmi_irq output will assert. 27 timeout_irq_en rw 0x0 setting this bit to 1 will enable timeout irq for transfers in ata mode only, and for wait_for_ready commands in both ata and nand mode. the device_busy_timeout value is used for this timeout. 26 udma rw 0x0 0= use ata-pio mode on the external bus. 1= use ata-ultra dma mode on the external bus. disabled = 0x0 use ata-pio mode on the external bus. enabled = 0x1 use ata-ultra dma mode on the external bus. free datasheet http:/// STMP36XX official product documentation 5/3/06 350 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 25:24 command_mode rw 0x0 00= write mode. 01= read mode. 10= read and compare mode (setting sense flop). 11= wait for ready. write = 0x0 write mode. read = 0x1 read mode. read_and_compare = 0x2 read and compare mode (setting sense flop). wait_for_ready = 0x3 wait for ready mode. for ata wait_for_ready command set cs=01. 23 word_length rw 0x0 0= 16-bit data bus mode. 1= 8-bit data bus mode. this bit should only be changed when run==0. 16_bit = 0x0 16-bit data bus mode. 8_bit = 0x1 8-bit data bus mode. 22 lock_cs rw 0x0 for ata/nand mode: 0= deassert chip select (cs) after run is complete. 1= co ntinue to assert chip select (cs) after run is complete. for camera mode: 0= do not wait for vsync rising edge before capturing data. 1= wait for vsync rising edge before capturing data (camera mode only). disabled = 0x0 deassert chip select (cs) after run is complete. enabled = 0x1 continue to assert chip select (cs) after run is complete. 21:20 cs rw 0x0 selects which chip select is active fo r this command. for ata wait_for_ready command, this must be set to b01. 19:17 address rw 0x0 specifies the three address lines for ata mode. in nand mode, use a0 for cle and a1 for ale. nand_data = 0x0 in nand mode, this address is used to read and write data bytes. nand_cle = 0x1 in nand mode, this address is used to write command bytes. nand_ale = 0x2 in nand mode, this address is used to write address bytes. 16 address_increment rw 0x0 0= address does not increment. 1= increment address. in ata mode, the address will increment with each cycle. in nand mode, the address will increment once, after the first cycle (going from cle to ale). disabled = 0x0 address does not increment. enabled = 0x1 increment address. 15:0 xfer_count rw 0x0 number of words (8- or 16 -bit wide) to transfer for this command. table 479. hw_gpmi_ctrl0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 351 13.5.2. gpmi compare register description the gpmi compare register specifies the expected data and the xor mask for comparing to the status values read from the device. this register is used by the read and compare command. hw_gpmi_compare 0x8000c010 description: empty description. example: empty example. 13.5.3. gpmi control register 1 description the gpmi control register 1 specifies addit ional control fields that are not used on a per-transaction basis. hw_gpmi_ctrl1 0x8000c020 hw_gpmi_ctrl1_set 0x8000c024 hw_gpmi_ctrl1_clr 0x8000c028 hw_gpmi_ctrl1_tog 0x8000c02c table 480. hw_gpmi_compare 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 mask reference table 481. hw_gpmi_comp are bit field descriptions bits label rw reset definition 31:16 mask rw 0x0000 16-bit mask that is applied after the read data is xored with the reference bit field. 15:0 reference rw 0x0000 16-bit value that is xored with data read from the nand device. free datasheet http:/// STMP36XX official product documentation 5/3/06 352 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 table 482. hw_gpmi_ctrl1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 dsample_time rsvd1 dev_irq timeout_irq burst_en abort_wait_for_ready3 abort_wait_for_ready2 abort_wait_for_ready1 abort_wait_for_ready0 dev_reset ata_irqrdy_polarity camera_mode gpmi_mode table 483. hw_gpmi_ctrl1 bit field descriptions bits label rw reset definition 31:14 rsvd2 ro 0x0 always write zeroes to this bit field. 13:12 dsample_time rw 0x0 this variable allows you to select the time when device read data is sampled. 0= at the rising edge of gpmi_clk when the read strobe deasserts. 1= one-half gpmi_clk cycle later than when dsample_time == 0. 2= one full gpmi_clk cycle later than when dsample_time == 0. 3= one and o ne-half gpmi_clk cycles later than when dsample_time == 0. 11 rsvd1 ro 0x0 always write zeroes to this bit field. 10 dev_irq rw 0x0 this bit is set when an interrupt is received from the ata device. write 0 to clear. 9 timeout_irq rw 0x0 this bit is set when a timeout occurs using the device_busy_timeout valu e. write 0 to clear. 8 burst_en rw 0x0 when set to 1, each dma request will generate a 4- transfer burst on the apb bus. 7 abort_wait_for_ready3 rw 0x0 abort a wait-for-ready command on channel 3. 6 abort_wait_for_ready2 rw 0x0 abort a wait-for-ready command on channel 2. 5 abort_wait_for_ready1 rw 0x0 abort a wait-for-ready command on nand channel 1 or ata channel 0. 4 abort_wait_for_ready0 rw 0x0 abort a wait-for-ready command on channel 0. 3 dev_reset rw 0x0 0= device reset pin is held low (asserted). 1= device reset pin is held high (deasserted). enabled = 0x0 device reset pin is held low (asserted). disabled = 0x1 device reset pin is held high (deasserted). free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 353 description: empty description. example: empty example. 13.5.4. gpmi timing register 0 description the gpmi timing register 0 specifies the timing parameters that are used by the cycle state machine to guarantee the various setup, hold, and cycle times for the external media type. hw_gpmi_timing0 0x8000c030 2 ata_irqrdy_polarity rw 0x1 for ata mode: 0= external ata iordy and irq are active low. 1= external ata iordy and irq are active high. for nand mode: 0= external rdy_busy[ 1] and rdy_busy[0] pins are ready when low and busy when high. 1= external rdy_busy[ 1] and rdy_busy[0] pins are ready when high and busy when low. note nand_rdy_busy[3:2] are not affected by this bit. activelow = 0x0 ata iordy and irq are active low, or nand_rdy_busy[1:0] are active low ready. activehigh = 0x1 ata iordy and irq are active high, or nand_rdy_busy[1:0] are active high ready. 1 camera_mode rw 0x0 when set to 1 and ata udma is enabled the udma interface becomes a camera interface. 0 gpmi_mode rw 0x0 0= nand mode. 1= ata mode. ata mode is only supported on channel zero. if ata mode is selected, then only channel three is available for nand use. nand = 0x0 nand mode. ata = 0x1 ata mode. table 484. hw_gpmi_timing0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 address_setup data_hold data_setup table 483. hw_gpmi_ctrl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 354 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 13.5.5. gpmi timing register 1 description the gpmi timing register 1 specifies the timeouts used when monitoring the nand ready pin or the ata irq and iowait signals. hw_gpmi_timing1 0x8000c040 table 485. hw_gpmi_timing 0 bit field descriptions bits label rw reset definition 31:24 rsvd1 ro 0x0 always write zeroes to this bit field. 23:16 address_setup rw 0x01 number of gpmiclk cycles that the ce/addr signals are active before a strobe is asserted. a value of zero is interpreted as 0. for ata pio modes, this is known in the ata7 specification as "address valid to dior-/diow- setup" 15:8 data_hold rw 0x02 data bus hold time in gpmiclk cycles. also the time that the data strobe is deasserted in a cycle. a value of 0 is interpreted as 64k cycles. for ata pio modes this is known in the ata7 specification as "dior-/diow- recovery time" 7:0 data_setup rw 0x03 data bus setup time in gpmiclk cycles. also the time that the data strobe is asserted in a cycle. this value must be greater than 2 for ata devices that use iordy to extend transfer cycles. a value of 0 is interpreted as 64k cycles. fo r ata pio modes, this is known in the ata7 specification as "dior-/diow-" table 486. hw_gpmi_timing1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 device_busy_timeout ata_ready_timeout free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 355 description: empty description. example: empty example. 13.5.6. gpmi timing register 2 description the gpmi timing register 2 specifies th e udma timing parameters that are used by the cycle state machine to guarantee the various setup, hold, and cycle times for the external media type. hw_gpmi_timing2 0x8000c050 description: table 487. hw_gpmi_timing 1 bit field descriptions bits label rw reset definition 31:16 device_busy_timeout rw 0x0000 timeout waiting for nand ready/busy or ata irq. used in wait_for_ready mode. this value is the number of gpmi_clk cycles multiplied by 4096. 15:0 ata_ready_timeout rw 0x0000 (deprecated - use device_busy_timeout instead) timeout waiting for iordy to be asserted high. atamode only. this value is the number of gpmi_clk cycles. table 488. hw_gpmi_timing2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 udma_trp udma_env udma_hold udma_setup table 489. hw_gpmi_timing 2 bit field descriptions bits label rw reset definition 31:24 udma_trp rw 0x09 udma ready-to-pause timi ng. this bit field is also used to specify tss. (refer to the udma timing specification.) set udma_trp to the larger of (trp, tss). a value of zero is interpreted as 64k cycles. 23:16 udma_env rw 0x02 udma envelope time. this bit field is also used to specify tmli and tzah. (refer to the udma timing specification.) set udma_env = max (tenv, tmli, tzah). a value of zero is interpreted as 64k cycles. 15:8 udma_hold rw 0x01 udma data bus hold time in gpmiclk cycles. a value of zero is inte rpreted as 64k cycles. 7:0 udma_setup rw 0x01 udma data bus setup time in gpmiclk cycles. a value of zero is inte rpreted as 64k cycles. free datasheet http:/// STMP36XX official product documentation 5/3/06 356 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 empty description. example: empty example. 13.5.7. gpmi dma data transfer register description the gpmi dma data transfer register is used by the dma to read or write data to or from the ata/nand control state machine. hw_gpmi_data 0x8000c060 description: empty description. example: empty example. 13.5.8. gpmi status register description the gpmi status register provides a read -back path for various operational states of the gpmi controller. hw_gpmi_stat 0x8000c070 table 490. hw_gpmi_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 data table 491. hw_gpmi_data bit field descriptions bits label rw reset definition 31:0 data rw 0x00000 in 16-bit mode, this register can be accessed in two 16-bit operations, one bus cycl e per operation. in 8-bit mode, one, two, three, or four bytes can can be accessed to send the same number of bus cycles. byte writes are supported only for the least significant byte. half-word (16-bit) writes are supported only for the lower half-word. table 492. hw_gpmi_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 present rsvd1 rdy_timeout ata_irq rsvd2 fifo_empty fifo_full dev3_error dev2_error dev1_error dev0_error free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 357 description: empty description. example: empty example. 13.5.9. gpmi debug information register description the gpmi debug information register provides a read-b ack path for diagnostics to determine the current operating state of the gpmi controller. hw_gpmi_debug 0x8000c080 table 493. hw_gpmi_stat bit field descriptions bits label rw reset definition 31 present ro 0x1 0= gpmi is not present in this product. 1= gpmi is present is in this product. unavailable = 0x0 gpmi is not present in this product. available = 0x1 gpmi is present in this product. 30:12 rsvd1 ro 0x0 always write zeroes to this bit field. 11:8 rdy_timeout ro 0x0 status of the rdy/busy timeout flags. 7 ata_irq ro 0x0 status of the ata_irq input pin. 6 rsvd2 ro 0x0 always write zeroes to this bit field. 5 fifo_empty ro 0x1 0= fifo is not empty. 1= fifo is empty. not_empty = 0x0 fifo is not empty. empty = 0x1 fifo is empty. 4 fifo_full ro 0x0 0= fifo is not full. 1= fifo is full. not_full = 0x0 fifo is not full. full = 0x1 fifo is full. 3 dev3_error ro 0x0 0= no error condition present on ata/nand device 3. 1= an error has occurred on ata/nand device 3 (timeout or compare failure, depending on command_mode). 2 dev2_error ro 0x0 0= no error condition present on ata/nand device 2. 1= an error has occurred on ata/nand device 2 (timeout or compare failure, depending on command_mode). 1 dev1_error ro 0x0 0= no error condition present on ata/nand device 1. 1= an error has occurred on ata/nand device 1 (timeout or compare failure, depending on command_mode). 0 dev0_error ro 0x0 0= no error condition present on ata/nand device 0. 1= an error has occurred on ata/nand device 0 (timeout or compare failure, depending on command_mode). free datasheet http:/// STMP36XX official product documentation 5/3/06 358 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 table 494. hw_gpmi_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ready3 ready2 ready1 ready0 wait_for_ready_end3 wait_for_ready_end2 wait_for_ready_end1 wait_for_ready_end0 sense3 sense2 sense1 sense0 dmareq3 dmareq2 dmareq1 dmareq0 cmd_end udma_state busy pin_state main_state table 495. hw_gpmi_debug bit field descriptions bits label rw reset definition 31 ready3 ro 0x0 read-only view of ready line 3. 30 ready2 ro 0x0 read-only view of ready line 2. 29 ready1 ro 0x0 read-only view of ready line 1. 28 ready0 ro 0x0 read-only view of ready line 0. 27 wait_for_ready_end3 ro 0x0 read-only view of wait_for_ready command end of channel 3. this view sees the toggle state. 26 wait_for_ready_end2 ro 0x0 read-only view of wait_for_ready command end of channel 2. this view sees the toggle state. 25 wait_for_ready_end1 ro 0x0 read-only view of wait_for_ready command end of channel 1. this view sees the toggle state. 24 wait_for_ready_end0 ro 0x0 read-only view of wait_for_ready command end of channel 0. this view sees the toggle state. 23 sense3 ro 0x0 read-only view of sense state of channel 3. a value of "1" indicates that a read and compare command failed or a timeout occured. 22 sense2 ro 0x0 read-only view of sense state of channel 2. a value of "1" indicates that a read and compare command failed or a timeout occured. 21 sense1 ro 0x0 read-only view of sense state of channel 1. a value of "1" indicates that a read and compare command failed or a timeout occured. 20 sense0 ro 0x0 read-only view of sense state of channel 0. a value of "1" indicates that a read and compare command failed or a timeout occured. 19 dmareq3 ro 0x0 read-only view of dma request line for channel 3. this view sees the toggle state. 18 dmareq2 ro 0x0 read-only view of dma request line for channel 2. this view sees the toggle state. 17 dmareq1 ro 0x0 read-only view of dma request line for channel 1. this view sees the toggle state. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 13: general -purpose media interface (gpmi) 359 description: empty description. example: empty example. 16 dmareq0 ro 0x0 read-only view of dma request line for channel 0. this view sees the toggle state. 15:12 cmd_end ro 0x0 read-only view of the command end toggle to dma. one per channel 11:8 udma_state ro 0x0 usm_idle = 4'h0, idle usm_dmarq = 4'h1, dma req usm_ack = 4'h2, dma ack usm_fifo_e = 4'h3, fifo empty usm_wpause = 4'h4, wr dma paused by device usm_tstrb = 4'h5, toggle hstrobe usm_captur = 4'h6, capture stage, (data sampled with dstrobe is valid) usm_datout = 4'h7, change burst dataout usm_crc = 4'h8, source crc to device usm_wait_r = 4'h9, waiting for ddmardy- usm_end = 4'ha; negate dmaack (end of dma) 7 busy ro 0x0 when asserted, the gpmi is busy. undefined results may occur if any registers are written when busy is asserted. disabled = 0x0 the gpmi is not busy. enabled = 0x1 the gpmi is busy. 6:4 pin_state ro 0x0 parameter psm_idle = 3'h0, psm_bytcnt = 3'h1, psm_addr = 3'h2, psm_stall = 3'h3, psm_strobe = 3'h4, psm_atardy = 3'h5, psm_dhold = 3'h6, psm_done = 3'h7. psm_idle = 0x0 psm_bytcnt = 0x1 psm_addr = 0x2 psm_stall = 0x3 psm_strobe = 0x4 psm_atardy = 0x5 psm_dhold = 0x6 psm_done = 0x7 3:0 main_state ro 0x0 parameter msm_idle = 4'h0, msm_bytcnt = 4'h1, msm_waitfe = 4'h2, msm_waitfr = 4'h3, msm_dmareq = 4'h4, msm_dmaack = 4'h5, msm_waitff = 4'h6, msm_ldfifo = 4'h7, msm_lddmar = 4'h8, msm_rdcmp = 4'h9, msm_done = 4'ha. msm_idle = 0x0 msm_bytcnt = 0x1 msm_waitfe = 0x2 msm_waitfr = 0x3 msm_dmareq = 0x4 msm_dmaack = 0x5 msm_waitff = 0x6 msm_ldfifo = 0x7 msm_lddmar = 0x8 msm_rdcmp = 0x9 msm_done = 0xa table 495. hw_gpmi_debug bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 360 chapter 13: general-purpose media interface (gpmi) 5-36xx-d1-1.02-050306 gpmi xml revision: 1.43 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 361 14. hardware ecc acc elerator (hwecc) this chapter describes the dma-based ha rdware ecc accelerator (hwecc) avail- able on the STMP36XX. it provides detailed descriptions of how to use the reed- solomon ecc accelerator. programmable registers are described in section 14.4 . 14.1. overview the hardware ecc accelerator provides a forward error-corr ection function for improving the reliability of various storage media that can be attached to the STMP36XX. modern high-density nand flas h devices, for example, presume the existence of forward error-co rrection algorithms, because permitting some soft or hard bit errors within the flash device allows a much higher yield and therefore lower-cost storage devices. the hardware ecc block is comprised of a robust algorithm for multi-bit error cor- rection using reed-solomon block codes. having a dma-based hardware accelera- tor for this function allows the cpu to focus on signal processing for enhanced functionality and to operate at lower clock frequencies and voltages for improved battery life. the cpu is not directly involved in generated parity symbols or checking for the errors. the hardware ecc accelerator is illustrated in figure 49 . flash ecc programmable registers reed-solomon ecc engine syndrome calculation key equation solver chien search forney evaluator 1-bit hamming encoder 1-bit hamming decoder ahb-to-apbh dma ahb slave apbh master ahb master ahb apbh ahb-to-apbh bridge vector interrupt ctlr interrupt vector ssfdc hamming ecc engine (deprecated) figure 49. hardware ecc accelerator block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 362 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 14.2. reed-solomon ecc accelerator the reed-solomon algorithm is capable of correcting up to 4 9-bit symbols in a 512- byte block. thus, up to 36 bits in error can be corrected in a 512-byte block, pro- vided they are clustered within no more than 4 9-bit symbols. this algorithm gener- ates 9 bytes (8 symbols) of error code or parity (sometimes called syndromes) per 512-byte block. the parity bytes are stored in the spare area at the end of each nand flash page. to understand how the reed-solomon algorithm is implemented on the STMP36XX, consider the case where there is a 512-byte data block located in the on-chip ram that needs to be written to a nand fl ash device. further, assume that a 9-byte reed-solomon parity field is to be written into the 16-byte spare area of the 528-byte nand flash page. assume that th e gpmi media interface is used to write the resultant 521 bytes of data and parity from on-chip memory to the nand flash device. ? channel commands in apbh dma channel 0 are used to point to the data block in either on-chip or off-chip ram (as shown in figure 50 ). ? the reed-solomon (rs) algorithm uses 9-bit symbols. thus, a 512-byte data block encompasses 455 1/9 symbols. ? as the data is read from on-chip ram, the hardware appends 47 8/9 zero-pad symbols to form the basic 511-symbol rs block. ? this block is treated as a large polynomi al and is divided by the hardware using the mathematics of galois fields 1 . ? the hardware retains the 8-symbol (72 bits or 9 bytes) remainder from this division, which it then stores as the pa rity for the block. channel command words in the same apbh dma channel (0) are us ed to store the parity into on-chip ram. ? the gpmi dma can then be started to copy the 521 bytes to the nand flash device. of course, both units can be fully overlapped. it is likely that ecc is to be calculated on more than 512 bytes, such as the case of mlc or ag-and. for those devices, it may be important to protect all metadata, which can be up to 7 additional bytes (page size is usually limited (physically or vir- tually) to 528 bytes. if 9 bytes are used for parity syndrome data, then there are 512 data plus 7 bytes of metadata available. it is not necessary for the data to be orde red as: data, metadata, parity. in fact, the decode error report requires that any corr ections be applied on 16-bit boundaries, so it makes sense to align the data and parity bytes on that boundary. while not required, it is suggested to place 512 bytes of data, then 9 bytes of parity data, and then the 7 bytes of metadata in a 528-byte page. the dma engine can use chained descriptors to read/write the data that way, making it seem like one continuous transfer. channel command word processing in the apbh dma allows the buffer to start on an arbitrary byte bounda ry within system memory. 1.oliver pretzel, ?error-correction codes and finite fields,? oxford univ. press, 1992 isbn 0-19-269067-1. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 363 utilizing the dma engine capa bilities, the dma command chain would point to the 512 bytes of data, then the additional 7 bytes of metadata at the end of the spare area, and then finally to the first 9 bytes of the spare area for storing the returned parity bytes. this is advantageous becau se the rs-ecc block does not correct the data in place (as with the stmp35xx), and the corrections returned are half-word (16-bit) aligned. placing the parity data at the end of the 528-byte data+spare area means copying, shifting, and masking is involved in correcting the data, whereas placing the parity bytes at the end of the data allows simpler error correction (if needed). 512-byte data area 528-byte nand flash page data 455 1 / 9 data symbols (9-bit) 16-byte spare area 47 8 / 9 zero pad symbols 8 parity symbols 511 symbol reed-solomon block code 503 symbol polynomial dividend pointed to by channel commands in apbh dma channel 0 galois field polynomial divider 8-parity symbol remainder 512 byte data area data 9-byte parity 16-byte spare area pointed to by channel commands in apbh dma channel 0 figure 50. hardware ecc reed-solomon block coding?encoder free datasheet http:/// STMP36XX official product documentation 5/3/06 364 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 14.2.1. reed-solomon encoding the rs encoder flowchart in figure 51 shows the detailed steps involved in pro- gramming and using the hardware ecc?s reed-solomon encoder. this flowchart shows how to use the hwecc block with the aphb dma, which is the normal oper- ating mode. to use the encoder with the dma: ? create a dma command chain with two co mmand structures on it (as shown in figure 52 ). the first command structure points to the 512-byte data block that is to be rs-encoded. the second points to a 12-byte (3-word) area to receive the computed parity. only 9 bytes will be written into this 12-byte buffer. stop flash rs ecc encode hw_apbh_ctrl_sftrst=0 hw_apbh_ctrl1_ch0_cmdcmplt_irq = 1 hw_apbh_ctrl1_ch0_cmdcmplt_irq_en = 1 set up channel command list for 2 commands, one for data block read and one for parity block write. hw_apbh_ch0_nxtcmdar = &first_channel_command return and wait for dma channel 0 command complete interrupt. loads first dma channel command, loads hw_hwecc_ctrl, kicks hwecc and starts all transfers and processing. this and the following reset must be done with an explicit apb pio operation before starting the dma. note: this is typically done only once per power up. apbh dma ch0 command complete isr hw_apbh_ctrl1_ch0_cmdcmplt_irq_en = 0 stop clear channel zero interrupt enable. hw_hwecc_ctrl_sftrst = 0 clear irq channel 0. set comamnd complete irq enable channel 0. figure 51. hardware ecc reed-solomon encode flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 365 ? to use the encoder, first turn off the module-wide soft reset bit before starting any dma activity. note that turning off the soft reset must take place by itself, prior to programming the rest of the control register. ? program the remainder of the desired hw_hwecc_ctrl register contents by modifying the first dma channel command structure. dma channel commands have the option to include a variable number of pio data transfers that occur before data dma transfers begin. in this case, the first channel command is initialized to transfer one word to the hwecc pio space before starting the data dma. dma pio transfers always begin at the device?s base address. thus, this command copies a 32-bit value from the end of the channel command structure to the hw_hwecc_ctrl register. set bits [1:0] of this channel command word to a value of 2, which will be lo aded into hw_h wecc_ctrl_ecc_sel, causing the device to operate in reed-solomon encode mode when the copy occurs. ? since the hardware ecc is a memo ry-to-memory dma device, its dma utilization is nominally limited only by the encoder?s dema nd for data. this natural limit may use too much dma bus bandwidth over its command time. as a result, the hw_hwecc_ctrl_dmawait_count bit field can specify additional wait cycles to insert between the dma cycle requests to reduce the hardware ecc?s short-term utilization. ? do not program the kick bit to one in the channel command word. the last thing the dma controller does after performing the pio copies and before waiting on dma requests from the hwecc is to set the kick bit via a specific hardware signal connecting the two blocks. (not e: the automatic kick from the dma engine to the hwecc block only occurs if there is pio done by the dma to the hwecc.) ? any previous command-complete interrupt status would have been cleared by writing a one to the interrupt bits? clear address prior to starting the dma channel command chain processing. software can then poll the dma command complete bit for channel 0, waiting for it to be se t to one. however, this typically takes hundreds of clock cycles. to get full ov erlap of the cpu, the gpmi, and the nextcmd_addr 512 buffer address hw_hwecc_ctrl= 0x01c80042 nextcmd_addr 9 buffer address 512-byte data block 9 bytes of parity at any byte alignment read write 1 pio,chain, dma read no chain, dma write 1 0 1 10 0 0 0 0 01 0 nextcmd_addr 4 buffer address 4 bytes of status write chain, dma write 1 0 0 0 01 figure 52. hardware ecc reed-solomon encode dma chain free datasheet http:/// STMP36XX official product documentation 5/3/06 366 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 hardware ecc module, use the aphb dma channel 0 command-complete interrupt, source bit hw_apbh_ctrl1:0. when this interrupt is received, the gpmi block can be scheduled to write the entire page to the nand hardware device the ?footprint? of the rs parity bits in system memory is shown in table 496 . this footprint is for the case where the dma buffer address is 32-bit word-aligned. note that the other three starting byte alignm ents are supported by the dma channel, as well. the byte aligner built into the shared dma aligns them so that the data copied from the hw_hwecc_data register by the dma is always 32-bit word-aligned, even though the system memory footprint may not be 32-bit word-aligned (see table 497 ). 14.2.2. reed-solomon decoding when a page is read from nand flash, its rs parity must be checked and if correct- able errors are found, they must be corr ected. this decoding process can also be fully overlapped with cpu executio n. the rs decoder flowchart in figure 53 shows the steps involved in programming the hardware ecc?s reed-solomon decoder, and figure 54 summarizes the process. table 496. hw_ecc reed-solomon parity bytes in system memory 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 all_ones all_zeroes set to zero by the encoder rs_parity3 rs_parity2 r s_parity1 rs_parity0 rs_parity7 rs_parity6 r s_parity5 rs_parity4 unused and unwritten rs_parity8 table 497. hw_ecc reed-solomon parity bytes, unaligned in system memory 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unused and unwritten all_ones all_zeroes set to zero by the encoder rs_parity2 rs_parity1 rs_parity0 s et to zero by the encoder rs_parity6 rs_parity5 r s_parity4 rs_parity3 unused and unwritten rs_parity8 rs_parity7 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 367 either of bits 28:29 set? stop flash rs ecc decode hw_apbh_ctrl0_sftrst=0 hw_apbh_ctrl1_ch0_cmdcmplt_irq = 1 hw_apbh_ctrl1_ch0_cmdcmplt_irq_en = 1 set up channel command list for 3 commands, one for data block read, one for parity block read, and finally a write command for the nine-word parity report. hw_apbh_ch0_nxtcmdar = &first_channel_command return and wait for dma channel 0 command complete interrupt. loads first dma channel command, loads hw_hwecc_ctrl_ecc_sel, kicks hwecc and starts all transfers and processing. this and the following apbh sftrst clear must be done with an explicit apb pio operation before starting the dma. note: this is typically done only once per power-up. apbh dma ch0 command complete isr hw_apbh_ctrl1_ch0_cmdcmplt_irq_en = 0 stop clear channel zero interrupt enable. hw_hwecc_ctrl_sftrst = 0 clear irq channel 0 (using sct). set command complete irq enable channel 0. read the first error report word. yes no process error report stop figure 53. hardware ecc reed-solomon decode flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 368 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 conceptually, an aphb dma channel 0 command chain with three (or more) com- mand structures linked together is used to perform the rs decode operation (as shown in figure 55 ). ? notice that in this case, the first tw o dma command structures point into the either on-chip or off-chip ram buffer where bytes were read from the nand flash device, i.e., the data block and the parity block. ? the decoder is initialized to read the data block, append the zero pad, and perform the polynomial division, this time with the supplied parity bytes. ? if the resulting division yields a zero remainder, then no errors are present and the hardware ecc block can immediately report back to firmware. ? if the remainder was non-zero, then it further examines the syndrome bytes to determine which bits must be corrected within the data block or parity block, if possible (not all errors are correctable). ? the third apbh dma command structure is used to write an error report structure into system memory. this error report structure includes error summary information, as well information on exac tly how firmware can correct the error. 512-byte data area 528-byte nand flash page data 9-byte parity 455 1 / 9 data symbols (9-bit) 16-byte spare area 47 8 / 9 zero pad symbols 8 parity symbols 511 symbol reed-solomon block code 503 symbol polynomial dividend pointed to by first apbh dma channel 0 command structure pointed to by second aphb dma channel 0 command structure galois field polynomial divider 9-word error report buffer == 0? y n 8 syndromes pointed to by third aphb dma channel 0 command structure 8 parity symbol remainder ok error (compute correction) figure 54. hardware ecc reed-solomon block coding?decoder phase 1 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 369 unlike its predecessor, the STMP36XX does not automatically correct bit errors found by the reed-solomon. instead it supplies up to eight pairs of index and mask values that can be used to correct the data and/or parity blocks (see table 498 ). ? the indices should be treated as applying to one of two spaces: the data space (where the msb of the index is set to zero ) or the parity space (where the msb of the index is set to one). ? for optimum performance, these arrays must be half-word (16-bit aligned). ? positive indices indicate th at the error is in the data block, and negative indices indicate an error in the parity block. ? to correct an error, the index sign bit is checked. if positive, an unsigned short reference into the data block is formed, and the half-word at that location is xored with the mask value corresponding to the index used. ? when an index/mask pair has no error to repair, then both half-words are written as zeroes by the hardware. note: the hwecc always writes all nine 32-bit words of the error report in rs mode whether an error is detected or not. thus, one can chain the dma command structures for a large number of data bloc ks together and let the hwecc work on a whole 2048 or 4096 (or more) byte page at once. when the dma command com- plete interrupt arrives, firmware can then check the error correction state for each block. this allows large units of work to be scheduled without the need for frequent cpu interrupts. also note that if there are corrections to be made, the index values are 1-based, so software must subtract one from them before applying the mask value. 512-byte data block 9 bytes of parity at any byte alignment read write nextcmd_addr 512 buffer address hw_hwecc_ctrl= 0x01c80043 nextcmd_addr 9 buffer address nextcmd_addr=0 36 buffer address 1 result word plus 8 correction words read 10 0 1 1 0 01 1 0 0 0 10 0 0 1 0 interrupt on done, no chain, write chain, read chain, read figure 55. hardware ecc reed-s olomon block decode dma chain free datasheet http:/// STMP36XX official product documentation 5/3/06 370 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 one recommended organization for the error report dma command structure is as follows: struct { dmacmdstruc * pnextcommand; unsigned long xfersizeword; unsigned short * pbuffer; // point to next word unsigned long errorreportstatus struct { short index; // use plus or minus to select data or parity block unsigned short mask; //if mask is zero then no error for this index } report[8]; } errorreportdmacommand as firmware walks the dma chain to check ecc results for multiple blocks in a com- mand transaction, it can quickly examine the error bit in the msb of the first word to determine if further corrective action is required. for the anticipated nand flash error rates, corrective action w ill not be required for most blocks. if corrective action is indicated, then the uncorr bit should next be checked; if it is set, no corrective action can be reliably pe rformed for the block. if there are errors that are correctable, then firmware should examine each index/mask pair and perform the indicated xor operations. there are never more than eight index/mask pairs generated by th e hwecc in reed-solomon mode. as the rs decoder reads the data block and the 9-byte parity block, it records either of two special conditions, i.e., that all of the bits are one or that all of the bits are zero. the all-ones case for both parity and data indicates an erased page in the nand device. table 498. hw_ecc reed-solomon decode r error report buffer in system memory 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 all_ones all_zeroes error uncorr reserved, reads zeroes ecc exception reserved, reads zero number of bits in error number of symbols in errors index[0] mask[0] index[1] mask[1] index[2] mask[2] index[3] mask[3] index[4] mask[4] index[5] mask[5] index[6] mask[6] index[7] mask[7] free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 371 to summarize, the apbh dma command chain for a reed-solomon decode opera- tion is shown in figure 55 . three dma command structures must be present for each block decoded by the hwecc. the three dma command structures for multi- ple data/parity blocks can be chained together to make larger units of work for the hwecc, and each will produce an appropriate erro r report structure. the rs decoder processes the 511-symbol block code in three phases. all phases may not be necessary, for example when no errors are found or when uncorrectable errors are found. t he three phases are: 1. syndrome calculation phase (sc) ?this is the process of reading in all of the symbols of the block and continuously dividing by the generator polynomial for the field. the eight syndromes are calculated as the remainder of this division and must be examined, as described above. this phase takes approximately 700 cycles for a 512-byte data block, with no planned dma wait states added. 2. key equation solver phase (kes) ?once the eight syndromes have been calculated, a set of eight linear equations in eight unknowns is formed. the pro- cess of solving these equations and selecting from the numerous possible solu- tions constitutes the kes phase. the part ial solution is obtained by dividing a polynomial based on the syndromes by a euclidian polynomial. this division, again using the mathematics of galois fi elds, yields two polynomials, the error evaluator (ee) polynomial and the error locator (el) polynomial. the ee poly- nomial is the remainder of this division and is zero if an uncorrectable (non-solv- able) case exists. the hardware terminates with an uncorrectable error in this case. this phase takes up to 560 hclks, with no planned dma wait states added. 3. chien search and forney evaluator phase (eval) ?this phase takes the ee and el polynomials from the kes pha se and uses chien?s algorithm for finding the locations of the errors based on the ee polynomial. the method basically involves substituting all 512 9-bit symbols into the ee polynomial. all non-zero results of these substitutions represent the locations of the various errors. another gf division is performe d at this point to determine the error value or the correction to apply at the symbol in error location. this phase con- sumes approximately 550 hclks, with no planned dma wait states added. the eval phase terminates either with an uncorrectable error interrupt or simply a ?done? interrupt. done is reported in either case. if uncorrectable errors occurred, it is up to software to determine how to deal with a bad block. one strategy might be to reread the data from nand flash in the hope that enough soft errors will have been removed to make correction successful on a second pass. 14.2.3. reed-solomon decoding using pio debug mode the block is connected only as a pio devic e to the apbh bus. even though it is designed to work with the dma controller integrated in the apbh bridge, all trans- fers to and from the block are programme d i/o (pio) read or write cycles. when the dma is ready to write to the hw_hwecc_data register, it does so with standard apb write cycles. when it is ready to re ad from the hw_hwecc_data register, it does so with standard apb read cycles. there are four dma-related signals that connect the hwecc to the dma, but all data transfers are standard pio cycles on the apb. the state of these four signals can be seen in the hw_hwecc_debug0 register. free datasheet http:/// STMP36XX official product documentation 5/3/06 372 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 thus, is it is possible to completely exercise the hwecc block for diagnostic pur- poses, using only load and store instructions from the cpu, without ever starting the dma controller. this section describes how to interact with the block using pio operations and also defines the block?s detailed behavior. whenever the hw_hwecc_ctrl register is written either by the cpu or the dma, it establishes the basic operation mode for the block, e.g., rs encode or rs decode. refer to the hw_hwecc_ct rl_ecc_sel bit field. if the hw_hwecc_ctrl register is written with a one in the kick bit, then the operation begins and the hwecc attempts to read the data block by toggling its pdmareq signal to the dma. notice that the pdmareq and pencmd signals are defined as toggle signals. they change state to si gnify either a request for another dma word or a notification that the current comma nd transfer is ended by the hwecc. diag- nostic software should poll these si gnals to determine when the hwecc is ready for another dma write and can then supply the data by storing a 32-bit word to the hw_hwecc_data register, just as the dma would do in normal operation. to perform a reed-solomon decode using pio debug mode (for 512-byte data block size), diagnostic softwa re would perform the following: 1. turn off the soft reset bit, hw_hwecc_ctrl_sftrst. 2. write a value of 0x01c80043 to hw _hwecc_ctrl, selecting rs decode mode. 3. set hw_hwecc_ctrl_run to one to simulate a dma kick 4. wait for hw_hwecc_debug0_dma_r equest status bit to toggle. 5. write four bytes of the data block data to the hw_hwecc_data register. 6. repeat steps 3, 4, and 5 until 512 bytes have been written to hw_hwecc_data, four at a time. 7. wait for hw_hwecc_debug0_dma_r equest status bit to toggle. 8. write four bytes of the parity block data to the hw_hwecc_data register. 9. repeat steps 6, 7, and 8 until all 9 bytes of parity have been written. 10. wait for hw_hwecc_debug0 _dma_request to toggle. 11. read the first error report word from hw_hwecc_data. 12. repeat steps 10, 11, and 12 until all nine words of the error report have been read. 13. write a zero to the hw_hwecc_ctrl_run bit and the operation is now com- plete. for debug purposes, the hwecc makes certain intermediate results available such as the syndrome calculation results or the key equation solver results. these inter- mediate variables are available for debug purposes in hw_hwecc_debugx. 14.3. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 373 14.4. programmable registers the following registers are available for pr ogrammer access and control of the hard- ware ecc accelerator. 14.4.1. hardware ecc accelerator control register description the hardware ecc accelerator control register provides overall control of the hardware ecc accelerator. hw_hwecc_ctrl 0x80008000 hw_hwecc_ctrl_set 0x80008004 hw_hwecc_ctrl_clr 0x80008008 hw_hwecc_ctrl_tog 0x8000800c table 499. hw_hwecc_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsrvd4 num_symbols rsrvd3 dmawait_count rsrvd2 byte_enable ecc_sel enc_sel rsrvd1 uncorr_irq uncorr_irq_en run table 500. hw_hwecc_ctrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 set this bit to zero to enable normal hwecc operation. set this bit to one (default) to disable clocking with the hwecc and hold it in its reset (lowest power) state. this bit can be turned on and then off to reset the hwecc block to its default state. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. 29:25 rsrvd4 ro 0x0 reserved, always set these bits to zero. 24:16 num_symbols rw 0x1c8 number of rs symbols (9-bits/symbol) to encode/decode. the maximum data-block size for rs is 503 symbols. 8 parity symbols are appended to generate an rs-codeword of 511 symbols. 0x1c8 represents a 512-byte data block. 0x1ce represents a 519-byte data block. 15:13 rsrvd3 ro 0x0 reserved, always set this bits to zero. 12:8 dmawait_count rw 0x0 this bit field specifies the number of hclks to insert before requesting a dma transfer. a value of 2 causes the hwecc state machine to delay two clocks after it is ready to request to a dm a cycle until it toggles the pdmareq line. this field acts as a throttle on the bandwidth consumed by the hwecc block. this field can be loaded by the dma. 7 rsrvd2 ro 0x0 reserved, always set this bit to zero. free datasheet http:/// STMP36XX official product documentation 5/3/06 374 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 description: the hwecc accelerator control register is used to select the specific type of operation to be performed by the hw ecc, e.g., reed-solomon decode. once kicked off by the dma, the selected command processes data supplied by the dma in a specific order, i.e., data block read, parity block read, followed by writing the error correction result block. this register contains bit fields that throttle the dma request rate and other bit fields that cont rol various debug modes. it also contains the overall soft reset bit. this bit is set to one at reset and must be turned off before any other bit fields are set and before an y dma operations commence. note: this is typically done once per power-up. example: hw_hwecc_ctrl.u = 0x00000000; // turn off the soft reset bit before starting dma transfers // all other bit fields are set by the first dma command 14.4.2. hardware ecc accelerator status register description the hardware ecc accelerator status regist er provides overall status of the hard- ware ecc accelerator. hw_hwecc_stat 0x80008010 hw_hwecc_stat_set 0x80008014 6 byte_enable rw 0x0 when ecc_select = 0 (rs-mode), this bit must be set if num_symbols does not exactly cover the desired number of bytes (i.e., num_syms * 9 / 8 != 0). this will force the hwecc to mask the byte adjacent to the last byte intended to be included in the data- block. (note: should be set to 1 for 512- or 519-byte blocks) 5 ecc_sel rw 0x0 the ecc select field determines the operation to be carried out by the hwecc block. 0= hw_ecc_rs 1= hw_ecc_ssfdc (deprecated) this field can be loaded by the dma. 4 enc_sel rw 0x0 determines whether to perform an encode or decode for the correction algorithm specified in ecc_sel. 0=encode. 1=decode 3 rsrvd1 ro 0x0 reserved, always set this bit to zero. 2 uncorr_irq rw 0x0 uncorrectable error interrupt request. an uncorrectable error has been detected. consult debug0 for further information as to the cause. 1 uncorr_irq_en rw 0x0 set this bit to enable uncorr_irq. 0 run rw 0x0 for debug purposes, the hwecc can be kicked off by setting this bit to one. in this mode, software diagnostics can simulate the operation of the dma by reading and writing the appropriate number of words from the dma read and writ e registers. in normal operation, the hwecc is kicked off after the last setup pio cycle of a dma command. table 500. hw_hwecc_ctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 375 hw_hwecc_stat_clr 0x80008018 hw_hwecc_stat_tog 0x8000801c description: the hwecc stat register provides visibility into t he run-time status of the hwecc. the register also reflects the hw ecc configurations supported in this ver- sion of the STMP36XX. example: hw_hwecc_stat.u = 0x00000000; 14.4.3. hardware ecc accelerator debug register 0 description the hardware ecc accelerator internal state machines and signals can be seen in this ecc debug register. hw_hwecc_debug0 0x80008020 hw_hwecc_debug0_set 0x80008024 hw_hwecc_debug0_clr 0x80008028 hw_hwecc_debug0_tog 0x8000802c table 501. hw_hwecc_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsdec_present rsenc_present ssdec_present ssenc_present rsrvd3 table 502. hw_hwecc_stat bit field descriptions bits label rw reset definition 31 rsdec_present ro 0x0 0= reed-solomon decode error correction encoding and decoding is not supported in this product. 30 rsenc_present ro 0x0 0= reed-solomon encode error correction encoding and decoding is not supported in this product. 29 ssdec_present ro 0x1 0= deprecated ssfdc-decode error correction encoding and decoding is supported in this product. 28 ssenc_present ro 0x1 0= deprecated ssfdc-encode error correction encoding and decoding is not supported in this product. 27:0 rsrvd3 ro 0x0 reserved, always set these bits to zero. free datasheet http:/// STMP36XX official product documentation 5/3/06 376 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 table 503. hw_hwecc_debug0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 dma_pendcmd dma_preq symbol_state rsrvd3 ctrl_state ecc_exception rsrvd2 num_bit_errors rsrvd1 num_symbol_errors table 504. hw_hwecc_debug 0 bit field descriptions bits label rw reset definition 31:30 rsrvd4 ro 0x0 reserved, always set these bits to zero. 29 dma_pendcmd ro 0x0 this read-only field indicates the state of the dma end command signal as it is sent from the hwecc to the dma. 28 dma_preq ro 0x0 this read-only field indicates the state of the dma request command signal as it is sent from the hwecc to the dma. 27:24 symbol_state ro 0x0 a copy of the hwecc symbol state-machine bits are visible in this register for diagnostic and validation purposes. 23:22 rsrvd3 ro 0x0 reserved, always set these bits to zero. 21:16 ctrl_state ro 0x0 a copy of the hwecc control state-machine bits are visible in this register for diagnostic and validation purposes. 15:12 ecc_exception ro 0x0 this read-only field indicates the reason for termination of the most recent operation. 0000= no exception 0001= rs, degree of lambda exceeds 4 0010= rs, lambda is all zeroes 0100= rs, degree of lambda not equal number of roots or lambda, i.e duplicate roots 1000= ssfdc, more than one error (deprecated) this information is stored as part of the error correction result block. 11:10 rsrvd2 ro 0x0 reserved, always set these bits to zero. 9:4 num_bit_errors ro 0x0 this read-only field indicates the number of bit errors detected and/or corrected. refer to the ecc_exception field for detailed information about uncorrectable errors. this information is stored as part of the error correct ion result block. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 377 description: the hw_hwecc_debug0 register provid es access to various internal state information which might prove useful during hardware debug and validation. example: value = hw_hwecc_debug0.u; // diagnostic programs can read and act upon various bit fields. 14.4.4. hardware ecc accelerator debug register 1 description the hardware ecc accelerator internal state machines and signals can be seen in this ecc debug register. hw_hwecc_debug1 0x80008030 hw_hwecc_debug1_set 0x80008034 hw_hwecc_debug1_clr 0x80008038 hw_hwecc_debug1_tog 0x8000803c description: the hw_hwecc_debug1 register provid es access to various internal state information that might prove useful during hardware debug and validation. example: value = hw_hwecc_debug1.u; // diagnostic programs can read and act upon various bit fields. 3 rsrvd1 ro 0x0 reserved, always set these bits to zero. 2:0 num_symbol_errors ro 0x0 this read-only field indicates the number of symbol errors detected and/or corrected. refer to the ecc_exception field for detailed information about uncorrectable errors. this information is stored as part of the error correct ion result block. table 505. hw_hwecc_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 syndrome2 syndrome1 syndrome0 table 506. hw_hwecc_debug 1 bit field descriptions bits label rw reset definition 31:27 rsrvd1 ro 0x00 reserved, always set these bits to zero. 26:18 syndrome2 ro 0x000 syndromes visible for debug 17:9 syndrome1 ro 0x0000 syndromes visible for debug 8:0 syndrome0 ro 0x0000 syndromes visible for debug table 504. hw_hwecc_debug 0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 378 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 14.4.5. hardware ecc accelerator debug register 2 description the hardware ecc accelerator internal state machines and signals can be seen in this ecc debug register. hw_hwecc_debug2 0x80008040 hw_hwecc_debug2_set 0x80008044 hw_hwecc_debug2_clr 0x80008048 hw_hwecc_debug2_tog 0x8000804c description: the hw_hwecc_debug2 register provid es access to various internal state information that might prove useful during hardware debug and validation. example: value = hw_hwecc_debug2.u; // diagnostic programs can read and act upon various bit fields. 14.4.6. hardware ecc accelerator debug register 3 description the hardware ecc accelerator internal state machines and signals can be seen in this ecc debug register. hw_hwecc_debug3 0x80008050 hw_hwecc_debug3_set 0x80008054 hw_hwecc_debug3_clr 0x80008058 hw_hwecc_debug3_tog 0x8000805c table 507. hw_hwecc_debug2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 syndrome5 syndrome4 syndrome3 table 508. hw_hwecc_debug 2 bit field descriptions bits label rw reset definition 31:27 rsrvd1 ro 0x00 reserved, always set these bits to zero. 26:18 syndrome5 ro 0x000 syndromes visible for debug 17:9 syndrome4 ro 0x0000 syndromes visible for debug 8:0 syndrome3 ro 0x0000 syndromes visible for debug free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 379 description: the hw_hwecc_debug3 register provid es access to various internal state information that might prove useful during hardware debug and validation. example: value = hw_hwecc_debug3.u; // diagnostic programs can read and act upon various bit fields. 14.4.7. hardware ecc accelerator debug register 4 description the hardware ecc accelerator internal state machines and signals can be seen in this ecc debug register. hw_hwecc_debug4 0x80008060 hw_hwecc_debug4_set 0x80008064 hw_hwecc_debug4_clr 0x80008068 hw_hwecc_debug4_tog 0x8000806c table 509. hw_hwecc_debug3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 omega0 syndrome7 syndrome6 table 510. hw_hwecc_debug 3 bit field descriptions bits label rw reset definition 31:27 rsrvd1 ro 0x00 reserved, always set these bits to zero. 26:18 omega0 ro 0x000 kes polynomials visible for debug 17:9 syndrome7 ro 0x0000 syndromes visible for debug 8:0 syndrome6 ro 0x0000 syndromes visible for debug table 511. hw_hwecc_debug4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 omega3 omega2 omega1 table 512. hw_hwecc_debug 4 bit field descriptions bits label rw reset definition 31:27 rsrvd1 ro 0x00 reserved, always set these bits to zero. 26:18 omega3 ro 0x000 kes polynomials visible for debug free datasheet http:/// STMP36XX official product documentation 5/3/06 380 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 description: the hw_hwecc_debug4 register provid es access to various internal state information that might prove useful during hardware debug and validation. example: value = hw_hwecc_debug4.u; // diagnostic programs can read and act upon various bit fields. 14.4.8. hardware ecc accelerator debug register 5 description the hardware ecc accelerator internal state machines and signals can be seen in this ecc debug register. hw_hwecc_debug5 0x80008070 hw_hwecc_debug5_set 0x80008074 hw_hwecc_debug5_clr 0x80008078 hw_hwecc_debug5_tog 0x8000807c description: the hw_hwecc_debug5 register provid es access to various internal state information that might prove useful during hardware debug and validation. example: value = hw_hwecc_debug5.u; // diagnostic programs can read and act upon various bit fields. 14.4.9. hardware ecc accelerator debug register 6 description the hardware ecc accelerator internal state machines and signals can be seen in this ecc debug register. hw_hwecc_debug6 0x80008080 17:9 omega2 ro 0x0000 kes polynomials visible for debug 8:0 omega1 ro 0x0000 kes polynomials visible for debug table 513. hw_hwecc_debug5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 lambda2 lambda1 lambda0 table 514. hw_hwecc_debug 5 bit field descriptions bits label rw reset definition 31:27 rsrvd1 ro 0x00 reserved, always set these bits to zero. 26:18 lambda2 ro 0x000 kes polynomials visible for debug 17:9 lambda1 ro 0x0000 kes polynomials visible for debug 8:0 lambda0 ro 0x0000 kes polynomials visible for debug table 512. hw_hwecc_debug 4 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 14: hardware ecc accelerator (hwecc) 381 hw_hwecc_debug6_set 0x80008084 hw_hwecc_debug6_clr 0x80008088 hw_hwecc_debug6_tog 0x8000808c description: the hw_hwecc_debug6 register provid es access to various internal state information that might prove useful during hardware debug and validation. example: value = hw_hwecc_debug6.u; // diagnostic programs can read and act upon various bit fields. 14.4.10. hardware ecc accelerator dma read/write data register description the hardware ecc accelerator transfers data to and from memory using the dma integrated into the ahb-to -apbh bridge. the dma moves write data to the hard- ware ecc accelerator using standard apb write cycles targeted at the hw_hwecc_data register. hw_hwecc_data 0x80008090 hw_hwecc_data_set 0x80008094 hw_hwecc_data_clr 0x80008098 hw_hwecc_data_tog 0x8000809c description: table 515. hw_hwecc_debug6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 lambda4 lambda3 table 516. hw_hwecc_debug 6 bit field descriptions bits label rw reset definition 31:18 rsrvd1 ro 0x00 reserved, always set these bits to zero. 17:9 lambda4 ro 0x0000 syndromes visible for debug 8:0 lambda3 ro 0x0000 syndromes visible for debug table 517. hw_hwecc_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 data table 518. hw_hwecc_data bit field descriptions bits label rw reset definition 31:0 data rw 0x00000000 data written to this pio address are used by the hwecc as the data block or the parity block. free datasheet http:/// STMP36XX official product documentation 5/3/06 382 chapter 14: hardware ecc accelerator (hwecc) 5-36xx-d1-1.02-050306 in normal operation, the dma writes to this pio address as it reads the data block or the parity block. it writes (typically) 128 words (512 bytes) of data block informa- tion in rs mode. after writing the data bloc k information to this register, it writes 9 bytes of parity information in 3 four byte words in rs mode. note that the data block and parity block information can be supplied from two independent dma commands and can therefore come from two indep endent buffers in system memory. once encoding or decoding is co mpleted, the dma will read fr om this buffer the parity report or decode report, respectively. example: hw_hwecc_data.u = 0x12345678; // diagnostic software can write to this register in place of the dma hwecc xml revision: 1.40 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 383 15. synchronous seri al port (ssp) this chapter describes th e synchronous serial port (ssp) included on the STMP36XX. it includes sections on external pins, bit rate generation, frame formats, motorola spi mode, texas instruments synchronous serial interface (ssi) mode, national semiconductor microwire mode, sd/sdio/mmc mode, and ms mode. programmable registers are described in section 15.11 . 15.1. overview the synchronous serial port is a flexible interface for inter-ic and removable media control and communication. the ssp suppor ts master operation of spi, texas instruments ssi, national semiconductor microwire, 1-bit and 4-bit sd/sdio/mmc, and ms modes. the spi mode has enhancements to support 1-bit legacy mmc cards. the ssp also supports slave op eration for the spi, ssi, and microwire modes. the ssp has a dedicat ed dma channel in the bri dge and can also be con- trolled directly by the cpu through pio registers. figure 56 shows a block diagram of the ssp port included on the STMP36XX. apbh dma controller ahb slave apbh master ahb master ahb ahb-to-apbh bridge arm core sram spi ti ssi 4-bit sd/sdio/mmc modes microwire ms system clock generator hclk sspclk ssp/gpio pin mux gpio pins synchronous serial port dma request figure 56. synchronous serial port block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 384 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 15.2. external pins table 519 lists the ssp pin placements for all supported modes. 15.3. bit rate generation the serial bit rate is derived by dividing down the internal clock sspclk. the clock is first divided by an even prescale valu e, cpsdvsr from 2 to 254, which is pro- grammed in sspcpsr. the clock is further di vided by a value from 1 to 256, which is 1 + scr, where scr is the value programmed in sspcr0. the frequency of the outp ut signal bit clock ssp_sc k is defined as follows: for example, if sspclk is 3.6864 mh z, and cpsdvsr=2, then ssp_sck has a frequency range from 7.2 khz to 1.8432 mhz. see chapter 4 , ?clock generation and control? on page 47 , for more clock details. 15.4. frame format for spi, ssi, and microwire each data frame is between 4 and 16 bits long, depending on the size of data pro- grammed, and is transmitted starting with the msb. there are three basic frame types that can be selected: ? motorola spi ? texas instruments synchro nous serial interface (ssi) ? national semiconductor microwire for all three formats, the serial clock ( ssp_sck) is held inactive while the ssp is idle and transitions at the programmed fr equency only during active transmissions or reception of data. the idle state of ssp_ sck is used to provide a receive timeout indication, which occurs when the receive fifo still cont ains data after a timeout period. for motorola spi and national semiconductor microwire frame formats, the serial frame (ssn) pin is active low and is assert ed (pulled down) during the entire trans- mission of the frame. table 519. ssp pin matrix pin name spi mode ti ssi mode microwire mode 4-bit sd/sdio/mmc mode ms mode ssp_sck sck clk clk clk clk ssp_cmd mosi mosi mosi cmd sdio ssp_data0 miso miso miso data0 ssp_data1 data1/irq bs ssp_data2 data2 ssp_data3 ssn ssn ssn data3 ssp_detect clockdivide * (1+clock_rate) ssp_sck= sspclk free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 385 for texas instruments synchronous serial interface (ssi) frame format, the ssn pin is pulsed for one serial clock period starting at its rising edge, prior to the transmis- sion of each frame. for this frame form at, both the ssp and the off-chip slave device drive their output on data on th e rising edge of ssp_sck, and latch data from the other device on the falling edge. unlike the full-duplex transmission of the other two frame formats, the national semiconductor microwire format uses a sp ecial master-slave messaging technique, which operates at half-duplex. in this mo de, when a frame begins, an 8-bit control message is transmitted to the off-chip sl ave. during this transmit, no incoming data is received by the ssp. after the message has been sent, the off-chip slave decodes it and, after waiting one serial clock cycle after the last bit of the 8-bit control mes- sage has been sent, responds with the required data. the returned data can be from 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 15.5. motorola spi mode the spi mode is used for general inter-co mponent communication and legacy 1-bit mmc cards. 15.5.1. spi dma mode the spi bus is inherently a full-duplex bidirectional interface. however, as most applications only require half-duplex data transmission, the STMP36XX has a single dma channel for the ssp. it can be configured for either transmit or receive. in dma receive mode, the spi continuously repeats the word written to its data register. in dma transmit mode, the spi ignores the incoming data. 15.5.2. motorola spi frame format the motorola spi inte rface is a four-wire interface where the ssn signal behaves as a slave select. the main feature of the motorola spi format is that the inactive state and phase of ssp_sck signal are programmable through the polarity and phase bits within the hw_ssp_ctrl1. 15.5.2.1. clock polarity ? when the clock polarity control bit is low, it produces a steady-state low value on the ssp_sck pin. ? when the clock polarity control bit is high, a steady-state high value is placed on the ssp_sck pin when data is not being transferred. 15.5.2.2. clock phase the phase control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit transmitted, by either allowing or not allowing a clock transition before the first data-capture edge. ? when the phase control bit is low, data is captured on the first clock-edge transition. ? when the clock phase control bit is high, data is captured on the second clock- edge transition. free datasheet http:/// STMP36XX official product documentation 5/3/06 386 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 15.5.3. motorola spi format with polarity=0, phase=0 single and continuous transmission signal sequences for motorola spi format with polarity=0, phase=0 are shown in figure 57 and figure 58 . in this configuration, during idle periods: ? the ssp_sck signal is forced low. ? ssn is forced high. ? the transmit data line mosi is arbitrarily forced low. ? when the ssp is configured as a master, ssp_sck is an output. ? when the ssp is configured as a slave, ssp_sck is an input. if the ssp is enabled and there is valid data within the transmit fifo, the start of the transmission is signified by the ssn master signal being low. this causes slave data to be enabled onto the miso input line of the master, and the enables the master mosi output pad. one half ssp_sck period later, valid master data is transferred to the mosi pin. now that both the master and slave data have been set, the ssp_sck master clock pin goes high after one fu rther half ssp_sck period. the data is now captured on the rising and propagated on the falling edges of the ssp_sck signal. figure 57. motorola spi frame format (sin gle transfer) with polarity=0 and phase=0 ssp_sck ssn miso mosi figure 58. motorola spi fram e format (continuous transfer) with polarity=0 and phase=0 ssp_sck ssn mosi/miso free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 387 in the case of a single word transmission, after all bits of the data word have been transferred, the ssn line is returned to its idle high st ate one ssp_sck period after the last bit has been captured. however, in the case of continuous ba ck-to-back transmissions, the ssn signal must be pulsed high between each data word transfer. this is because the slave select pin freezes the data in its serial pe ripheral register and does not allow it to be altered if the phase bit is logic zero. ther efore, the master de vice must raise the ssn pin of the slave device between each data transfer to enable the serial periph- eral data write. on completion of the cont inuous transfer, the ssn pin is returned to its idle state one ssp_sck period after the last bit has been captured. 15.5.4. motorola spi format with polarity=0, phase=1 the transfer signal sequence for motorola spi format with polarity=0 and phase=1 is shown in figure 59 , which covers both single and continuous transfers. in this configuration, during idle periods: ? the ssp_sck signal is forced low. ? ssn is forced high. ? the transmit data line mosi is arbitrarily forced low. ? when the ssp is configured as a ma ster, the ssp_sck pad is an output. ? when the ssp is configured as a slave, the ssp_sck is an input. if the ssp is enabled and there is valid data within the transmit fifo, the start of the transmission is signified by the ssn master signal being low. after a further one half ssp_sck period, both master and slave valid data are enabled with a rising-edge transition. data is then captured on th e falling edges and propagated on the rising edges of the ssp_sck signal. in the case of a single word transfer, after all bits have been transferred, the ssn line is returned to its idle high state one ssp_sck period after the last bit has been captured. for continuous back-to-back transfers, the sspfsout pi n is held low between suc- cessive data words and termination is the same as that of a single word transfer. figure 59. motorola spi fram e format (continuous transfer) with polarity=0 and phase=1 ssp_sck ssn miso mosi free datasheet http:/// STMP36XX official product documentation 5/3/06 388 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 15.5.5. motorola spi format with polarity=1, phase=0 single and continuous transmission signal sequences for motorola spi format with polarity=1 and ph ase=0 are shown in figure 60 and figure 61 . note: in figure 60 , q is an undefined signal. l in this configuration, during idle periods: ? the ssp_sck signal is forced high. ? ssn is forced high. ? the transmit data line mosi is arbitrarily forced low. ? when the ssp is configured as a ma ster, the ssp_sck pad is an output. ? when the ssp is configured as a slave, the ssp_sck is an input. if the ssp is enabled and there is valid da ta within the transmit fifo, the start of transmission is signified by the ssn mast er signal being driven low, which causes slave data to be immediately transferred onto the miso line of the master, and enabling the master mosi output pad. one half-period later, valid master data is transferred to the mosi line. now that both master and slave data have be en set, the ssp_sck master clock pin becomes low after one further half ssp_sck period. this means that data is cap- tured on the falling edges and propagated on the rising edges of the ssp_sck sig- nal. figure 60. motorola spi frame format (single transfer) with polarity=1 and phase=0 ssp_sck ssn miso mosi figure 61. motorola spi frame format (continuous transfer) with polarity=1 and phase=0 ssp_sck ssn mosi/miso free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 389 in the case of a single word transmission, after all bits of the data word are trans- ferred, the ssn line is returned to its idle high state one ssp_sck period after the last bit has been captured. however, in the case of continuous ba ck-to-back transmissions, the ssn signal must be pulsed high between each data word transfer. this is because the slave select pin freezes the data in its serial pe ripheral register and does not allow it to be altered if the phase bit is logic zero. ther efore, the master de vice must raise the sspsfssin pin of the slave device between ea ch data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssn pin is returned to its idle state one ssp_sck period after the la st bit has been captured. 15.5.6. motorola spi format with polarity=1, phase=1 the transfer signal sequence for motorola spi format with polarity=1 and phase=1 is shown in figure 62 , which covers both single and continuous transfers. note: in figure 62 , q is an undefined signal. in this configuration, during idle periods: ? the ssp_sck signal is forced high. ? ssn is forced high. ? the transmit data line mosi is arbitrarily forced low. ? when the ssp is configured as a ma ster, the ssp_sck pad is an output. ? when the ssp is configured as a slave, the ssp_sck is an input. if the ssp is enabled and there is valid da ta within the transmit fifo, the start of transmission is signified by the ssn mast er signal being driven low, and mosi out- put is enabled. after a further one-half ssp_ sck period, both master and slave are enabled onto their respective transmissi on lines. at the same time, the ssp_sck is enabled with a falling edge tr ansition. data is then capt ured on the rising edge and propagated on the falling edg es of the ssp_sck signal. after all bits have been transferred, in the case of a single word transmission, the ssn line is returned to its idle high st ate one ssp_sck period after the last bit has been captured. for continuous back-to-back transmissions, the ssn pin remains in its active low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. figure 62. motorola spi frame format with polarity=1 and phase=1 ssp_sck ssn miso mosi free datasheet http:/// STMP36XX official product documentation 5/3/06 390 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 for continuous back-to-back transfers, th e ssn pin is held low between successive data words and termination is the same as that of the single word transfer. 15.6. texas instruments synchronou s serial interf ace (ssi) mode figure 63 shows the texas instruments synchronous serial frame format for a single transmitted frame. in this mode, ssp_sck and ssn are forced low, and the transmit data line mosi is three-stated whenever the ssp is idle. on ce the bottom entry of the transmit fifo contains data, ssn is pulsed high for one ssp_sck period. th e value to be trans- mitted is also transferred from the transmit fifo to the serial shift register of the transmit logic. on the next rising edge of ssp_sck, the msb of the 4-to-16-bit data frame is shifted out on the ssprxd pin by the off-chip serial slave device. both the ssp and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each ssp_sck. the received data is transferred from the serial shifter to the receive fifo on the first rising edge of ssp_sck after the lsb has been latched. figure 64 shows the texas instrument synchrono us serial frame format when back- to-back frames are transmitted. figure 63. texas instruments synchronous serial frame format (single transfer) ssp_sck ssn mosi/miso free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 391 15.7. national semiconductor microwire mode figure 65 shows the national semiconductor microwire frame format, again for a single frame. figure 66 shows the same format when back-to-back frames are transmitted. microwire format is very similar to spi fo rmat, except that transmission is half- duplex instead of full-duplex, using a master-slave message passing technique. each serial transmission begins with an 8-bit control word th at is transmitted from the ssp to the off-chip slave device. during this transmission, no incoming data is received by the ssp. after the message has been sent, the off-chip slave decodes it and, after waiting one serial clock cycle after the last bit of the 8-bit control message has been sent, responds with the required data. the returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. in this configuration, during idle periods: ? the ssp_sck signal is forced low. ? ssn is forced high. ? the transmit data line mosi is forced to high impedance. a transmission is triggered by writing a contro l bit to the transm it fifo. the falling edge of ssn causes the value contained in the bottom entry of the transmit fifo to figure 64. texas instruments synchronous serial frame format (continuous transfer) ssp_sck ss mosi/miso ssp_sck ssn mosi/miso figure 65. microwire frame format (single transfer) ssp_sck ssn miso mosi free datasheet http:/// STMP36XX official product documentation 5/3/06 392 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 be transferred to the serial shift register of the transmit logic, and the msb of the 8- bit control frame to be shifted out onto the mosi pin. ssn remains low for the duration of the frame transmission. the mi so pin remains three-stated during this transmission. the off-chip serial slave device latches each control bit onto its serial shifter on the rising edge of each ssp_sck. after the last bit is latched by the slave device, the control byte is decoded during a one clo ck cycle wait-state, and the slave responds by transmitting data back to the ssp. each bi t is driven onto mi so line on the falling edge of ssp_sck. the ssp in turn la tches each bit on the rising edge of ssp_sck. at the end of the frame, for sing le transfers, the ssn signal is pulled high one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be trans ferred to the receive fifo. note : the off-chip slave device can three-st ate the receive line either on the falling edge of ssp_sck after the lsb has been latched in the rece ive shifter, or when the ssn pin goes high. for continuous transfers, data transmission begins and ends in the same manner as a single transfer. however, the ssn line is continuously asserted (held low) and transmission of data occurs back-to-back. the control byte of the next frame follows directly after the lsb of the received da ta from the current frame. each of the received values is transm itted from the receive sh ifter on the falling edge of ssp_sck, after the lsb of the frame has been latched into the ssp. 15.7.0.1. setup and hold time requirements on ssn with respect to ssp_sck in microwire mode in the microwire mode, the ssp slave sample s the first bit of receive data on the ris- ing edge of ssp_sck after ssn has gone low. masters that drive a free-running ssp_sck must ensure that the ssn signal has sufficient setup and hold margins with respect to the rising edge of ssp_sck. figure 67 illustrates thes e setup and hold time requir ements. with respect to the ssp_sck rising edge on which the first bit of receive data is to be sampled by the ssp slave, ssn must have a setup of at least two times the period of ssp_sck on which the ssp operates. with respect to th e ssp_sck rising edge previous to this edge, ssn must have a hold of at least one ssp_sck period. figure 66. microwire frame format (continuous transfer) ssp_sck ssn miso mosi free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 393 15.8. sd/sdio/mmc mode this mode is used to provide high performance with sd, sdio, mmc, and high- speed (4-bit) mmc cards. sd/mmc mode supports simultaneous command and data transfers. commands are sent to the card and responses are returned to the host on the cmd line. regis- ter data, such as card info rmation, is sent as a comm and response and is therefore on the cmd line. block data read from or wr itten to the card?s flash is transferred on the dat line(s). the ssp also supports the sdio irq. the ssp?s sd/mmc controller can automatica lly perform a single block read/write or card register operation with a single pio setup and run. for example, the sd/mmc controller can perform these steps with a single write to the pio registers: ? send command to the card. ? receive response from the card. ? check response for errors (and asse rt a cpu irq if there is an error). ? wait for the dat line(s) to be ready to transfer data (while counting for timeout) ? transfer a block of data to/from the card. ? check the crc or crc status of received/sent data (and assert irq if there is an error). the sd/mmc controller is generally used wi th the dma. each dma descriptor is set up the sd/mmc controller to perform a si ngle complex operat ion as exemplified above. multiple dma descriptors can be chained to perform multiple card block transfers without cpu intervention. 15.8.1. sd/mmc command/response transfer sd/mmc commands are written to the hw _ssp_cmdx registers and sent on the cmd line. command tokens consist of a start bit (0), a source bit (1), the actual figure 67. microwire frame format (continuous transfer) free datasheet http:/// STMP36XX official product documentation 5/3/06 394 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 command, which is padded to 38 bits, a 7-bit crc and a stop bit (1). the command token format is shown in table 520 . sd/mmc cards transmit command words with the most significant bit first. after the card receives the command, it checks for crc errors or invalid commands. if an error occurs, the card withholds the usual response to the command. after transmitting the end bit, the ssp releases the cmd line to the high-z state. a pullup resistor on the cmd node keeps it at the 1 state until the response packet is received. the slave waits to issue the reply until the sck line is clocking again. after the ssp sends an sd/mmc command, it optionally starts looking for a response from the card. it waits for the cmd line to go low, indicating the start of the response token. once the ssp has received the start an d source bits, it begins shifting the response conten t into the receive shift register. the ssp calculates the crc7 of the incoming data. if the card fails to start sending an expected response packet within 64 sck cycles, then an error has occurred. the command may be invalid or have a bad crc. after the ssp detects a timeout, it stops any dma request activity and sets the resp_timeout flag. if resp_timeout_irq_en is set, then a cpu irq is asserted. the ssp calculates the crc of the received response and compare it to the crc received from the card. if they do not match, then the ssp sets the resp_err sta- tus flag. if resp_err_irq_en is set, t hen a cpu irq is asserted on a command response crc mismatch. the ssp can also compare the 32-bit card status word, known as response r1, against a reference to check for errors . if check_resp in hw_ssp_ctrl0 is set, then the ssp xors the res ponse with the xor field in the hw_ssp_compref register. it then masks the results with the mask field in the hw_ssp_compmask register. if there are any differences bet ween the masked response and the refer- ence, then an error has oc curred. the cpu asserts the resp_err status flag. if resp_err_irq_en is set, then the resp_e rr_irq is asserted. in the isr, the cpu can read the status word to see which error flags are set. the regular and long response tokens are shown in table 521 and table 522 : 15.8.2. sd/mmc data block transfer block data is transferred on the data0 pin. in 1-bit i/o mode, the block data is for- matted as shown in table 523 . block data transfers typically have 512 bytes of pay- table 520. sd/mmc command/response transfer line start source data crc end cmd 0 1 (host) 38-bit command crc7 1 table 521. sd/mmc command regular response token line start source data crc end cmd 0 0 (card) 38-bit response crc7 1 table 522. sd/mmc command regular long response token line start source data crc end cmd 0 0 (card) 117-bit response crc16 1 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 395 load, plus a 16-bit crc, a start bit, and an end bit. the block size is programmable with the xfer_count field in the hw_ssp_ctrl0 register. in sd/mmc mode, word_length in the hw_ssp_ctrl1 register field should alwa ys be set to 8 bits. data is always sent most significant bit of the least significant byte first. the ssp is designed to support block transfer modes only. streaming modes may not be supported. figure 68 shows a flowchart of sd/mmc block read and write transfers. in block write mode, the card holds the data0 line low while it is busy. ssp must wait for the data0 line to be high for one clock cycle before starting to write a block. in block read mode, the card begins sending the data when it is ready. the first bit transmitted by the card is a start bit 0. prior to the 0 start bit, the data0 bus is high. after the start bit is received, data is sh ifted in. the ssp bus width is set using the bus_width bit in the hw_ssp_ctrl0 register. in 1-bit bus mode, the block data is formatted as shown in table 523 . in 4-bit i/o mode, the block data is formatted as shown in table 524 . 15.8.2.1. sd/mmc multiple block transfers the ssp supports sd/mmc mult iple block transfers. t he cpu or dma will config- ure the sd/mmc controller to issue a multi-block read or write command. if dma is used, then the first descriptor issues the multi-block read/write command and receives/sends the first block (512 bytes) of data. subsequent dma descriptors only receive/send blocks of data and do not issue new sd/mmc commands. if the card is configured for an open-ended multi-bl ock transfer, then the last dma descriptor needs to issue a stop command to the card. after each block of data has been transfer red, the ssp sends/receives the crc and checks the crc or the crc token. if the crc is okay, then the ssp signals the dma that it is done. 15.8.2.2. sd/mmc block transfer crc protection all block data transferred over the data bus is protected by crc16. for reads, the ssp calculates the crc of incoming data and compares it to the crc16 reference that is provided by the card at the end of the block. if a crc mismatch occurs, then the block asserts the data_crc_err status flag. if data_crc_irq_en is set, then a cpu irq is asserted. for block write operations, the card determines if a crc error has occurred. after the ssp has sent a block of data, it transmits the reference crc16. the card com- pares that to its calculated crc16. the card then sends a crc status token on the table 523. sd/mmc data block transfer 1-bit bus mode line start data data data crc end data0 0 data bit 7 byte 0 ... data bit 0 byte 511 crc16 1 table 524. sd/mmc data block transfer 4-bit bus mode line start data data data crc end data3 0 data bit 7 byte 0 ... data bit 3 byte 511 crc16 1 data2 0 data bit 6 byte 0 ... data bit 2 byte 511 crc16 1 data1 0 data bit 5 byte 0 ... data bit 1 byte 511 crc16 1 data0 0 data bit 4 byte 0 ... data bit 0 byte 511 crc16 1 free datasheet http:/// STMP36XX official product documentation 5/3/06 396 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 data bus. it sends a positive status (?010?) if the transfer was good, and a negative status (?101?) if the crc16 did not match. if the ssp receives a crc bad token, it sets the data_crc_error in the hw_ssp_ status register, and then it indi- cates it to the cpu if data_crc_irq_en is set. when the response is sent by the m m c card, the ssp will place the response in the resp register. the ssp w ill check the crc7 of the response packet against the received crc7. if there is an error, it w ill assert a cpu irq. sd/mmc block read example dma pio cycle: sd/m m c m ode read mode xfer_count=512 write the block_read command to sdctrlx. dma sets ssp run bit. ssp sends out the mmc block read command and begins looking at the dat line for a start bit. after the block read command is sent, ssp looks at the cmd line for a response. w hen the data is ready, the m m c will send the start bit and the ssp w ill put the data into the receive fifo and start asserting dma request. the received data w ill also be checked for crc16. if there is a crc error, the ssp w ill assert a c pu irq . after the block has been read and the crc checked, the ssp w ill indicate to the dm a that it is done. the dma can then issue a new command sequence, or tell the cpu that it is done. w hen the response is sent by the mmc card, the ssp will place the response in the resp register. the ssp w ill check the crc7 of the response packet against the received crc7. if there is an error, it w ill assert a cpu irq. sd/mmc block write example dma pio cycle: sd/mmc mode write mode xfer_count=512 write the block_write command to sdctrlx. dma sets ssp run bit. ssp sends out the mmc block write command and begins looking at the dat line for busy c ondition. ssp w ill start issuing d m a requests to fill the transm it fifo. after the block w rite command is sent, ssp looks at the cmd line for a response. w hen the data line is no longer busy, the ssp will start sending data. the transm itted data w ill also have crc16 calculated and transm itted after the data. if the card indicates a crc error, the ssp w ill assert a cpu irq. after the block has been sent and the crc checked, the ssp will indicate to the dm a that it is done. the dma can then issue a new command sequence or tell the cpu that it is done. figure 68. sd/mmc block transfer flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 397 15.8.3. sdio interrupts the ssp supports sdio inte rrupts. when the ssp is in sd/mmc mode and the sdio_irq bit in the hw_ssp_ctrl0 register is set, the ssp looks for interrupts on data1 during the valid irq periods. the valid irq periods are defined in the sdio specification. if the card asserts an interrupt and sdio_irq_en is set, then the ssp sets the sdio_irq status bit and asserts a cpu irq. other than detecting when card irqs are valid, the sdio irq function operates independently from the rest of the ssp. after the cpu receives an irq, it should monitor the ssp and dma status to determine when it should send commands to the sdio card to handle the interrupt. 15.8.4. sd/mmc mode error handling there are several errors that can occur during sd/mmc op eration. these errors can be caused by normal unexpected events, such as having a card removed or unusual events such as a card failure. the detected error cases are listed below. please note that in all cases belo w, a cpu irq is only asserted if data_crc_irq_enable is set in hw_ssp_ctrl1 register. ? data receive crc error ?detected by the ssp after a block receive. if this occurs, the ssp will not indicate to the dm a that the transfer is complete. it will set the data_crc_err status flag and assert a cpu irq. the isr should reset the ssp dma channel and instruct the dma to re-try the block read operation. ? data transmit crc error ?transmit crc error token is received from the sd/mmc card on the dat line after a bloc k transmit. if this occurs, the ssp will not indicate to the dma that the transfer is complete. it will set the data_crc_err status flag and assert a cpu irq. the isr should reset the ssp dma channel and instruct the dma to re-try the block write operation. ? data timeout error ?the ssp timeout counter is used to detect a timeout condition during data write or read oper ations. the timeout counts any time that the ssp is waiting on a busy dat bus. for read operations, the dat line(s) indicate busy before the ca rd sends the start bit. fo r write operations, the dat line(s) may indicate busy after the block has been sent to the card. if the timeout counter expires before the dat line(s) become ready, the ssp stops any dma requests, sets the data_timeout status flag, and asserts a cpu irq. the isr should check the status register to see that a data timeout has occurred. it can then reset the dma channel a nd ssp to re-try the operation. ? dma overflow/underflow ?the ssp should stop sck if the receive fifo is full or the transmit fifo is empty. so, a dm a underflow or overflow should not occur. however, if it does due to some unforeseen problem, the recv_ovrflw or xmit_undrflw status bit is set in the ssp status register. ? command response error ?the sd/mmc card returns an r1 status response after most commands. the ssp can co mpare the r1 response against a mask/reference pair. if any of the enabled bits are set, then an error has occurred. the ssp stops requesting any dm as, sets the resp_err status flag, and asserts a cpu irq. the cpu can read the ssp status register to see the resp_err flag and read the hw_ssp_s dresp0 register to get the actual response from the sd/mmc card. that response contains the specific error information. once the error is understood, the cpu can reset the dma channel and ssp and re-try the operation or take some other action to recover or inform the user of a non-recoverable error. free datasheet http:/// STMP36XX official product documentation 5/3/06 398 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 ? command response timeout ?if an expected response is not received within 64 sck cycles, then the command respons e has timed out. if this occurs, the ssp stops any dma requests, stops transf erring data to the card, sets the resp_timeout status flag, and asse rts the resp_timeout_irq. the isr should read the status register to fi nd that a command response timeout has occurred. it can then decide to rese t the dma channel an d ssp and re-try the operation. 15.8.5. sd/mmc clock control ? the serial clock (sck) never runs when the run bit is not set. ? sck runs any time that run is set and a data or command is active or pending. if a command has been sent and a response is expected, then sck continues to run until the response is received. if a data operation is active or if the dat line is busy, then sck runs. ? sck stops running if received command re sponse status r1 indicates an error. ? sck stops running if a data operation has timed out or a crc error has occurred. ? sck stops running after all pending commands and data operations have completed. sck restarts when a new command or data operation has been requested. 15.9. ms mode the ssp ms mode supports 1-bit ms data transfers. the ssp ms mode is designed to work with the STMP36XX dma controller. the dma controller?s linked descriptor architecture provides a high level of automatic operation without cpu intervention. 15.9.1. ms mode i/o pins the ms standard defines three pins: ? sdio ?a bidirectional data pin used for commands and data. ? bs : bus state?the bus state pin is used to indicate to the card which state it is operating in. ? sclk : serial clock?data chan ges on falling edges and is latched in on rising edges. 15.9.2. basic ms mode protocol the ms protocol uses a hierarchy of commands and bus operations to provide access to the internal flash memory, as shown in figure 69 . at a high level, the sys- tem may read or write flash pages or access card information or configuration data. those high-level operations are performed by executing a number of transfer pro- tocol commands, or tpcs. each tpc is sent to the card in a four-state bus transac- tion. the ssp?s ms controller automates each four-state bus access associated with a tpc. the cpu or dma provides higher-level control, putting mu ltiple tpcs together to perform the desired compound functions. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 399 15.9.3. ms mode high-level operation the STMP36XX cpu or dma is responsible for combining several smaller com- mands (tpcs) into complex operations such as reading or writing flash pages. the dma?s linked descriptor feature is particular ly useful for automating ms operations without requiring cpu intervention. ea ch dma descriptor commands the ssp to either send a single tpc with associated four-state bus acce ss or wait for a card irq during bs0. an example flow chart of the dma executing a ms page read oper- ation is shown in figure 70 . 15.9.4. ms mode four-state bus protocol the four-state bus operations are centered around transitions of the bus state. each bus state change represents a new operating state of the card, as shown in figure 71 . in most cases, the card starts in bs0/irq. when the card needs to signal the host, then it asserts the irq by bringing sdio high. irqs are asserted to signal that a requested task, such as a flash p age read or write, has completed. when the host is ready to send a command, it changes the bs signal from low to high, transitioning to bs1. on the next cycl e, the host begins transmitting the trans- fer protocol command (tpc). the tpc is eigh t bits wide. it includes a four-bit com- mand and the complement of the command for error-checking. the tpcs include: ? read_page_data? reads a 512byte+crc16 page from the page buffer. ? read_reg? reads from the register whose address was previously set. data length depends on the register. ? write_page_data? writes a 512byte+crc16 page to the page buffer. ? write_reg? writes to the register whose address was previously set. data length depends on the register. ? set_r/w_reg_adrs? sets the register accessed by read_reg and write_reg commands. sends 4bytes+crc16. ? set_cmd? sets the command to be executed by the flash memory controller. sends 8bits+crc16. the flash memory controller starts operation with this tpc and sets an int when it is completed. ? get_int? requests the contents of the int register. returns 8bits+crc16. flash read flash write read card information high-level operations multiple command protocol transfer protocol commands four-state bus access multiple commands used to perform high- level operation basic command element basic bus operations figure 69. basic ms protocols free datasheet http:/// STMP36XX official product documentation 5/3/06 400 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 write_reg to write the parameters (block and page address, etc). use setcmd to write the block_read command. card begins internal read cycle, returns to bs0. when the read is complete, card will assert irq. host: irq asserted? host: timeout expired? yes no no host send get_int command to check the status of the read command. use the dma?s sense command to compare the returned int status with an error mask stop checking for ms irq, set timeout error irq to cpu. error found? set error irq to cpu. cpu can issue additional commands to recover from the error. host send read_page_data command to start reading from the page buffer. yes yes no dma descriptor 1 sends command, 6 bytes parameters, crc16. dma descriptor 2 sends setcmd command w/ block_read as parameter, crc16. dma descriptor 3 wait for card irq (sdio=1). dma descriptor 4 sends get_int command, reads 1 byte int status + crc16. dma descriptor 6 send read_page_data. read 512 bytes data + crc16. dma descriptor 5 look at int status byte to see if any errors occurred. check crc16. is crc okay? ssp asserts cpu irq and does not return done to the dma. ssp returns done status to dma. dma starts another operation or asserts done irq to cpu. no yes figure 70. ms operation flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 401 after the tpc is sent, the host drives the bs line low again, transitioning to bs2. if the command results in data being written to the card, then the data transfer occurs during bs2. if the command results in data being read from the card, then bs2 is a ?handshake? state in which the host waits for the card to indicate that it is ready to send the requested read data to the host. the card toggles the sdio line when it is ready. in data write operations, bs3 is t he handshake state. in that case, the card signals the ready state after it has processed the written data or command enough to return to bs0. in the read-data case, the data is transferred from the card to the host in bs3. 15.9.5. wait for card irq many ms commands, such as flash read/w rite/erase, take longer than the time allowed during the han dshake period to complete. in these cases, the system returns to bs0 while the card is busy. afte r the card has completed its work (or finds an error during the attempt) , then it will irq the host by pulling sdio high. the host then checks the card?s status, as described in section 15.9.6 . the ssp can be programmed to wait for the card irq before transitioning to bs1 and issuing the tpc. to do this, set the wait_for_irq bit in the hw_ssp_ctrl0 register. after the run bit is set, the ssp monitors the sdio line and count for timeout. if the timeout expires before the card asserts the irq, then the ssp stops any dma activity and sets the data_timeout status and the data_timeout_irq, if it is enabled. 15.9.6. checking card status in ms mode, card status and flash page data are transferred over the sdio line. the card status can be retrieved by i ssuing a read_reg tpc after appropriately setting the register pointers with set_r/w _reg_addrs. the interrupt status reg- ister is often all that is needed. it can be easily read using the get_int tpc. get_int always returns eight bits of st atus while read_reg can return as many bytes as have been configured. the ssp can check up to 32 bits of status against a reference to check for errors. to check the read data, set the check_resp bit in the hw_ssp_ctrl0 register and provid e a mask and reference in the comp- mask and compref registers. when checking status, the xfer_size should be set to no more than four bytes because th e compare registers are 32 bits wide. if the masked card status does not match the re ference, the ssp stops any dma activity, sets the resp_error flag, and, if en abled, asserts th e resp_error_irq. bs0 idle/irq bs1 tpc bs2 handshake bs3 r-data+crc bs0 idle/irq bs1 tpc bs2 w-data+crc bs3 handshake four-state read four-state write figure 71. ms four-state read and write free datasheet http:/// STMP36XX official product documentation 5/3/06 402 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 15.9.7. ms mode error conditions there are several errors that can occur during ms operation. these errors can be caused by normal unexpected events, such as having a card removed, or unusual events, such as a card failure. the detected error cases include the following: ? data receive crc error? detected by the ssp after any data receive. if this occurs, the ssp will not indicate to the dm a that the transfer is complete. it will set the data_crc_err status flag and assert a cpu irq. the isr should reset the ssp dma channel and instruct the dma to re-try the read operation. note that in ms mode, a data crc error can occur on a 512-byte flash page or on a register read. any tpc that results in data being read from the card can result in this error. ? data transmit crc error? the ms card will check the crc16 of any data that is sent from the host during bs2. this data may be a 512-byte page of data for flash write, or it may be a register para meter or command as small as one byte. if a crc error occurs, the card will not return a ready signal during the handshake state. this will cause a time out in the ssp waiting for the handshake to complete during bs3. ? data timeout error? in ms mode, the timeout counter is used while waiting for an irq in bs0. if the timeout counter expires before an expected irq is asserted, the ssp will set the data_timeo ut status flag and can assert the data_timeout_irq if it is enabled. if the cpu irq is used, the isr should check the status register to see that a data timeout has occurred. it can then reset the dma channel and ssp to re-try the operation. the cpu can also read the ms status register to see if the ca rd has an error and/or needs to be reset. ? card status error? after a card has signaled an irq to the ssp to indicate that a requested flash controller operation has completed, the dma or cpu will instruct the ssp to issue a get_int comm and to retrieve t he interrupt status from the card. the ssp will use its ch eck response (check_resp) mode to compare the card?s status wi th a reference. if an erro r is indicated, the ssp will stop dma activity, set the resp_error flag and the resp_error_irq if it is enabled. 15.9.8. ms mode details the ssp handles all aspects of a full four -state bus transaction. it uses the com- mand registers that were added for sd/mmc to hold the 8-bit tpc. the data portion of the transaction is handled by the standa rd data path (fifo, data register, dma, etc.). all ms data transactions use a crc16 for edc. this crc16 is different than what is used for sd/mmc. see the ms documentation for specifics. the ssp monitors the sdio lin e and detects the card ha ndshake signal that indi- cates it is ready to transition from bs3 to bs4 or bs4 to bs0. the ms specification requires that the card indicate it is ready within 12 sclk cycles. the ssp also receives four continuous toggles on sdio before going to the next bus state. if the timeout counter expires before the read y handshake has been received, the ssp times out. this results in a data_timeout_irq to the cpu. 15.10. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 403 15.11. programmable registers the following registers provide control fo r programmable elements of the ssp port. 15.11.1. ssp control register 0 description hw_ssp_ctrl0 0x80010000 hw_ssp_ctrl0_set 0x80010004 hw_ssp_ctrl0_clr 0x80010008 hw_ssp_ctrl0_tog 0x8001000c table 525. hw_ssp_ctrl0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate run half_duplex lock_cs ignore_crc read data_xfer sdio_irq bus_width wait_for_irq wait_for_cmd long_resp check_resp get_resp enable xfer_count table 526. hw_ssp_ctrl0 bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 ssp reset. 0: ssp is no t reset. 1: ssp is held in reset. after reset, all regi sters are returned to their reset state. 30 clkgate rw 0x1 gate ssp clocks. 0: ssp clocks are not gated. 1: ssp clocks are gated. set this to save power while the ssp is not actively being us ed. configuration state is kept while the clock is gated. 29 run rw 0x0 ssp run. 0: ssp is not running. 1: ssp is running. automatically set during dma operation. 28 half_duplex rw 0x0 1= ignore receive data when transmitting, and force transmit data=0 when receiving. spi mode only. (read bit and data_xfer bit indicates tx or rx). 27 lock_cs rw 0x0 in spi mode: this affects the ssn output. 0= deassert chip select (cs) after transfer is complete. 1= continue to assert chip select (cs) after transfer is complete. software must clear this bit at the end of the transfer sequence. in sd/mmc mode: 0= look for a crc status token from the card on data0 after a block write. 1= ignore the crc status response on data0 after a write operation. note that the sd/mmc function should be used when performing mmc bustest_w operation. free datasheet http:/// STMP36XX official product documentation 5/3/06 404 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 26 ignore_crc rw 0x0 ignore crc - sd/mmc, ms - ignores the response crc. 25 read rw 0x0 read mode. when this and data_xfer are set, the ssp will read data from the devi ce. if this is not set, then the ssp will write data to the device. 24 data_xfer rw 0x0 data transfer mode. when set, transfer xfer_count bytes of dat a. when not set, the ssp will not transfer any data (command or wait for irq only). in ms mode, this bit selects the destination of read transfers and source for write transfers: set to 1 if using rx/tx fifos, and set to 0 if using resp0/cmd1 registers. when set to 0 in ms mode, the xfer_count field must be 4 or less. 23 sdio_irq rw 0x0 sdio irq mode. when set, the ssp will check for sdio card irqs on dat1 during valid irq periods. 22 bus_width rw 0x0 data bus width. set this bit to 0 for all modes, except for sd which can be either 0 or 1. one_bit = 0x0 data bus is 1-bit wide four_bit = 0x1 data bus is 4-bits wide 21 wait_for_irq rw 0x0 wait for ms irq. in ms mode, waits for the card to assert an irq before switching to bus state 1 and sending the tpc. in sd/mmc mode, this signal means wait for mmc ready before sending command. (mmc is busy when databit0 is low.) 20 wait_for_cmd rw 0x0 wait for data done (sd/mmc mode). 0: send commands immediately after they are written. 1: wait to send command until after the crc-checking phase of a data transfer has comp leted successfully. this delays sending a command until a block of data is transferred. this can be used to send a stop command during an sd/mmc multi-block read. 19 long_resp rw 0x0 get long response (sd/mmc mode). 0: the card response will be short. 1: the card will provide a 136- bit response. only valid if get_resp is set. a long response cannot be checked using check_resp. 18 check_resp rw 0x0 check response (sd/mmc, ms modes). if this bit is set, the ssp will xor the re sult with the reference field and then mask the incoming status word with the mask field in the compare register. if there is a mismatch, then the ssp will set the resp_err status bit, and, if enabled, the resp_err_irq. this should not be used with long_resp. 17 get_resp rw 0x0 get response (sd/mmc, ms modes). 0: do not wait for a response from the card. 1: this command should receive a response from the card. table 526. hw_ssp_ctrl0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 405 description: empty description. example: empty example. 15.11.2. sd/mmc and ms command register 0 description this register is the command index an d control register for sd/mmc and ms modes. hw_ssp_cmd0 0x80010010 hw_ssp_cmd0_set 0x80010014 hw_ssp_cmd0_clr 0x80010018 hw_ssp_cmd0_tog 0x8001001c 16 enable rw 0x0 command transmit enable (sd/mmc, ms modes). 0: commands are not enabled. 1: data in command registers will be sent. this is normally enabled in sd/mmc or ms mode but is disabled when waiting for a ms irq. 15:0 xfer_count rw 0x1 number of words to transfer, as referenced in word_length in hw_ssp_ct rl1. the run bit and dma request will clear after this many words have been transferred. in sd/mmc or ms mode, this should be a multiple of the block size. table 527. hw_ssp_cmd0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 cmd table 526. hw_ssp_ctrl0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 406 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 table 528. hw_ssp_cmd0 bit field descriptions bits label rw reset definition 31:8 rsvd0 ro 0x0 reserved 7:0 cmd rw 0x0 sd/mmc command index (uses 5:0) or ms tpc [7:0] to be sent to card. mmc_go_idle_state = 0x00 mmc_send_op_cond = 0x01 mmc_all_send_cid = 0x02 mmc_set_relative_addr = 0x03 mmc_set_dsr = 0x04 mmc_reserved_5 = 0x05 mmc_switch = 0x06 mmc_select_deselect_card = 0x07 mmc_send_ext_csd = 0x08 mmc_send_csd = 0x09 mmc_send_cid = 0x0a mmc_read_dat_until_stop = 0x0b mmc_stop_transmission = 0x0c mmc_send_status = 0x0d mmc_bustest_r = 0x0e mmc_go_inactive_state = 0x0f mmc_set_blocklen = 0x10 mmc_read_single_block = 0x11 mmc_read_multiple_block = 0x12 mmc_bustest_w = 0x13 mmc_write_dat_until_stop = 0x14 mmc_set_block_count = 0x17 mmc_write_block = 0x18 mmc_write_multiple_block = 0x19 mmc_program_cid = 0x1a mmc_program_csd = 0x1b mmc_set_write_prot = 0x1c mmc_clr_write_prot = 0x1d mmc_send_write_prot = 0x1e mmc_erase_group_start = 0x23 mmc_erase_group_end = 0x24 mmc_erase = 0x26 mmc_fast_io = 0x27 mmc_go_irq_state = 0x28 mmc_lock_unlock = 0x2a mmc_app_cmd = 0x37 mmc_gen_cmd = 0x38 sd_go_idle_state = 0x00 sd_all_send_cid = 0x02 sd_send_relative_addr = 0x03 sd_set_dsr = 0x04 sd_io_send_op_cond = 0x05 sd_select_deselect_card = 0x07 sd_send_csd = 0x09 sd_send_cid = 0x0a sd_stop_transmission = 0x0c sd_send_status = 0x0d sd_go_inactive_state = 0x0f sd_set_blocklen = 0x10 sd_read_single_block = 0x11 sd_read_multiple_block = 0x12 sd_write_block = 0x18 sd_write_multiple_block = 0x19 sd_program_csd = 0x1b sd_set_write_prot = 0x1c sd_clr_write_prot = 0x1d sd_send_write_prot = 0x1e sd_erase_wr_blk_start = 0x20 sd_erase_wr_blk_end = 0x21 sd_erase_group_start = 0x23 sd_erase_group_end = 0x24 sd_erase = 0x26 sd_lock_unlock = 0x2a sd_io_rw_direct = 0x34 sd_io_rw_extended = 0x35 sd_app_cmd = 0x37 sd_gen_cmd = 0x38 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 407 description: empty description. example: empty example. 15.11.3. sd/mmc command register 1 description this register is the command argu ment register for sd/mmc mode. hw_ssp_cmd1 0x80010020 description: empty description. example: empty example. 15.11.4. sd/mmc and ms compare reference register description this register is the status respons e reference for mmc/sd and ms modes. hw_ssp_compref 0x80010030 description: empty description. example: table 529. hw_ssp_cmd1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_arg table 530. hw_ssp_cmd1 bit field descriptions bits label rw reset definition 31:0 cmd_arg rw 0x0 sd/mmc or ms command argument. see ssp_ctrl0_data_xfer bit description. table 531. hw_ssp_compref 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 reference table 532. hw_ssp_compre f bit field descriptions bits label rw reset definition 31:0 reference rw 0x0 sd/mmc, ms compar e mode reference. if check_resp is set, the response will be xored with this value. the results will be masked by the mask bitfield. if there are any differences, then the ssp will indicate an error state to the dma. free datasheet http:/// STMP36XX official product documentation 5/3/06 408 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 empty example. 15.11.5. sd/mmc and ms compare mask register description this register is the status resp onse mask for mmc/sd and ms modes. hw_ssp_compmask 0x80010040 description: empty description. example: empty example. 15.11.6. ssp timing register description this register is used to co nfigure the timing for the ssp. hw_ssp_timing 0x80010050 table 533. hw_ssp_compmask 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 mask table 534. hw_ssp_compmask bit field descriptions bits label rw reset definition 31:0 mask rw 0x0 sd/mmc, ms compare mode mask. if check_resp is set, the response is compared to reference, and the results are masked by this bitfield. table 535. hw_ssp_timing 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 timeout clock_divide clock_rate table 536. hw_ssp_timing bit field descriptions bits label rw reset definition 31:16 timeout rw 0x0 timeout counter, in seri al clock cycles. this timeout is used for data transfer/write operations in sd/mmc and ms modes. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 409 description: empty description. example: empty example. 15.11.7. ssp control register 1 description control register 1. hw_ssp_ctrl1 0x80010060 hw_ssp_ctrl1_set 0x80010064 hw_ssp_ctrl1_clr 0x80010068 hw_ssp_ctrl1_tog 0x8001006c 15:8 clock_divide rw 0x0 clock pre-divider. clock_divide must be an even value from 2 to 254. 7:0 clock_rate rw 0x0 serial clock rate. the value clock_rate is used to generate the transmit an d receive bit rate of the ssp. the bit rate is sspclk / (clock_divide x (1+ clock_rate)). clock_rate is a value from 0 to 255. table 537. hw_ssp_ctrl1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sdio_irq sdio_irq_en resp_err_irq resp_err_irq_en resp_timeout_irq resp_timeout_irq_en data_timeout_irq data_timeout_irq_en data_crc_irq data_crc_irq_en xmit_irq xmit_irq_en recv_irq recv_irq_en recv_timeout_irq recv_timeout_irq_en recv_ovrflw_irq recv_ovrflw_irq_en dma_enable loopback slave_out_disable phase polarity slave_mode word_length ssp_mode table 538. hw_ssp_ctrl1 bit field descriptions bits label rw reset definition 31 sdio_irq rw 0x0 if this is set, an sdio card interrupt has occurred and an irq, if enabled, has been sent to the interrupt collector (icoll). write a one to the sct clear address to reset this inte rrupt request status bit. 30 sdio_irq_en rw 0x0 sdio card interrupt ir q enable. 0: sdio card irqs masked. 1: sdio card irqs will be sent to the icoll. table 536. hw_ssp_timing bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 410 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 29 resp_err_irq rw 0x0 when the check_resp bit in ctrl0 is set, if an unexpected response is received from the card, this bit will be set. write a one to the sct clear address to reset this interrupt request status bit. note that the ssp block must be reset after a crc error or timeout irq. 28 resp_err_irq_en rw 0x0 sd/mmc card error irq enable. 0: card error irq is masked. 1: card error irq is enabled. when set to 1, if an sd/mmc card indicates a card erro r (bit is set in both the sd/mmc error mask and r1 card status response), then a cpu irq will be asserted. 27 resp_timeout_irq rw 0x0 if this is set, a command response timeout has occurred, and an irq, if enab led, has been sent to the irq collector. write a one to the sct clear address to reset this interrupt request status bit. note that the ssp block must be reset after a crc error or timeout irq. 26 resp_timeout_irq_en rw 0x0 sd/mmc, ms card command respone timeout error irq enable. 0: response timeout irq is masked. 1: response timeout irq is enabled. when set to 1, if an sd/mmc card does not respond to a command within 64 cycles or a ms card does not return ready during the handshake bus state within 32 cycles, then this cpu irq will be asserted. 25 data_timeout_irq rw 0x0 data transmit/receive timeout error irq. if the timeout counter expires befo re the dat bus is ready for write or sends read da ta, then a data timeout has occurred. only valid for sd/mmc and ms modes. write a one to the sct clear address to reset this interrupt request status bi t. note that the ssp block must be reset after a crc error or timeout irq. 24 data_timeout_irq_en rw 0x0 data transmit/receive timeout error irq enable. if the timeout counter expires before the dat bus is ready for write or sends read data, then a data timeout has occurred. only valid for sd/mmc and ms modes. 23 data_crc_irq rw 0x0 data transmit/receive crc error irq. only valid for sd/mmc and ms modes. write a one to the sct clear address to reset this interrupt request status bit. note that the ssp block must be reset after a crc error or timeout irq. 22 data_crc_irq_en rw 0x0 data transmit/receive crc error irq enable. only valid for sd/mmc and ms modes. 21 xmit_irq rw 0x1 transmit fifo half empt y or less irq. if enabled and the transmit fifo is half empty or lesss, an irq will be generated. write a one to the sct clear address to reset this interrupt request status bit. 20 xmit_irq_en rw 0x0 transmit fifo half empty or less irq enable. if set and the transmit fifo is half empty or lesss, an irq will be generated. not for use with dma. table 538. hw_ssp_ctrl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 411 19 recv_irq rw 0x0 receive fifo at least half filled irq. if enabled and the receive fifo is half filled, an irq will be generated. write a one to the sct clear address to reset this interrupt request status bit. 18 recv_irq_en rw 0x0 receive fifo at least half filled irq enable. if set and the receive fifo is half filled, an irq will be generated. this should not be used with the dma. 17 recv_timeout_irq rw 0x0 data timeout interrupt. if enabled and the receive fifo is not empty, an irq will be generated if 128 hclk cycles pass before the data register is read. write a one to the sct clear address to reset this interrupt request status bit. 16 recv_timeout_irq_en rw 0x0 receive timeout. if set and the receive fifo is not empty, an irq will be generated if 128 hclk cycles pass before the data register is read. 15 recv_ovrflw_irq rw 0x0 receiver overflow interr upt. indicates that the receive fifo has been written to while full. write a one to the sct clear address to reset this interrupt request status bit. 14 recv_ovrflw_irq_en rw 0x0 receiver overflow interrupt enable. if set, an irq will be generated if the receive fifo is written to while full. 13 dma_enable rw 0x0 dma enable. this signal enables dma request and dma command end signals to be asserted. 12 loopback rw 0x0 loopback mode is not supported. clear this bit to 0. 11 slave_out_disable rw 0x0 slave output disable. 0: ssp can drive miso in slave mode. 1: ssp does not drive miso in slave mode. 10 phase rw 0x0 serial clock phase. for spi mode only. 9 polarity rw 0x0 serial clock polarity. for spi and sd modes only. in sd mode, 0: command and transmit data change after rising edge of sck, 1: command and transmit data change after falling edge of sck. 8 slave_mode rw 0x0 slave mode. 0: ssp is in master mode. 1: ssp is in slave mode. set to one for sd/mmc and ms modes. table 538. hw_ssp_ctrl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 412 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 15.11.8. ssp data register description hw_ssp_data 0x80010070 description: 7:4 word_length rw 0x8 word length in bits per word. 0x0 to 0x2 are reserved and undefined. 0x3 is 4 bits per word...0xf is 16 bits per word. always use 8 bits per word in sd/mmc and ms modes. reserved0 = 0x0 0x0 is reserved and undefined reserved1 = 0x1 0x1 is reserved and undefined reserved2 = 0x2 0x2 is reserved and undefined four_bits = 0x3 use 4 bits per word eight_bits = 0x7 use 8 bits per word sixteen_bits = 0xf use 16 bits per word 3:0 ssp_mode rw 0x0 operating mode. 0x0 = motorola spi mode, 0x1 = ti syncronous serial interface mode, 0x2 = national microwire mode, 0x3 = sd/mmc card mode, 0x4 = ms mode. before changing ssp_mode, a soft reset must be issued to clear the fifos. spi = 0x0 motorola spi mode ssi = 0x1 texas instruments ssi mode microwire = 0x2 national semiconductor microwire mode sd_mmc = 0x3 sd/mmc mode ms = 0x4 ms mode table 539. hw_ssp_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 data table 540. hw_ssp_dat a bit field descriptions bits label rw reset definition 31:0 data rw 0x0 data register. holds one, two, three, or four words, depending on the word_length. if word_length is not 8, 16, or 32, the words are padded to those lengths. data is right-justified. when the run bit is set, reads will cause the receive fifo read pointer to increment and writes will cause the transmit fifo write pointer to increment. byte-writes are supported only for the least significant byte. half-word (16-bit) writes are supported only for the lower half-word. table 538. hw_ssp_ctrl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 413 empty description. example: empty example. 15.11.9. sd/mmc card response register 0 description hw_ssp_sdresp0 0x80010080 description: empty description. example: empty example. 15.11.10.sd/mmc card response register 1 description hw_ssp_sdresp1 0x80010090 description: empty description. example: empty example. table 541. hw_ssp_sdresp0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 resp0 table 542. hw_ssp_sdresp0 bit field descriptions bits label rw reset definition 31:0 resp0 ro 0x0 sd/mmc response status bits[31:0]. in ms mode, device read data can be placed here. see ssp_ctrl0_data_xfer bit description. table 543. hw_ssp_sdresp1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 resp1 table 544. hw_ssp_sdresp1 bit field descriptions bits label rw reset definition 31:0 resp1 ro 0x0 sd/mmc short response command index [37:32] or long response [63:32] free datasheet http:/// STMP36XX official product documentation 5/3/06 414 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 15.11.11.sd/mmc card response register 2 description hw_ssp_sdresp2 0x800100a0 description: empty description. example: empty example. 15.11.12.sd/mmc card response register 3 description hw_ssp_sdresp3 0x800100b0 description: empty description. example: empty example. 15.11.13.ssp status register description ssp read-only status register. hw_ssp_status 0x800100c0 table 545. hw_ssp_sdresp2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 resp2 table 546. hw_ssp_sdresp2 bit field descriptions bits label rw reset definition 31:0 resp2 ro 0x0 sd/mmc long response [95:64] table 547. hw_ssp_sdresp3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 resp3 table 548. hw_ssp_sdresp3 bit field descriptions bits label rw reset definition 31:0 resp3 ro 0x0 sd/mmc long response [127:96] free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 415 table 549. hw_ssp_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 present ms_present sd_present card_detect recv_count xmit_count dmareq dmaend sdio_irq resp_crc_err resp_err resp_timeout data_crc_err timeout recv_timeout_stat recv_data_stat recv_ovrflw recv_full recv_not_empty xmit_not_full xmit_empty xmit_undrflw cmd_busy data_busy data_xfer busy table 550. hw_ssp_status bit field descriptions bits label rw reset definition 31 present ro 0x1 ssp present bit. 0: ssp is not present in this product. 1: ssp is present. 30 ms_present ro 0x1 ms controller present. 0: ms controller is not present in this product. 1: ms controller is present. 29 sd_present ro 0x1 sd/mmc controller present. 0: sd/mmc controller is not present in this product. 1: sd/mmc controller is present. 28 card_detect ro 0x0 reflects the state of the ssp_detect input pin. 27:24 recv_count ro 0x0 receive fifo count. number of bytes of valid data in receive fifo. when zero, use the full bit to differentiate between full and empty. 23:20 xmit_count ro 0x0 transmit fifo count. number of bytes of valid data in transmit fifo. when zero, use the full bit to differentiate between full and empty. 19 dmareq ro 0x0 reflects the state of th e ssp_dmareq output port. this is a toggle signal. 18 dmaend ro 0x0 reflects the state of the ssp_dmaend output port. this is a toggle signal. 17 sdio_irq ro 0x0 sdio irq has been detected. 16 resp_crc_err ro 0x0 sd/mmc, ms response failed crc check. 15 resp_err ro 0x0 sd/mmc, ms card responded to command with an error condition. 14 resp_timeout ro 0x0 sd/mmc, ms card expected command response not received within 64 clk cycles (16 for ms). this indicates a card error, bad command, or command that failed crc check. 13 data_crc_err ro 0x0 data crc error 12 timeout ro 0x0 in sd/mmc mode, the timeout counter expired before data bus was ready. in ms mode, the timeout expired waiting for interru pt from card. free datasheet http:/// STMP36XX official product documentation 5/3/06 416 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 15.11.14.ssp debug register description this register is a read-onl y debug register for the ssp. hw_ssp_debug 0x80010100 11 recv_timeout_stat ro 0x0 raw receive timeout status. indicates that no read has occurred to non-empty receive data fifo for 128 cycles 10 recv_data_stat ro 0x0 raw receive fifo at least half filled interrupt status. 9 recv_ovrflw ro 0x0 raw receiver overflow interrupt. 8 recv_full ro 0x0 receive fifo full 7 recv_not_empty ro 0x0 receive fifo not empty 6 xmit_not_full ro 0x1 transmit fifo not full 5 xmit_empty ro 0x1 transmit fifo empty. 4 xmit_undrflw ro 0x0 transmit underflow has occurred. 3 cmd_busy ro 0x0 sd/mmc or ms command controller is busy sending a command or receiving a response. 2 data_busy ro 0x0 card indicates data line is busy (sd/mmc or ms) 1 data_xfer ro 0x1 data transfer active 0 busy ro 0x0 ssp is busy. table 551. hw_ssp_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 datacrc_err data_stall dat_sm mstk_sm cmd_oe cmd_sm clk_oe mmc_sm dat0_oe dat321_oe ssp_cmd ssp_resp ssp_txd ssp_rxd table 552. hw_ssp_debug bit field descriptions bits label rw reset definition 31:28 datacrc_err ro 0x0 data crc error 27 data_stall ro 0x0 ms/mmc mode: fifo transfer not ready. table 550. hw_ssp_status bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 15: sy nchronous serial port (ssp) 417 description: empty description. example: empty example. ssp xml revision: 1.38 26:24 dat_sm ro 0x0 ms/mmc data transfer state machine dsm_idle = 0x0 dsm_start = 0x1 dsm_word = 0x2 dsm_crc1 = 0x3 dsm_crc2 = 0x4 dsm_end = 0x5 dsm_rxdly = 0x6 23:20 mstk_sm ro 0x0 ms state machine mstk_idle = 0x0 mstk_ckon = 0x1 mstk_bs1 = 0x2 mstk_tpc = 0x3 mstk_bs2 = 0x4 mstk_hdshk = 0x5 mstk_bs3 = 0x6 mstk_rw = 0x7 mstk_crc1 = 0x8 mstk_crc2 = 0x9 mstk_bs0 = 0xa mstk_done = 0xb 19 cmd_oe ro 0x0 enable for ssp_cmd 18:16 cmd_sm ro 0x0 mmc command_state machine csm_idle = 0x0 csm_index = 0x1 csm_arg = 0x2 csm_crc = 0x3 15 clk_oe ro 0x0 enable for ssp_clkout 14:12 mmc_sm ro 0x0 mmc_state machine mmc_idle = 0x0 mmc_cmd = 0x1 mmc_trc = 0x2 mmc_resp = 0x3 mmc_rprx = 0x4 mmc_tx = 0x5 mmc_ctok = 0x6 mmc_rx = 0x7 11 dat0_oe ro 0x0 enable for ssp_txd0 10 dat321_oe ro 0x0 enable for ssp_txd321 9 ssp_cmd ro 0x0 ssp_cmd 8 ssp_resp ro 0x0 ssp_resp 7:4 ssp_txd ro 0x0 ssp_txd 3:0 ssp_rxd ro 0x0 ssp_rxd table 552. hw_ssp_debug bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 418 chapter 15: synchronous serial port (ssp) 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 16: lcd interface (lcdif) 419 16. lcd interface (lcdif) this chapter describes the lcd interfac e included on the STMP36XX and includes operation examples. programmable registers are described in section 16.5 . 16.1. overview many products based on the STMP36XX include an lcd panel with an integrated controller/driver. these smar t lcds are available in a range of sizes and capabili- ties, from simple text-only displays to qvga, 16bpp color tft panels. the inte- grated controllers include a frame buffer and logic to generate the appropriate lcd waveforms, including any frame rate mo dulation for stn displays. smart displays have an asynchronous parallel interface th at is used for setup and to write to the frame buffer. in general, it is not necessary to read data from the lcd controller. the lcd interface provided on the STMP36XX is shown in figure 72 . 24-mhz xtal osc. divide by n lcdif programmable registers arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram lcdif pin state machine dma request external lcd controller xclk write strobe d0..d15 csn resetn regn figure 72. lcd interface block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 420 chapter 16: lcd interface (lcdif) 5-36xx-d1-1.02-050306 the lcd interface on the STMP36XX has several major features: ? dma data transfers allow minimal cpu overhead. ? 8 and 16-bit data bus widths are supported. ? programmable timing supports a wide range of controllers. the lcdif provides an efficient mechanism to control an external smart lcd with an integrated controller. it resides on the apbx bus. it has memory-mapped control and data registers. the ah b-apbx bridge dma can be used to move data from a memory-mapped frame buffer to the lcd?s internal frame buffer. the cpu can directly send commands or data by setting up a non-dma transfer and writing directly to the data register. since the lcdif uses the ahb-apbx bridge dma, the software designer can take advantage of the dma?s linke d descriptors. this enable s substantial flexibility for setting up frame buffers. it can be configured for 8 or 16 bit transfers. in 8-bit mode, pins corresponding to the up per bits will output 0, unle ss they have been configured to connect to another peripheral (such as gpio). the lcdif receives little-endian input, but can transform the output through the use of the data_swizzle field in the hw_lcdif_ctrl register. the data swizzle manipulates the out-going data based on the following values: ? 00 (0): no swizzle (little-endian) ? 01 (1): swap bytes zero and thre e, swap bytes 1 and 2 (big-endian) ? 10 (2): swap half words ? 11 (3): swap bytes within each half-word the data register (hw_lcdif_data) uses the bus byte enables, which are used to determine how many valid bytes are in each written word. for example, if the entire 32-bit word is valid, the lcdif transmits two (16-bit m ode) or four (8-bit mode) lcd data operations. the dma sends full 32-bit words as much as possible. the last word will be shorter if the dm a transfer length is not a mult iple of four bytes. if sys- tem software writes to the data register di rectly, care should be taken to ensure that the correct byte enables are asserted (b y using the appropriate store command). otherwise, the lcdif may send invalid cycles to the display. the lcdif provides a request signal to the central dma; see section 11.2. ?apbx dma? on page 258 . the request signal is asserted any time the lcdif is enabled and its data fifo has space for more data. the dma request signal is also visible in the lcdif control and status register. soft ware writing directly to the lcdif data register (as opposed to using dma) should monitor the fifo_status bit and only write new data when the fifo is not full. the lcdif has a control output line that ca n be used to select which register is being written to in the lcd?s controller. th is register-select line is typically used to switch between command and data modes. 16.2. lcd interface op eration example if using dma, see chapter 11 for more information on using the dma engine. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 16: lcd interface (lcdif) 421 the typical usage of the lcdif block in so ftware mode (also called soft dma) would flow similarly to that outlined in section 16.2.1 and section 16.2.2 . 16.2.1. initialization steps 1. to set the output pins for driving the lcd panel, set the appropriate bits in the hw_pinctrl_muxselx registers in the pinctrl block. (see chapter 17 , ?pin control and gpio? on page 429 .) 2. bring the lcdif out of soft reset and clock gate. 3. reset the lcd controller by setting lcdif_ctrl_reset bit appropriately, being careful to observ e the reset requirements of the controller. 4. set the busy_enable bit in the hw_lcdi f_ctrl register if connected to an lcd controller that implements a busy line. otherwise, the busy line is ignored. 5. set the timings in the hw_lcdif_timing register appropriately. cmd_hold is the hold time in cycles for the dcn signal. cmd_setup is the setup time in cycles for the dcn signal. data_hold is the hold time in cycles for the wen signal. data_setup is the setup time in cycles for the wen signal. also note that all four of these fields must be non-zero. the lcdif does not function if any of these signals are set to zero. 6. set the data_swizzle according to the endianness of the lcd controller. 7. set the mode86 register based on whether the data strobe should be active high (1) or low (0). 8. set the data_select register based on whether the data to be sent is in com- mand mode (0) or data mode (1). note that the idle state for the dcn signal is high, regardless of the programmi ng of the data_select register. 9. set the word_length field appropriately?0 = 16-bit bus, 1 = 8-bit bus. 16.2.2. run time steps 1. set the count register with the amount of data transfer units to send. the transfer unit size is based on word_length, so programming 100 into count with a word_length of 0 will send 100 half-words. 2. when the above setup is completed and software is ready to send data, the run bit is set to 1. the lcdif is now r eady to receive data through writes to the hw_lcdif_data register. note that, while in soft dma mode, the software will need to poll the fifo_status bit to ensure that it does not overflow the lcdif's data buffers. the fifo_status bit indicates the fifo full state when it is 0. therefore, when the fifo_status bit is 1, the data register ca n be safely written with a word, half-word, or byte as required. writing to the data register when the fifo _status bit is 0 will result in incorrect operation. the run bit is cleared automatically when the lcdif has received all the data and completed the transfer to the pane l. the current trans- fer can be canceled (or aborted) if the run bit is manually set to 0. if the run bit is set to 0 during the middle of a transfer, the lcdif transmits out all data it has received to that point?that is, it will flush the fifo. in this case, the transfer count is not satisfied, but the transfer will finish no rmally, and the lcdif will return to the idle state and be ready to be programmed for the next transfer. free datasheet http:/// STMP36XX official product documentation 5/3/06 422 chapter 16: lcd interface (lcdif) 5-36xx-d1-1.02-050306 16.3. lcdif pin timing diagrams the lcdif has flexible pin and strobe timings, shown in figure 73 , which enable it to optimally support a wide range of lcds. the lcdif has four basic timing parameters: setup and hold for the com- mand/data register selection (tcs, tch) and setup and hold for the data bus (tds, tdh). these parameters are expr essed in xclk cycles. the lcdif data strobe polarity can be selected to acti ve high (6800 mode) or active low (8080 mode). in 8080 mode, new data is written at the falling edge of the write strobe, wen. wen is asserted low for tds xclk clock cycles. the lcd controller latches the data with the rising edge of wen. wen remains high for tdh xclk cycles. the cen signal also remains asserted (low) for at least tdh xclk cycles. the data/command register select signal is asserted tas xc lk cycles before cen and remains asserted for tah cycles after cen is no longer active. the minimum cycle time is two xclk cycles (tds=tdh=1). this results in a maxi- mum lcd data rate of 12mb/sec when xclk is 24 mhz. tds and tdh are 8-bit values so minimum lcdif rate is at 510 xclk cycles (47 khz with a 24-mhz xclk). the timings are not automatically adjusted if the xclk frequency changes, so it may be necessary to adjust the timings if xclk changes. 16.4. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. figure 73. lcdif timing (command cycle) data0 lcdif_wen lcdif_data (write) tds tdh lcdif_cen data1 tdh tas lcdif_d/cn tah free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 16: lcd interface (lcdif) 423 16.5. programmable registers the lcd interface block contains the fo llowing directly programmable registers. 16.5.1. lcd interface control and status register description the lcd interface control and status regist er provides overall control of the lcd parallel interface. hw_lcdif_ctrl 0x80060000 hw_lcdif_ctrl_set 0x80060004 hw_lcdif_ctrl_clr 0x80060008 hw_lcdif_ctrl_tog 0x8006000c table 553. hw_lcdif_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate present rsrvd1 busy_enable fifo_status dma_req data_swizzle reset mode86 data_select word_length run count table 554. hw_lcdif_ctrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 this bit must be set to zero to enable normal operation of the lcdif. when set to one, it forces a block-level reset. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. 29 present ro 0x1 0: lcdif not present in this product 1: lcdif is present. 28:26 rsrvd1 ro 0x0 reserved bits, write as 0. 25 busy_enable rw 0x0 this bit enables the use of the interface's busy signal input. this should be enabled for lcd controllers that implement a busy line (to stall the lcdif from sending more data until ready). otherwise this bit should be cleared. busy_disabled = 0x0 the busy si gnal from the lcd controller will be ignored. busy_enabled = 0x1 enable the use of the busy signal from the lcd controller. 24 fifo_status ro 0x0 lcdif data fifo status. this bit indicates whether the fifo is full or not full. fifo_full = 0x0 lcdif data fifo is full, and lcdif data register must not be written. fifo_ok = 0x1 ok to write the lcdif data register. 23 dma_req ro 0x0 reflects the current st ate of the dma request line for the lcdif. the dma request line toggles for each new request. free datasheet http:/// STMP36XX official product documentation 5/3/06 424 chapter 16: lcd interface (lcdif) 5-36xx-d1-1.02-050306 description: the lcd interface control and status re gister provides a variety of control and status functions to the programmer. these functions allow the interface to be very flexible to work with a variety of lcd controllers, and to minimize overhead and increase performance of lcd programming. example: empty example. 22:21 data_swizzle rw 0x0 this field specifies how to swap the bytes in the hw_lcdif_data register before transmitting them over the lcd interface bus. the data is always transmitted with the least si gnificant byte/hword (half- word) first after the swizzle takes place. the swizzle function is independent of the word_length bit. see the explanation of the hw_lcdif_data for names and definitions of data register fields. the supported swizzle configurations are: no_swap = 0x0 no byte swapping.(little endian) little_endian = 0x0 little endian byte ordering (same as no_swap). big_endian_swap = 0x1 big endian swap (swap bytes 0,3 and 1,2). swap_all_bytes = 0x1 swizzle all bytes, swap bytes 0,3 and 1,2 (aka big endian). hwd_swap = 0x2 swap half-words. hwd_byte_swap = 0x3 swap bytes within each half-word. 20 reset rw 0x0 reset bit for the external lcd controller. this bit can be changed at any time. lcdreset_low = 0x0 lcd_reset output signal is low. lcdreset_high = 0x1 lcd_reset output signal is high. 19 mode86 rw 0x0 data strobe polarity. this bit should only be changed when run = 0. 8080_mode = 0x0 data strobe is active low. 6800_mode = 0x1 data strobe is active high. 18 data_select rw 0x0 command mode polarity. this bit should only be changed when run = 0. cmd_mode = 0x0 command mode. dcn signal is low. data_mode = 0x1 data mode. dcn signal is high. 17 word_length rw 0x0 data bus transfer width. 16_bit = 0x0 16-bit data bus mode. 8_bit = 0x1 8-bit data bus mode. 16 run rw 0x0 when this bit is set by software, the lcdif will send count words (whether 8 or 16 bits) of data as data is written to the data register. the run bit is cleared by hardware only after count words have been written to the data register. 15:0 count rw 0x0 this field tells the lcdif how much data will be sent for this frame, or transaction. count refers to the number of words of data. the word size is specified in the word_length field (8 or 16 bit words). table 554. hw_lcdif_ctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 16: lcd interface (lcdif) 425 16.5.2. lcd interface timing register description the lcd interface timing register contro ls the various setup and hold times enforced by the lcd interface. hw_lcdif_timing 0x80060010 description: the values used in this register are dependent on the part icular lcd controller used; consult the user's manual for the particular controller for required timings. each field of the register must be non -zero, therefore th e minimum value is: 0x01010101. note: the timings are not automatically adjusted if the xclk fre- quency changes; it may be necessary to ad just the timings if xclk changes. note: each field in this register must be non-zero or the lc d interface will not function. example: empty example. 16.5.3. lcd interface data register description the data sent to an external lcd controller is written to this register. data can be written to this register (from the processo r's perspective) as bytes, half-words (16 bits), or words (32 bits), as appropriate. hw_lcdif_data 0x80060020 table 555. hw_lcdif_timing 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 cmd_hold cmd_setup data_hold data_setup table 556. hw_lcdif_timing bit field descriptions bits label rw reset definition 31:24 cmd_hold rw 0x00 number of xclk cycles that the dcn signal is active after cen is deasserted. 23:16 cmd_setup rw 0x00 number of xclk cycles that the the dcn signal is active before cen is asserted. 15:8 data_hold rw 0x00 data bus hold time in xclk cycles. also the time that the data strobe is deasserted in a cycle 7:0 data_setup rw 0x00 data bus setup time in xclk cycles. also the time that the data strobe is asserted in a cycle. free datasheet http:/// STMP36XX official product documentation 5/3/06 426 chapter 16: lcd interface (lcdif) 5-36xx-d1-1.02-050306 description: in 16-bit mode, either one or two 16-bi t data words can be written to the data reg- ister at once. in 8-bit transfer mode, one, tw o or four bytes can be written to this reg- ister. example: empty example. 16.5.4. lcd interface debug register description the lcd interface debug regist er provides a diagnostic view of the state machine and other useful internal signals. hw_lcdif_debug 0x80060030 table 557. hw_lcdif_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 data_three data_two data_one data_zero table 558. hw_lcdif_data bit field descriptions bits label rw reset definition 31:24 data_three rw 0x00 in 16-bit mode, this field contains the higher order byte of a 16-bit transfer. in 8-bit mode, this byte, if written, is sent last. 23:16 data_two rw 0x00 in 16-bit mode, this field contains the lower order byte of a 16-bit transfer. in 8-bit mode, this byte, if written, is sent third. 15:8 data_one rw 0x00 in 16-bit mode, this field contains the higher order byte of a 16-bit transfer. in 8-bit mode, this byte, if written, is sent second. 7:0 data_zero rw 0x00 in 16-bit mode, this field contains the lower order byte of a 16-bit transfer. in 8-bit mode, this byte, if written, is sent first. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 16: lcd interface (lcdif) 427 description: the lcd interface debug register is for diagnostic use only. example: empty example. lcdif xml revision: 1.33 table 559. hw_lcdif_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 busy last_subword subword_position empty_word state data_count table 560. hw_lcdif_debug bit field descriptions bits label rw reset definition 31:28 rsrvd1 ro 0x0 reserved bits. write as 0. 27 busy ro 0x00 read-only view of the input busy signal from the external lcd controller. 26 last_subword ro 0x00 read-only view of signal indicating last sub-word in current word is being transmitted. 25:24 subword_position ro 0x00 read-only view of poi nter to the current sub-word being transmitted. 23 empty_word ro 0x00 read-only view of the empty word signal. 22:16 state ro 0x00 read-only view of th e current state machine state. 15:0 data_count ro 0x00 read-only view of th e current state of the transmit word counter. free datasheet http:/// STMP36XX official product documentation 5/3/06 428 chapter 16: lcd interface (lcdif) 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 429 17. pin control and gpio this chapter describes the pin control and general-purpose input/output (gpio) pin interface implemented on the STMP36XX. it includes sections on pin multiplexing and drive strength selection, followed by a description of the gpio interface opera- tion. figure 74 and figure 75 , along with table 561 , ta b l e 5 6 2 , table 563 , and table 564 , illustrate the pin multiplexing pl an. programmable registers are described in section 17.6 . 17.1. overview the STMP36XX has 109 digital interface pins in the bga package, of which 48 are available on the qfp package. (in the context of this chapter, ?digital pin? means the 3.3-v standard digital interface pins. this does not include jtag, testmode, or digital radio interface pins.) each digital pin may be dynamically programmed at any time to be in one of the fol- lowing states: ? high-impedance (for input, three-state, or open-drain applications) ?low ?high ? controlled by one of 'n' chip hardware interface blocks, where 'n' is a pin- dependent number between 1 and 3, as described in section 17.2 . additionally, the state of each pin may be read at any time (no matter how it is con- figured), and its drive strength may be config ured to be 4 or 8 ma (or to be 4 or 16 ma for high current pins). each pin may also be used as an interrupt input, and the interrupt trigger type may be configured to be low level-sensitiv e, high level-sensi- tive, rising edge-sensitive , or falling edge-sensitive. for programming purposes, these 109 pins ar e divided into four banks of up to 32 pins each. the following sections show how to use all the features of each pin, and the pin register definitions are included in section 17.6 . 17.2. pin interface multiplexing the STMP36XX is somewhat pin-limited in the bga package, and severely pin-lim- ited in the qfp package. it contains a ri ch set of specialized hardware interfaces (spi, nand flash, nor flash, sdram, etc.), but does not have enough pins to allow use of all signals of all interfaces simultaneously. consequently, a pin multi- plexing scheme (the ?pin mux?) is employ ed to allow customers to choose which specialized interfaces to enable for their applications. in addition to these special- ized hardware interfaces, the STMP36XX allows any digital pin to be used as a gpio pin. this capability supports cust om interfacing requirements, such as the ability to communicate with leds, digital buttons, and other devices that are not directly supported by any of the stmp 36xx specialized ha rdware interfaces. each pin is connected to 1, 2, or 3 specializ ed hardware interfaces in addition to the gpio block. the description of each pin in chapter 35 , ?pin descriptions? on page 809 contains full details on which specia lized hardware interfaces are attached to that pin. for example, pin pwm0 (gpi o bank 3, bit 10) is shared between the pwm, etm, and debug uart hardware interfaces, so care must be taken when designing a system to ensure that these functions are not required simultaneously. free datasheet http:/// STMP36XX official product documentation 5/3/06 430 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 programs define which of the available ha rdware interfaces controls each pin by writing a two-bit field for that pin into one of the hw_pinct rl_muxselx registers, as shown in table 561 through table 564 . pin names are shown in the last row under each register. see also figure 74 and figure 75 . table 561. relation ship of muxselx registers to gpio bits to pin names: bank 0 gpio bank 0, pins 15-0 (reg muxsel0) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1514131211109876543210 gpmi_d15 gpmi_d14 gpmi _d13 gpmi_d12 gpmi_d11 gpmi_d10 gpmi_d09 gpmi_d08 gpmi_d07 gp mi_d06 gpmi_d05 gpmi_d04 gpmi_d 03 gpmi_d02 gpmi _d01 gpmi_d0 0 gpio bank 0, pins 31-16 (reg muxsel1) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ssp_ data3 ssp_ data2 ssp_ data1 ssp_ data0 ssp_sck ssp_cmd ssp_ detect gpmi_a2 gpmi_a1 gpmi_a0 gpmi_ wrn gpmi_ rdy2 gpmi_ rdy3 gpmi_ rdy gpmi_ rdn gpmi_irq table 562. relationsh ip of muxselx registers to gpio bits to pin names: bank 1 gpio bank 1, pins 15-0 (reg muxsel2) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1514131211109 876543210 lcd_d15 lcd_d14 lcd_d13 lcd_d12 lcd_d11 lcd_d10 lcd_d09 lcd_d08 lcd_d07 lcd_d06 lcd_d05 lcd_d04 lcd_d03 lcd_d02 lcd_d01 lcd_d00 gpio bank 1, pins 25-16 (reg muxsel3) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved reserved reserved reserved reserved reserved uartap_ tx uartap_ rx uartap_ rts uartap_ cts lcd_ busy gmpi_ reset m lcd_cs lcd_wr lcd_rs lcd_ reset free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 431 table 563. relation ship of muxselx registers to gpio bits to pin names: bank 2 gpio bank 2, pins 15-0 (reg muxsel4) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1514131211109876543210 emi_d15 emi_d14 emi_d13 emi_d12 emi_d11 emi_d10 emi_d09 emi_d08 emi_d07 emi_d06 emi_d05 emi_d04 emi_d03 emi_d02 emi_d01 emi_d00 gpio bank 2, pins 31-16 (reg muxsel5) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 emi_ rasn emi_a14 emi_a13 emi_a12 emi_a11 emi_a10 emi_a09 emi_a08 emi_a07 emi_a06 emi_a05 emi_a04 emi_a03 emi_a02 emi_a01 emi_a00 table 564. relationship of muxselx registers to gpio bits to pin names: bank 3 gpio bank 3, pins 15-0 (reg muxsel6) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1514131211109876543210 rotarya pwm4 pwm3 pwm2 pwm1 pwm0 emi_wen emi_ dom1 emi_ dom0 emi_ casn emi_cke emi_clk emi_ce3n smi_ce2n emi_ce1n emi_ce0n gpio bank 3, pins 18-16 (reg muxsel7) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved i2c_sda i2c_scl rotaryb free datasheet http:/// STMP36XX official product documentation 5/3/06 432 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 31 30 15 gpmi_d15 emi_a22 29 28 14 gpmi_d14 emi_a21 gpmi_ce2n* 27 26 13 gpmi_d13 emi_a20 25 24 12 gpmi_d12 emi_a19 23 22 11 21 20 10 19 18 9 17 16 8 15 14 7 13 12 6 11 10 5 9 8 4 7 6 3 5 4 2 3 2 1 1 0 0 31 30 31 29 28 30 27 26 29 25 24 28 23 22 27 21 20 26 19 18 25 17 16 24 15 14 23 13 12 22 11 10 21 9 8 20 7 6 19 5 4 18 3 2 17 1 0 16 muxsel0 gpio0 muxsel1 gpio0 gpmi_d11 emi_a18 gpmi_d10 emi_a17 gpmi_d9 emi_a16 gpmi_d8 emi_a15 gpmi_d7 erepair gpmi_d6 tm2 gpmi_d5 tm1 gpmi_d4 tm0 gpmi_d3 bm3 gpmi_d2 bm2 gpmi_d1 bm1 gpmi_d0 bm0 ssp_data3 ssp_data2 ssp_data1 ssp_data0 ssp_sck ssp_cmd ssp_detect rtck gpmi_a2 emi_a25 gpmi_a1 emi_a24 gpmi_a0 emi_a23 gpmi_wrn gpmi_rdy2 gpmi_rdy3 emi_oen gpmi_rdy gpmi_rdn gpmi_irq gpmi_ce1n* gpmi_ce0n* gpmi_ce3n* 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 muxsel0 gpio0 muxsel1 gpio0 bank 0 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 31 30 15 lcd_d15 etm_db7 rtck 29 28 14 lcd_d14 etm_db6 27 26 13 lcd_d13 etm_db5 25 24 12 lcd_d12 etm_db4 23 22 11 21 20 10 19 18 9 17 16 8 15 14 7 13 12 6 11 10 5 9 8 4 7 6 3 5 4 2 3 2 1 1 0 0 31 30 31 29 28 30 27 26 29 25 24 28 23 22 27 21 20 26 19 18 25 17 16 24 15 14 23 13 12 22 11 10 21 9 8 20 7 6 19 5 4 18 3 2 17 1 0 16 muxsel2 gpio1 muxsel3 gpio1 lcd_d11 etm_db3 lcd_d10 etm_db2 lcd_d9 etm_db1 lcd_d8 etm_db0 lcd_d7 etm_da7 lcd_d6 etm_da6 lcd_d5 etm_da5 lcd_d4 etm_da4 lcd_d3 etm_da3 lcd_d2 etm_da2 lcd_d1 etm_da1 lcd_d0 etm_da0 uartapp_tx ir_tx uartapp_rx ir_rx uartapp_rts rtck ir_clk uartapp_cts lcd_busy gpmi_resetn emi_reset lcd_cs etm_tclk lcd_wr etm_psa2 lcd_rs etm_psa0 lcd_reset etm_psa1 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 muxsel2 gpio1 muxsel3 gpio1 bank 1 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 power-up pin function ( general-purpose i/o ) unused key gpmi pins ssp pins emi pins lcd pins app uart pins ir pins etm/jtag pins i 2 c pins timrot pins pwm pins spdif pin dbg uart pins figure 74. pin control mux chart (banks 0 and 1) free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 433 power-up pin function ( general-purpose i/o ) unused key gpmi pins ssp pins emi pins lcd pins app uart pins ir pins etm/jtag pins i 2 c pins timrot pins pwm pins spdif pin dbg uart pins 31 30 15 emi_d15 29 28 14 emi_d14 27 26 13 emi_d13 25 24 12 emi_d12 23 22 11 21 20 10 19 18 9 17 16 8 15 14 7 13 12 6 11 10 5 9 8 4 7 6 3 5 4 2 3 2 1 1 0 0 31 30 31 29 28 30 27 26 29 25 24 28 23 22 27 21 20 26 19 18 25 17 16 24 15 14 23 13 12 22 11 10 21 9 8 20 7 6 19 5 4 18 3 2 17 1 0 16 muxsel4 gpio2 muxsel5 gpio2 emi_d11 emi_d10 emi_d9 emi_d8 emi_d7 emi_d6 emi_d5 emi_d4 emi_d3 emi_d2 emi_d1 emi_d0 emi_rasn emi_a14 emi_a13 emi_a12 emi_a11 emi_a10 emi_a9 emi_a08 emi_a7 emi_a6 emi_a5 emi_a4 emi_a3 emi_a2 emi_a1 emi_a0 bank 2 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 muxsel4 gpio2 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 muxsel5 gpio2 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 31 30 15 rotarya 29 28 14 pwm4 etm_psb1 27 26 13 pwm3 etm_psb0 spkr_spdif 25 24 12 pwm2 etm_psb2 rtck 23 22 11 21 20 10 19 18 9 17 16 8 15 14 7 13 12 6 11 10 5 9 8 4 7 6 3 5 4 2 3 2 1 1 0 0 31 30 31 29 28 30 27 26 29 25 24 28 23 22 27 21 20 26 19 18 25 17 16 24 15 14 23 13 12 22 11 10 21 9 8 20 7 6 19 5 4 18 3 2 17 1 0 16 muxsel6 gpio3 muxsel7 gpio3 pwm1 etm_tsyncb uartdbg_tx pwm0 etm_tsynca uartdbg_rx emi_wen emi_dqm1 emi_dqm0 emi_casn emi_cke emi_clk emi_ce3n gpmi_ce3n emi_ce2n gpmi_ce2n emi_ce1n gpmi_ce1n emi_ce0n gpmi_ce0n i2c_sda i2c_scl rotaryb bank 3 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 muxsel6 gpio3 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 muxsel7 gpio3 0 0 1 1 0 0 1 1 pin function 0 muxsel= muxsel= muxsel= pin function 1 pin function 2 muxsel= pin function 3 figure 75. pin control mux chart (banks 2 and 3) free datasheet http:/// STMP36XX official product documentation 5/3/06 434 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 readback registers are never affe cted by the operation of the hw_pinctrl_muxselx registers and alwa ys sense the actual value on the data pin. for example, if a pin is programmed to be a gpio output and then driven high, any specialized hardware interfaces that are actively monitoring that pin will read the high logic value. conversely, if the pin mux is programmed to give a specialized hardware interface such as the emi block control of a particular pin, the current state of that pin can be read through its gp io read register at any time, even while active emi cycles are in progress. because the pin mux configuration is indepe ndent for each individual pin, any pin not required for a given active interface c an be reused as a gpio pin. for example, the emi_ce0n pin can be configured and controlled as a gpio pin, while the other emi interface pins are controlled by the emi block. 17.3. pin drive strength selection each digital pin can be programmed to drive at either 4 or 8 ma by setting the bit corresponding to that pin in one of the hw_pinctrl_drivex registers. there are two exceptions to this behavior. the pwm3 and pwm4 pins have higher drive capa- bility and will drive at 16 ma wh en the 8-ma setti ng is selected. 17.4. gpio interface the registers discussed in the following se ctions exist within each of these four banks to configure the chip?s digital pins. some pins only exist in the 169-pin pack- age options. the registers that control thos e pins exist but perform no useful func- tion when in a 100-pin package. 17.4.1. output operation programming and controlling a digital pin as a gpio output is accomplished by pro- gramming the appropriate bits in four registers, as shown in figure 76 . ? after setting the field in the hw_p inctrl_muxselx to program for gpio control, the hw_pinctrl_drivex regist er bit is set for the desired drive strength. ? the hw_pinctrl _doutx register bit is then lo aded with the level that will initially be driven on the pin. ? finally, the hw_pinctrl_doex register bit is set. ? once set, the logic value the hw_pinctrl _doutx bit will be driven on the pin and the value can be toggled with repeated writes. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 435 17.4.2. input operation any digital pin may be used as a gpio input by programming its hw_pinctrl_muxselx field to 3 to enable gpio mode, programming its hw_pinctrl_doex field to 0 to disable output, and then reading from the hw_pinctrl_dinx register, as shown in figure 77 . note that because of clock synchronization issues, the logic levels read from the hw_pinctrl_dinx registers are delayed from the pins by two apbx clock cycles. figure 76. gpio output setup flowchart write to hw_pinctrl_muxselx register bit to select pin as gpio. write to hw_pinctrl_doutx register bit to set the output value to drive on the pin. re-write the hw_pinctrl_doutx register bit to change the value driven on the pin. write to hw_pinctrl_doex register bit to enable the data value to be driven on the pin. write to hw_pinctrl_drivex register bit to set current drive strength. begin end free datasheet http:/// STMP36XX official product documentation 5/3/06 436 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 17.4.3. input interrupt operation programming and controlling a digital pin as a gpio interrupt i nput is accomplished by programming the appropriate bits in six registers, as shown in figure 78 . ? after setting the hw_pinctrl_m uxselx register for gpio, the hw_pinctrl_irqlevelx and hw_pinct rl_irqpolx registers set the interrupt trigger mode. a gp io interrupt pin can be programmed in one of four trigger detect modes: positive edge, negative edge, positive level, and negative level triggered. ? the hw_pinctrl_irqstatx register bit sh ould then be cleared to ensure that there are no interrupts pending when enabled. ? setting the hw_pinctrl_pin 2irqx register bit will then set up the pin to be an interrupt pin. ? at this point, if an interrupt event occurs on the pin, it will be sensed and recorded in the appropriate hw_pinctrl_irqstatx bit. ? however, the interrupt will not be communicat ed back to the in terrupt collector until the hw_pinctrl_irqenx register bit is enabled. figure 79 shows the logic diagram for the interrupt-generation circuit. figure 77. gpio input setup flowchart write to hw_pinctrl_muxselx register bit to select pin as gpio. read hw_pinctrl_dinx register bit to get the value on the pin. write zero to hw_pinctrl_doex register bit to ensure pin is selected as an input. begin end free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 437 write to hw_pinctrl_muxselx register bit to select pin as gpio. write to hw_pinctrl_irqpolx register bit to set high or low logic assertion. write to hw_pinctrl_irqenx register bit to enable the interrupt signal back to the interrupt collector. write to hw_pinctrl_pin2irqx register bit to enable as an interrupt pin. write zero to hw_pinctrl_irqstatx register bit to clear interrupts. write to hw_pinctrl_irqlevelx register bit to set level or edge assertion. begin end write zero to hw_pinctrl_doex register bit to ensure pin is selected as an input. figure 78. gpio interrupt flowchart free datasheet http:/// STMP36XX official product documentation 5/3/06 438 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 17.5. behavior during reset a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. hw_pinctrl_dinxb pin gpxbb sync hw_pinctrl_irqpolxb rise fall low high hw_pinctrl_irqlevelxb hw_pinctrl_statxb hw_pinctrl_irqenxb level pinctrl_irqx to cpu sct clear write to gpiox & (apb_wdata[b]== 1) 1 from other 31 bits hw_pinctrl_pin2irqxb edge internal register hw_pinctrl_ctrl [hw_pinctrl_ctrl_irqoutb] figure 79. gpio interrupt generation free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 439 17.6. programmable registers the following programmable r egisters are available for controlling the pin control and gpio interface of the STMP36XX. 17.6.1. pinctrl block control register description the pinctrl block control register contains the block control bits and combined interrupt output status for each pinctrl bank. hw_pinctrl_ctrl 0x80018000 hw_pinctrl_ctrl_set 0x80018004 hw_pinctrl_ctrl_clr 0x80018008 hw_pinctrl_ctrl_tog 0x8001800c table 565. hw_pinctrl_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate present3 present2 present1 present0 rsrvd1 irqout3 irqout2 irqout1 irqout0 table 566. hw_pinctrl_ctr l bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 this bit must be set to zero to enable operation of any of the pinctrl banks. when set to one, it forces a block-level reset. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it disables the block clock. 29 present3 ro 0x1 gpio functionality present. 0: gpio functionality for pin control bank 3 is not present in this product. 1: gpio functionality for bank 3 is present. 28 present2 ro 0x1 gpio functionality present. 0: gpio functionality for pin control bank 2 is not present in this product. 1: gpio functionality for bank 2 is present. 27 present1 ro 0x1 gpio functionality present. 0: gpio functionality for pin control bank 1 is not present in this product. 1: gpio functionality for bank 1 is present. 26 present0 ro 0x1 gpio functionality present. 0: gpio functionality for pin control bank 0 is not present in this product. 1: gpio functionality for bank 0 is present. 25:4 rsrvd1 ro 0x000000 always write zeroes to this field. 3 irqout3 ro 0x0 read-only view of the interrupt collector gpio3 signal, sourced from the combined irq outputs from bank 3. 2 irqout2 ro 0x0 read-only view of the interrupt collector gpio2 signal, sourced from the combined irq outputs from bank 2. free datasheet http:/// STMP36XX official product documentation 5/3/06 440 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: this register contains block-wide control bits and combined bank interrupt status bits. for normal operation, write a 0x00000000 into this register. example: empty example. 17.6.2. pinctrl bank 0 lower pin mux select register description the pinctrl bank 0 lower pin mux select register provides pin function selec- tion for pins 0 through 15 of bank 0. hw_pinctrl_muxsel0 0x80018010 hw_pinctrl_muxsel0_set 0x80018014 hw_pinctrl_muxsel0_clr 0x80018018 hw_pinctrl_muxsel0_tog 0x8001801c description: this register allows the programmer to select which hardware interface blocks drive the first sixteen pins in bank 0. for example, if this register is set to 0x0000002c, the second pin in the bank (gpio0[1]) will be set to gpio mode, the third pin in the bank will be set to its second alternate functi on mode, and bank pins 0 and 3-15 will be set to their primary function modes. 1 irqout1 ro 0x0 read-only view of the interrupt collector gpio1 signal, sourced from the combined irq outputs from bank 1. 0 irqout0 ro 0x0 read-only view of the interrupt collector gpio0 signal, sourced from the combined irq outputs from bank 0. table 567. hw_pinctrl_muxsel0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 func_sel table 568. hw_pinctrl_mu xsel0 bit field descriptions bits label rw reset definition 31:0 func_sel rw 0xffffffff this field selects which hardware interface block controls each of the first 16 pins in bank 0. this field is divided into sixteen 2-bit subfields, with bits [1:0] corresponding to pin 0, bits [3:2] corresponding to pin 1, etc. subfield definitions: 00= default peripheral 01= alternate peripheral1 or undefined 10= alternate peripheral2 or undefined 11= gpio table 566. hw_pinctrl_ctr l bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 441 see the table in the pin interface multip lexing section earlier in this chapter for information about pin-to-gpio bank mapping. example: empty example. 17.6.3. pinctrl bank 0 upper pin mux select register description the pinctrl bank 0 upper pin mux select register provides pin function selec- tion for pins 16 through 31 of bank 0. hw_pinctrl_muxsel1 0x80018020 hw_pinctrl_muxsel1_set 0x80018024 hw_pinctrl_muxsel1_clr 0x80018028 hw_pinctrl_muxsel1_tog 0x8001802c description: this register allows the programmer to select which hardware interface blocks drive the last sixteen pins in bank 0. for example, if this register is set to 0x00000003, the sixt eenth pin in the ba nk (gpio0[16]) will be set to gpio mode and bank pins 17-31 will be set to their primary function mode. see the table in the pin interface multip lexing section earlier in this chapter for information about pin-to-gpio bank mapping. example: empty example. 17.6.4. pinctrl bank 0 drive strength register description the pinctrl bank 0 drive strength regist er selects the current drive strength for pins in bank 0. hw_pinctrl_drive0 0x80018030 hw_pinctrl_drive0_set 0x80018034 hw_pinctrl_drive0_clr 0x80018038 table 569. hw_pinctrl_muxsel1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 func_sel table 570. hw_pinctrl_mu xsel1 bit field descriptions bits label rw reset definition 31:0 func_sel rw 0xffffffff this field selects which hardware interface block controls each of the last 16 pins in bank 0. this field is divided into sixteen 2-bit subfields, with bits [1:0] corresponding to pin 16, bits [3:2] corresponding to pin 17, etc. subfield definitions: 00= default peripheral 01= alternate peripheral1 or undefined 10= alternate peripheral2 or undefined 11= gpio free datasheet http:/// STMP36XX official product documentation 5/3/06 442 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 hw_pinctrl_drive0_tog 0x8001803c description: the pinctrl bank 0 drive strength register selects the drive strength (4 ma or 8 ma) for pins in bank 0 that are configured fo r output. for example, if this register is set to 0x10000004, then bank 0 pins 2 and 28 will be set to 8-ma driv e strength and the rest of the pins in the bank will be set to 4-ma drive strength. example: empty example. 17.6.5. pinctrl bank 0 data output register description the bank 0 data output register provides data for all pins in bank 0 that are config- ured for gpio output mode. hw_pinctrl_dout0 0x80018050 hw_pinctrl_dout0_set 0x80018054 hw_pinctrl_dout0_clr 0x80018058 hw_pinctrl_dout0_tog 0x8001805c description: this register contains the data that will be driven out a ll bank 0 pins that are config- ured for gpio output mo de. for example, if hw_pinctrl_muxsel0 contains 0x0000000f and hw_pinctrl_doe0 contai ns 0x00000001, then gpio0[0] will table 571. hw_pinctrl_drive0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 drive8ma table 572. hw_pinctrl_dri ve0 bit field descriptions bits label rw reset definition 31:0 drive8ma rw 0x00000000 this field selects the drive strength for pins configured as outputs. each bit in this register corresponds to one of the 32 pins in bank 0: 0= 4-ma drive strength 1= 8-ma drive strength table 573. hw_pinctrl_dout0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dataout table 574. hw_pinctrl_dout0 bit field descriptions bits label rw reset definition 31:0 dataout rw 0x00000000 this field selects the output value (0 or 1) for pins configured as gpio outputs. each bit in this register corresponds to one of the 32 pins in bank 0. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 443 be driven with the value from bit 0 of this register, gpio0[1] w ill not be driven, and gpio0[2:15] will be controlled by th e associated primary interfaces. example: empty example. 17.6.6. pinctrl bank 0 data input register description the current value of all bank 0 pins may be read from the pinctrl bank 0 data input register. hw_pinctrl_din0 0x80018060 hw_pinctrl_din0_set 0x80018064 hw_pinctrl_din0_clr 0x80018068 hw_pinctrl_din0_tog 0x8001806c description: this register reflects the current values of all the bank 0 pins. the register accu- rately reflects the state of the pin, regardless of the setting of the hw_pinctrl_muxselx or hw_pinctrl_doe x registers. but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the hw_pinctrl_muxselx register should be set to 3 (gpio mode) and the pin's bit in the hw_pinctrl_doex register should be set to 0 (disabled) to ensure that the chip is not driving the pin. for example, if hw_pinctrl_muxsel0 contains 0x0000000f and hw_pinctrl_doe0 contains 0x00000001, th en pin gpio0[1] will be an input pin, and bit 1 of this register will reflect its current state. example: empty example. 17.6.7. pinctrl bank 0 output enable register description the pinctrl bank 0 output enable regist er controls the output enable signal for all pins in bank 0 that are configured for gpio mode. hw_pinctrl_doe0 0x80018070 hw_pinctrl_doe0_set 0x80018074 hw_pinctrl_doe0_clr 0x80018078 hw_pinctrl_doe0_tog 0x8001807c table 575. hw_pinctrl_din0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 datain table 576. hw_pinctrl_din 0 bit field descriptions bits label rw reset definition 31:0 datain ro 0x00000000 each bit in this read-only register corresponds to one of the 32 pins in bank 0. the current state of each pin in bank 0, synchronized to hclk, may be read here. free datasheet http:/// STMP36XX official product documentation 5/3/06 444 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: for pins in bank 0 that are configured as gpios (by setting the pin's control field in hw_pinctrl_muxsel0/1 to 3) , a 1 in this register will enable the corresponding bit value from hw_pinctrl_dout0 to be dr iven out the pin, and a 0 in this regis- ter will disable the corresponding driver . for example, if hw_pinctrl_muxsel0 contains 0x0000000f and hw_pinctrl_d oe0 contains 0x00000001, then pin gpio0[0] will be driven with the value from hw_pin ctrl_dout0 bit 0, pin gpio0[1] will be three-stated , and pins gpio0[2-15] will be controlled by the default peripheral interface associated with each of those pins. example: empty example. 17.6.8. pinctrl bank 0 interrupt select register description the bank 0 interrupt select register selects which of the bank 0 pins may be used as interrupt sources. hw_pinctrl_pin2irq0 0x80018080 hw_pinctrl_pin2irq0_set 0x80018084 hw_pinctrl_pin2irq0_clr 0x80018088 hw_pinctrl_pin2irq0_tog 0x8001808c description: table 577. hw_pinctrl_doe0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dataoe table 578. hw_pinctrl_doe0 bit field descriptions bits label rw reset definition 31:0 dataoe rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 0. setting a bit in this register to one allows the STMP36XX to drive the corresponding pin in gpio mode. table 579. hw_pinctrl_pin2irq0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 enable2irq table 580. hw_pinctrl_pin 2irq0 bit field descriptions bits label rw reset definition 31:0 enable2irq rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 0: 0= deselect the pin's interrupt functionality. 1= select the pin to be used as an interrupt source. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 445 as described earlier in this chapter, any digital i/o pin can be used as an interrupt source. this register selects which pins in bank 0 can be used to generate inter- rupts. if the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the hw_pinctrl_irqlevel0 and hw_pinctrl_irqpol0 regi sters) will set the corr esponding bit in the hw_pinctrl_irqstat0 register. if the pin is additionally enabled in the hw_pinctrl_irqen0 re gister, then the in terrupt will be prop agated to the inter- rupt collector as interrupt gpio0. for example, if this register contai ns 0x00000014, then pins gpio0[2] and gpio0[4] can be used as in terrupt pins, and no other pins in bank 0 will cause bits to be set in the hw_pinctrl_irqstat0 register. example: empty example. 17.6.9. pinctrl bank 0 interrupt mask register description the pinctrl bank 0 interrupt mask regist er contains interrupt enable masks for the pins in bank 0. hw_pinctrl_irqen0 0x80018090 hw_pinctrl_irqen0_set 0x80018094 hw_pinctrl_irqen0_clr 0x80018098 hw_pinctrl_irqen0_tog 0x8001809c description: as described earlier in this chapter, any digital i/o pin can be used as an interrupt source. this register masks the interrupt sour ces from the pins in bank 0. if a bit is set in this register and the same bit is set in hw_pinctrl_irqstat0, an interrupt will be propagated to the interrupt collector as interrupt gpio0. for example, if this register contai ns 0x00000014, then only bits 2 and 4 in hw_pinctrl_irqstat0 (corresponding to pins gpio0[2] and gpio0[4]) will cause interrupts from bank 0. example: empty example. table 581. hw _pinctrl_irqen0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 irqenable table 582. hw_pinctrl_irq en0 bit field descriptions bits label rw reset definition 31:0 irqenable rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 0: 1= enable interrupts from the corresponding bit in hw_pinctrl_irqstat0. 0= disable interrupts from the corresponding bit in hw_pinctrl_irqstat0. free datasheet http:/// STMP36XX official product documentation 5/3/06 446 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 17.6.10. pinctrl bank 0 interrupt level/edge register description the pinctrl bank 0 interrupt level/edge register selects level or edge sensitivity for interrupt requests for the pins in bank 0. hw_pinctrl_irqlevel0 0x800180a0 hw_pinctrl_irqlevel0_set 0x800180a4 hw_pinctrl_irqlevel0_clr 0x800180a8 hw_pinctrl_irqlevel0_tog 0x800180ac description: this register selects level or edge detection for interrupt generation. each pin in bank 0 that is configured for interrupt generation can be independently set to inter- rupt on low level, high level, rising edge, or falling edge by setting bits in this register and hw_pinctrl_irqpol0 (see below) appropriately. example: empty example. 17.6.11. pinctrl bank 0 interrupt polarity register description the pinctrl bank 0 interrupt polarity regi ster selects the pola rity for interrupt requests for the pins in bank 0. hw_pinctrl_irqpol0 0x800180b0 hw_pinctrl_irqpol0_set 0x800180b4 hw_pinctrl_irqpol0_clr 0x800180b8 hw_pinctrl_irqpol0_tog 0x800180bc table 583. hw_p inctrl_irqlevel0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bitirqlevel table 584. hw_pinctrl_irq level0 bit field descriptions bits label rw reset definition 31:0 bitirqlevel rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 0: 1= level detection 0= edge detection table 585. hw_pinctrl_irqpol0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 irqpol free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 447 description: this register selects the polarity for in terrupt generation. each pin in bank 0 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or fa lling edge by setting this register and hw_pinctrl_irqlevel0 (see above) appropriately. example: empty example. 17.6.12. pinctrl bank 0 interrupt status register description the pinctrl bank 0 interrupt status regist er reflects pending interrupt status for the pins in bank 0. hw_pinctrl_irqstat0 0x800180c0 hw_pinctrl_irqstat0_set 0x800180c4 hw_pinctrl_irqstat0_clr 0x800180c8 hw_pinctrl_irqstat0_tog 0x800180cc description: this register reflects the pending interrupt status for pins in bank 0. bits in this reg- ister are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling e dge) occurs on a bank 0 pin that has been enabled as an interrupts source in the hw_pinctrl_pin 2irq0 register. software may clear any bit in this register by writing a 1 to the bit at the sct clear address, e.g., hw_pinctrl_irqstat0_clr. status bits fo r pins configured as level-sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in hw_pinctrl_pin2irq0. table 586. hw_pinctrl_irqpo l0 bit field descriptions bits label rw reset definition 31:0 irqpol rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 0: 0= low or falling edge 1= high or rising edge table 587. hw_pinctrl_irqstat0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 stat table 588. hw_pinctrl_irq stat0 bit field descriptions bits label rw reset definition 31:0 stat rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 0: 0= no interrupt pending 1= interrupt pending free datasheet http:/// STMP36XX official product documentation 5/3/06 448 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 if a bit is set in this register, and the corresponding bit is also set in the hw_pincntrl_irqen0 mask register, then the gpio0 interrupt will be asserted to the interrupt collector. example: empty example. 17.6.13. pinctrl bank 1 lower pin mux select register description the pinctrl bank 1 lower pin mux select register provides pin function selec- tion for pins 0 through 15 of bank 1. hw_pinctrl_muxsel2 0x80018110 hw_pinctrl_muxsel2_set 0x80018114 hw_pinctrl_muxsel2_clr 0x80018118 hw_pinctrl_muxsel2_tog 0x8001811c description: this register allows the programmer to select which hardware interface blocks drive the first sixteen pins in bank 1. for example, if this register is set to 0x0000002c, the second pin in the bank (gpio1[1]) will be set to gpio mode, the third pin in the bank will be set to its se cond alternate functi on mode, and bank 1 pins 0 and 3-15 will be set to their primary function modes. see the table in the pin interface multip lexing section earlier in this chapter for information about pin to gpio bank mapping. example: empty example. 17.6.14. pinctrl bank 1 upper pin mux select register description the pinctrl bank 1 upper pin mux select register provides pin function selec- tion for pins 16 through 25 of bank 1. hw_pinctrl_muxsel3 0x80018120 table 589. hw_pinctrl_muxsel2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 func_sel table 590. hw_pinctrl_mu xsel2 bit field descriptions bits label rw reset definition 31:0 func_sel rw 0xffffffff this field selects which hardware interface block controls each of the first 16 pins in bank 1. this field is divided into sixteen 2-bit subfields, with bits [1:0] corresponding to pin 0, bits [3:2] corresponding to pin 1, etc. subfield definitions: 00= default peripheral 01= alternate peripheral1 or undefined 10= alternate peripheral2 or undefined 11= gpio. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 449 hw_pinctrl_muxsel3_set 0x80018124 hw_pinctrl_muxsel3_clr 0x80018128 hw_pinctrl_muxsel3_tog 0x8001812c description: this register allows the programmer to select which hardware interface blocks drive the last 10 pins in bank 1. for exam ple, if this register is set to 0x00000003, the sixteenth pin in the bank (gpio1[16]) will be set to gpio mode and bank 1 pins 17-25 will be set to thei r primary function mode. see the table in the pin interface multip lexing section earlier in this chapter for information about pin to gpio bank mapping. example: empty example. 17.6.15. pinctrl bank 1 drive strength register description the pinctrl bank 1 drive strength regist er selects the current drive strength for pins in bank 1. hw_pinctrl_drive1 0x80018130 hw_pinctrl_drive1_set 0x80018134 hw_pinctrl_drive1_clr 0x80018138 hw_pinctrl_drive1_tog 0x8001813c table 591. hw_pinctrl_muxsel3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 func_sel table 592. hw_pinctrl_mu xsel3 bit field descriptions bits label rw reset definition 31:20 rsrvd1 ro 0x0 always write zeroes to this field. 19:0 func_sel rw 0xfffff this field selects which hardware interface block controls each of the last 10 pins in bank 1. this field is divided into ten 2 bit subfields, with bits [1:0] corresponding to pin 16, bits [3:2] corresponding to pin 17, etc. subfield definitions: 00= default peripheral 01= alternate peripheral1 or undefined 10= alternate peripheral2 or undefined 11= gpio free datasheet http:/// STMP36XX official product documentation 5/3/06 450 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: the pinctrl bank 1 drive strength register selects the drive strength (4 ma or 8 ma) for pins in bank 1 that are configured for output. example: empty example. 17.6.16. pinctrl bank 1 data output register description the pinctrl bank 1 data output register pr ovides data for all pins in bank 1 that are configured for gpio output mode. hw_pinctrl_dout1 0x80018150 hw_pinctrl_dout1_set 0x80018154 hw_pinctrl_dout1_clr 0x80018158 hw_pinctrl_dout1_tog 0x8001815c table 593. hw_pinctrl_drive1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 drive8ma table 594. hw_pinctrl_dri ve1 bit field descriptions bits label rw reset definition 31:26 rsrvd1 ro 0x0 always write zeroes to this field. 25:0 drive8ma rw 0x0 this field selects the drive strength for pins configured as outputs. this field is segmented into 1 bit per pin subfields, with bit 0 corresponding to bank 1 pin 0, bit 1 corresponding to pin 1, etc. subfield definitions: 0= 4-ma drive strength 1= 8-ma drive strength table 595. hw_pinctrl_dout1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 dataout free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 451 description: this register contains the data that will be driven out all bank 1 pins which are con- figured for gpio output mode. for exam ple, if hw_pinctrl_muxsel2 contains 0x0000000f and hw_pinctrl_doe1 contai ns 0x00000001, then gpio1[0] will be driven with the value from bit 0 of this register, gpio1[1] w ill not be driven, and gpio1[2:15] will be controlled by th e associated primary interfaces. example: empty example. 17.6.17. pinctrl bank 1 data input register description the current value of all bank 1 pins may be read from the pinctrl bank 1 data input register. hw_pinctrl_din1 0x80018160 hw_pinctrl_din1_set 0x80018164 hw_pinctrl_din1_clr 0x80018168 hw_pinctrl_din1_tog 0x8001816c description: this register reflects the current values of all the bank 1 pins. the register accu- rately reflects the state of the pin, regardless of the setting of the hw_pinctrl_muxselx or hw_pinctrl_doe x registers. but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the hw_pinctrl_muxselx register should be set to 3 (gpio mode) and the pin's bit in the hw_pinctrl_doex register should be set to 0 (disabled) to ensure that the chip is not driving the pin. table 596. hw_pinctrl_dout1 bit field descriptions bits label rw reset definition 31:26 rsrvd1 ro 0x0 always write zeroes to this field. 25:0 dataout rw 0x0 this field selects the output value (0 or 1) for pins configured as gpio outputs. each bit in this register corresponds to one of the 26 pins in bank 1. table 597. hw_pinctrl_din1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 datain table 598. hw_pinctrl_din 1 bit field descriptions bits label rw reset definition 31:26 rsrvd1 ro 0x0 always write zeroes to this field. 25:0 datain ro 0x0 each bit in this read-only register corresponds to one of the 26 pins in bank 1. the current state of each pin in bank 1, synchronized to hclk, may be read here. free datasheet http:/// STMP36XX official product documentation 5/3/06 452 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 for example, if hw_pinctrl_muxsel2 contains 0x0000000f and hw_pinctrl_doe1 contains 0x00000001, th en pin gpio1[1] will be an input pin, and bit 1 of this register will reflect its current state. example: empty example. 17.6.18. pinctrl bank 1 output enable register description the pinctrl bank 1 output enable regist er controls the output enable signal for all pins in bank 1 that are configured for gpio mode. hw_pinctrl_doe1 0x80018170 hw_pinctrl_doe1_set 0x80018174 hw_pinctrl_doe1_clr 0x80018178 hw_pinctrl_doe1_tog 0x8001817c description: for pins in bank 1 that are configured as gpios (by setting the pin's control field in hw_pinctrl_muxsel2/3 to 3) , a 1 in this register will enable the corresponding bit value from hw_pinctrl_dout1 to be driv en on the pin, and a 0 in this register will disable the corresponding driver. for example, if hw_pinctrl_muxsel2 contains 0x0000000f and hw_pinctrl_d oe1 contains 0x00000001, then pin gpio1[0] will be driven with the value from hw_pin ctrl_dout1 bit 0, pin gpio1[1] will be three-stated , and pins gpio1[2-15] will be controlled by the default peripheral interface associated with each of those pins. example: empty example. 17.6.19. pinctrl bank 1 interrupt select register description the pinctrl bank 1 interrupt select regist er selects which of the bank 1 pins may be used as interrupt sources. hw_pinctrl_pin2irq1 0x80018180 hw_pinctrl_pin2irq1_set 0x80018184 table 599. hw_pinctrl_doe1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 dataoe table 600. hw_pinctrl_doe1 bit field descriptions bits label rw reset definition 31:26 rsrvd1 ro 0x0 always write zeroes to this field. 25:0 dataoe rw 0x0 each bit in this register corresponds to one of the 26 pins in bank 1. setting a bit in this register to one allows the STMP36XX to drive the corresponding pin in gpio mode. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 453 hw_pinctrl_pin2irq1_clr 0x80018188 hw_pinctrl_pin2irq1_tog 0x8001818c description: as described earlier in this chapter, any digital i/o pin can be used as an interrupt source. this register selects which pins in bank 1 can be used to generate inter- rupts. if the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the hw_pinctrl_irqlevel1 and hw_pinctrl_irqpol1 regi sters) will set the corr esponding bit in the hw_pinctrl_irqstat1 register. if the pin is additionally enabled in the hw_pinctrl_irqen1 re gister, then the in terrupt will be prop agated to the inter- rupt collector as interrupt gpio1. for example, if this register contai ns 0x00000014, then pins gpio1[2] and gpio1[4] can be used as in terrupt pins, and no other pins in bank 1 will cause bits to be set in the hw_pinctrl_irqstat1 register. example: empty example. 17.6.20. pinctrl bank 1 interrupt mask register description the pinctrl bank 1 interrupt mask regist er contains interrupt enable masks for the pins in bank 1. hw_pinctrl_irqen1 0x80018190 hw_pinctrl_irqen1_set 0x80018194 hw_pinctrl_irqen1_clr 0x80018198 hw_pinctrl_irqen1_tog 0x8001819c table 601. hw_pinctrl_pin2irq1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 enable2irq table 602. hw_pinctrl_pin 2irq1 bit field descriptions bits label rw reset definition 31:26 rsrvd1 ro 0x0 always write zeroes to this field. 25:0 enable2irq rw 0x0 each bit in this register corresponds to one of the 26 pins in bank 1: 0= deselect the pin's interrupt functionality. 1= select the pin to be used as an interrupt source. free datasheet http:/// STMP36XX official product documentation 5/3/06 454 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: as described earlier in this chapter, any digital i/o pin can be used as an interrupt source. this register masks the interrupt sour ces from the pins in bank 1. if a bit is set in this register and the same bit is set in hw_pinctrl_irqstat1, an interrupt will be propagated to the interrupt collector as interrupt gpio1. for example, if this register contai ns 0x00000014, then only bits 2 and 4 in hw_pinctrl_irqstat1 (corresponding to pins gpio1[2] and gpio1[4]) will cause interrupts from bank 1. example: empty example. 17.6.21. pinctrl bank 1 interrupt level/edge register description the pinctrl bank 1 interrupt level/edge register selects level or edge sensitivity for interrupt requests for the pins in bank 1. hw_pinctrl_irqlevel1 0x800181a0 hw_pinctrl_irqlevel1_set 0x800181a4 hw_pinctrl_irqlevel1_clr 0x800181a8 hw_pinctrl_irqlevel1_tog 0x800181ac table 603. hw _pinctrl_irqen1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 irqenable table 604. hw_pinctrl_irq en1 bit field descriptions bits label rw reset definition 31:26 rsrvd1 ro 0x0 always write zeroes to this field. 25:0 irqenable rw 0x0 each bit in this register corresponds to one of the 26 pins in bank 1: 1= enable interrupts from the corresponding bit in hw_pinctrl_irqstat1. 0= disable interrupts from the corresponding bit in hw_pinctrl_irqstat1. table 605. hw_p inctrl_irqlevel1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 bitirqlevel free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 455 description: this register selects level or edge detection for interrupt generation. each pin in bank 1 that is configured for interrupt generation can be independently set to inter- rupt on low level, high level, rising edge, or falling edge by setting bits in this register and hw_pinctrl_irqpol1 (see below) appropriately. example: empty example. 17.6.22. pinctrl bank 1 interrupt polarity register description the pinctrl bank 1 interrupt polarity regi ster selects the pola rity for interrupt requests for the pins in bank 1. hw_pinctrl_irqpol1 0x800181b0 hw_pinctrl_irqpol1_set 0x800181b4 hw_pinctrl_irqpol1_clr 0x800181b8 hw_pinctrl_irqpol1_tog 0x800181bc description: this register selects the polarity for interrupt generation. each pin in bank 1 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or fa lling edge by setting this register and hw_pinctrl_irqlevel1 (see above) appropriately. example: table 606. hw_pinctrl_irq level1 bit field descriptions bits label rw reset definition 31:26 rsrvd1 ro 0x0 always write zeroes to this field. 25:0 bitirqlevel rw 0x0 each bit in this register corresponds to one of the 26 pins in bank 1: 1= level detection 0= edge detection table 607. hw_pinctrl_irqpol1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 irqpol table 608. hw_pinctrl_irqpo l1 bit field descriptions bits label rw reset definition 31:26 rsrvd1 ro 0x0 always write zeroes to this field. 25:0 irqpol rw 0x0 each bit in this register corresponds to one of the 26 pins in bank 1: 0= low or falling edge 1= high or rising edge free datasheet http:/// STMP36XX official product documentation 5/3/06 456 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 empty example. 17.6.23. pinctrl bank 1 interrupt status register description the pinctrl bank 1 interrupt status regist er reflects pending interrupt status for the pins in bank 1. hw_pinctrl_irqstat1 0x800181c0 hw_pinctrl_irqstat1_set 0x800181c4 hw_pinctrl_irqstat1_clr 0x800181c8 hw_pinctrl_irqstat1_tog 0x800181cc description: this register reflects the pending interrupt status for pins in bank 1. bits in this reg- ister are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling e dge) occurs on a bank 1 pin that has been enabled as an interrupt source in the hw _pinctrl_pin2irq1 register. software may clear any bit in this register by writing a 1 to the bit at the sct clear address, e.g., hw_pinctrl_irqstat1_clr. status bits fo r pins configured as level-sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in hw_pinctrl_pin2irq1. if a bit is set in this register, and the corresponding bit is also set in the hw_pincntrl_irqen1 mask register, then the gpio1 interrupt will be asserted to the interrupt collector. example: empty example. 17.6.24. pinctrl bank 2 lower pin mux select register description the pinctrl bank 2 lower pin mux select register provides pin function selec- tion for pins 0 through 15 of bank 2. hw_pinctrl_muxsel4 0x80018210 hw_pinctrl_muxsel4_set 0x80018214 hw_pinctrl_muxsel4_clr 0x80018218 table 609. hw_pinctrl_irqstat1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 stat table 610. hw_pinctrl_irq stat1 bit field descriptions bits label rw reset definition 31:26 rsrvd1 ro 0x0 always write zeroes to this field. 25:0 stat rw 0x0 each bit in this register corresponds to one of the 26 pins in bank 1: 0= no interrupt pending 1= interrupt pending free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 457 hw_pinctrl_muxsel4_tog 0x8001821c description: this register allows the programmer to select which hardware interface blocks drive the first sixteen pins in bank 2. for example, if this register is set to 0x0000002c, the second pin in the bank (gpio2[1]) will be set to gpio mode, the third pin in the bank will be set to its se cond alternate functi on mode, and bank 2 pins 0 and 3-15 will be set to their primary function modes. see the table in the pin interface multip lexing section earlier in this chapter for information about pin to gpio bank mapping. example: empty example. 17.6.25. pinctrl bank 2 upper pin mux select register description the pinctrl bank 2 upper pin mux select register provides pin function selec- tion for pins 16 through 31 of bank 2. hw_pinctrl_muxsel5 0x80018220 hw_pinctrl_muxsel5_set 0x80018224 hw_pinctrl_muxsel5_clr 0x80018228 hw_pinctrl_muxsel5_tog 0x8001822c table 611. hw_pinctrl_muxsel4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 func_sel table 612. hw_pinctrl_mu xsel4 bit field descriptions bits label rw reset definition 31:0 func_sel rw 0xffffffff this field selects which hardware interface block controls each of the first 16 pins in bank 2. this field is divided into sixteen 2 bit subfields, with bits [1:0] corresponding to pin 0, bits [3:2] corresponding to pin 1, etc. subfield definitions: 00= default peripheral 01= alternate peripheral1 or undefined 10= alternate peripheral2 or undefined 11= gpio table 613. hw_pinctrl_muxsel5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 func_sel free datasheet http:/// STMP36XX official product documentation 5/3/06 458 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: this register allows the programmer to select which hardware interface blocks drive the last sixteen pins in bank 2. for example, if this register is set to 0x00000003, the sixt eenth pin in the ba nk (gpio2[16]) will be set to gpio mode and bank 2 pins 17-31 will be set to their primary function mode. see the table in the pin interface multip lexing section earlier in this chapter for information about pin to gpio bank mapping. example: empty example. 17.6.26. pinctrl bank 2 drive strength register description the pinctrl bank 2 drive strength regist er selects the current drive strength for pins in bank 2. hw_pinctrl_drive2 0x80018230 hw_pinctrl_drive2_set 0x80018234 hw_pinctrl_drive2_clr 0x80018238 hw_pinctrl_drive2_tog 0x8001823c description: table 614. hw_pinctrl_mu xsel5 bit field descriptions bits label rw reset definition 31:0 func_sel rw 0xffffffff this field selects which hardware interface block controls each of the last 16 pins in bank 2. this field is divided into sixteen 2 bit subfields, with bits [1:0] corresponding to pin 16, bits [3:2] corresponding to pin 17, etc. subfield definitions: 00= default peripheral 01= alternate peripheral1 or undefined 10= alternate peripheral2 or undefined 11= gpio table 615. hw_pinctrl_drive2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 drive8ma table 616. hw_pinctrl_dri ve2 bit field descriptions bits label rw reset definition 31:0 drive8ma rw 0x00000000 this field selects the drive strength for pins configured as outputs. this field is segmented into 1 bit per pin subfields, with bit 0 corresponding to bank 3 pin 0, bit 1 corresponding to pin 1, etc. subfield definitions: 0= 4-ma drive strength 1= 8-ma drive strength free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 459 the drive strength register selects the drive strength (4 ma or 8 ma) for pins in bank 2 that are configured for output. example: empty example. 17.6.27. pinctrl bank 2 data output register description the pinctrl bank 2 data output register pr ovides data for all pins in bank 2 that are configured for gpio output mode. hw_pinctrl_dout2 0x80018250 hw_pinctrl_dout2_set 0x80018254 hw_pinctrl_dout2_clr 0x80018258 hw_pinctrl_dout2_tog 0x8001825c description: this register contains the data that will be driven out a ll bank 2 pins that are config- ured for gpio output mo de. for example, if hw_pinctrl_muxsel4 contains 0x0000000f and hw_pinctrl_doe2 contai ns 0x00000001, then gpio2[0] will be driven with the value from bit 0 of this register, gpio2[1] w ill not be driven, and gpio2[2:15] will be controlled by th e associated primary interfaces. example: empty example. 17.6.28. pinctrl bank 2 data input register description the current value of all bank 2 pins may be read from the pinctrl bank 2 data input register. hw_pinctrl_din2 0x80018260 hw_pinctrl_din2_set 0x80018264 hw_pinctrl_din2_clr 0x80018268 hw_pinctrl_din2_tog 0x8001826c table 617. hw_pinctrl_dout2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dataout table 618. hw_pinctrl_dout2 bit field descriptions bits label rw reset definition 31:0 dataout rw 0x00000000 this field selects the output value (0 or 1) for pins configured as gpio outputs. each bit in this register corresponds to one of the 32 pins in bank 2. table 619. hw_pinctrl_din2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 datain free datasheet http:/// STMP36XX official product documentation 5/3/06 460 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: this register reflects the current values of all the bank 2 pins. the register accu- rately reflects the state of the pin regardless of the setting of the hw_pinctrl_muxselx or hw_pinctrl_doe x registers. but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the hw_pinctrl_muxselx register should be set to 3 (gpio mode) and the pin's bit in the hw_pinctrl_doex register should be set to 0 (disabled) to ensure that the chip is not driving the pin. for example, if hw_pinctrl_muxsel4 contains 0x0000000f and hw_pinctrl_doe2 contains 0x00000001, th en pin gpio2[1] will be an input pin, and bit 1 of this register will reflect its current state. example: empty example. 17.6.29. pinctrl bank 2 output enable register description the pinctrl bank 2 output enable regist er controls the output enable signal for all pins in bank 2 that are configured for gpio mode. hw_pinctrl_doe2 0x80018270 hw_pinctrl_doe2_set 0x80018274 hw_pinctrl_doe2_clr 0x80018278 hw_pinctrl_doe2_tog 0x8001827c description: for pins in bank 2 that are configured as gpios (by setting the pin's control field in hw_pinctrl_muxsel4/5 to 3) , a 1 in this register will enable the corresponding bit value from hw_pinctrl_dout2 to be dr iven out the pin, and a 0 in this regis- ter will disable the corresponding driver . for example, if hw_pinctrl_muxsel4 contains 0x0000000f and hw_pinctrl_d oe2 contains 0x00000001, then pin gpio2[0] will be driven with the value from hw_pin ctrl_dout2 bit 0, pin table 620. hw_pinctrl_din 2 bit field descriptions bits label rw reset definition 31:0 datain ro 0x00000000 each bit in this read-only register corresponds to one of the 32 pins in bank 2. the current state of each pin in bank 2, synchronized to hclk, may be read here. table 621. hw_pinctrl_doe2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dataoe table 622. hw_pinctrl_doe2 bit field descriptions bits label rw reset definition 31:0 dataoe rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 2. setting a bit in this register to one allows the STMP36XX to drive the corresponding pin in gpio mode. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 461 gpio1[1] will be three-stated , and pins gpio2[2-15] will be controlled by the default peripheral interface associated with each of those pins. example: empty example. 17.6.30. pinctrl bank 2 interrupt select register description the pinctrl bank 2 interrupt select regist er selects which of the bank 2 pins may be used as interrupt sources. hw_pinctrl_pin2irq2 0x80018280 hw_pinctrl_pin2irq2_set 0x80018284 hw_pinctrl_pin2irq2_clr 0x80018288 hw_pinctrl_pin2irq2_tog 0x8001828c description: as described earlier in this chapter, any digital i/o pin can be used as an interrupt source. this register selects which pins in bank 2 can be used to generate inter- rupts. if the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the hw_pinctrl_irqlevel2 and hw_pinctrl_irqpol2 regi sters) will set the corr esponding bit in the hw_pinctrl_irqstat2 register. if the pin is additionally enabled in the hw_pinctrl_irqen2 re gister, then the in terrupt will be prop agated to the inter- rupt collector as interrupt gpio2. for example, if this register contai ns 0x00000014, then pins gpio2[2] and gpio2[4] can be used as in terrupt pins, and no other pins in bank 2 will cause bits to be set in the hw_pinctrl_irqstat2 register. example: empty example. 17.6.31. pinctrl bank 2 interrupt mask register description the pinctrl bank 2 interrupt mask regist er contains interrupt enable masks for the pins in bank 2. hw_pinctrl_irqen2 0x80018290 hw_pinctrl_irqen2_set 0x80018294 hw_pinctrl_irqen2_clr 0x80018298 hw_pinctrl_irqen2_tog 0x8001829c table 623. hw_pinctrl_pin2irq2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 enable2irq table 624. hw_pinctrl_pin 2irq2 bit field descriptions bits label rw reset definition 31:0 enable2irq rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 2: 0= deselect the pin's interrupt functionality. 1= select the pin to be used as an interrupt source. free datasheet http:/// STMP36XX official product documentation 5/3/06 462 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: as described earlier in this chapter, any digital i/o pin can be used as an interrupt source. this register masks the interrupt sour ces from the pins in bank 2. if a bit is set in this register and the same bit is set in hw_pinctrl_irqstat2, an interrupt will be propagated to the interrupt collector as interrupt gpio2. for example, if this register contai ns 0x00000014, then only bits 2 and 4 in hw_pinctrl_irqstat2 (corresponding to pins gpio2[2] and gpio2[4]) will cause interrupts from bank 2. example: empty example. 17.6.32. pinctrl bank 2 interrupt level/edge register description the pinctrl bank 2 interrupt level/edge register selects level or edge sensitivity for interrupt requests for the pins in bank 2. hw_pinctrl_irqlevel2 0x800182a0 hw_pinctrl_irqlevel2_set 0x800182a4 hw_pinctrl_irqlevel2_clr 0x800182a8 hw_pinctrl_irqlevel2_tog 0x800182ac table 625. hw _pinctrl_irqen2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 irqenable table 626. hw_pinctrl_irq en2 bit field descriptions bits label rw reset definition 31:0 irqenable rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 2: 1= enable interrupts from the corresponding bit in hw_pinctrl_irqstat2. 0= disable interrupts from the corresponding bit in hw_pinctrl_irqstat2. table 627. hw_p inctrl_irqlevel2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bitirqlevel table 628. hw_pinctrl_irq level2 bit field descriptions bits label rw reset definition 31:0 bitirqlevel rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 2: 1= level detection 0= edge detection free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 463 description: this register selects level or edge detection for interrupt generation. each pin in bank 2 which is configured for interrupt generation can be independently set to inter- rupt on low level, high level, rising edge, or falling edge by setting bits in this register and hw_pinctrl_irqpol2 (see below) appropriately. example: empty example. 17.6.33. pinctrl bank 2 interrupt polarity register description the pinctrl bank 2 interrupt polarity regi ster selects the pola rity for interrupt requests for the pins in bank 2. hw_pinctrl_irqpol2 0x800182b0 hw_pinctrl_irqpol2_set 0x800182b4 hw_pinctrl_irqpol2_clr 0x800182b8 hw_pinctrl_irqpol2_tog 0x800182bc description: this register selects the polarity for interrupt generation. each pin in bank 2 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or fa lling edge by setting this register and hw_pinctrl_irqlevel2 (see above) appropriately. example: empty example. 17.6.34. pinctrl bank 2 interrupt status register description the pinctrl bank 2 interrupt status regist er reflects pending interrupt status for the pins in bank 2. hw_pinctrl_irqstat2 0x800182c0 hw_pinctrl_irqstat2_set 0x800182c4 hw_pinctrl_irqstat2_clr 0x800182c8 hw_pinctrl_irqstat2_tog 0x800182cc table 629. hw_pinctrl_irqpol2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 irqpol table 630. hw_pinctrl_irqpo l2 bit field descriptions bits label rw reset definition 31:0 irqpol rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 2: 0= low or falling edge 1= high or rising edge free datasheet http:/// STMP36XX official product documentation 5/3/06 464 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: this register reflects the pending interrupt status for pins in bank 2. bits in this reg- ister are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling e dge) occurs on a bank 2 pin that has been enabled as an interrupt source in the hw _pinctrl_pin2irq2 register. software may clear any bit in this register by writing a 1 to the bit at the sct clear address, e.g., hw_pinctrl_irqstat2_clr. status bits fo r pins configured as level-sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in hw_pinctrl_pin2irq2. if a bit is set in this register, and the corresponding bit is also set in the hw_pincntrl_irqen2 mask register, then the gpio2 interrupt will be asserted to the interrupt collector. example: empty example. 17.6.35. pinctrl bank 3 lower pin mux select register description the pinctrl bank 3 lower pin mux select register provides pin function selec- tion for pins 0 through 15 of bank 3. hw_pinctrl_muxsel6 0x80018310 hw_pinctrl_muxsel6_set 0x80018314 hw_pinctrl_muxsel6_clr 0x80018318 hw_pinctrl_muxsel6_tog 0x8001831c table 631. hw_pinctrl_irqstat2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 stat table 632. hw_pinctrl_irq stat2 bit field descriptions bits label rw reset definition 31:0 stat rw 0x00000000 each bit in this register corresponds to one of the 32 pins in bank 2: 0= no interrupt pending 1= interrupt pending table 633. hw_pinctrl_muxsel6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 func_sel free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 465 description: this register allows the programmer to select which hardware interface blocks drive the first sixteen pins in bank 3. for example, if this register is set to 0x0000002c, the second pin in the bank (gpio3[1]) will be set to gpio mode, the third pin in the bank will be set to its se cond alternate functi on mode, and bank 3 pins 0 and 3-15 will be set to their primary function modes. see the table in the pin interface multip lexing section earlier in this chapter for information about pin-to-gpio bank mapping. example: empty example. 17.6.36. pinctrl bank 3 upper pin mux select register description the pinctrl bank 3 upper pin mux select register provides pin function selec- tion for pins 16 through 18 of bank 3. hw_pinctrl_muxsel7 0x80018320 hw_pinctrl_muxsel7_set 0x80018324 hw_pinctrl_muxsel7_clr 0x80018328 hw_pinctrl_muxsel7_tog 0x8001832c table 634. hw_pinctrl_mu xsel6 bit field descriptions bits label rw reset definition 31:0 func_sel rw 0xffffffff this field selects which hardware interface block controls each of the first 16 pins in bank 3. this field is divided into sixteen 2 bit subfields, with bits [1:0] corresponding to pin 0, bits [3:2] corresponding to pin 1, etc. subfield definitions: 00= default peripheral 01= alternate peripheral1 or undefined 10= alternate peripheral2 or undefined 11= gpio table 635. hw_pinctrl_muxsel7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 func_sel free datasheet http:/// STMP36XX official product documentation 5/3/06 466 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: this register allows the programmer to select which hardware interface blocks drive the last three pins in bank 3. for example, if this register is set to 0x00000003, the sixteenth pin in the bank (gpio0[16] ) will be set to gpio mode and bank pins 17-18 will be set to thei r primary function mode. see the table in the pin interface multip lexing section earlier in this chapter for information about pin-to-gpio bank mapping. example: empty example. 17.6.37. pinctrl bank 3 drive strength register description the pinctrl bank 3 drive strength regist er selects the current drive strength for pins in bank 3. hw_pinctrl_drive3 0x80018330 hw_pinctrl_drive3_set 0x80018334 hw_pinctrl_drive3_clr 0x80018338 hw_pinctrl_drive3_tog 0x8001833c table 636. hw_pinctrl_mu xsel7 bit field descriptions bits label rw reset definition 31:6 rsrvd1 ro 0x0 always write zeroes to this field. 5:0 func_sel rw 0x3f this field selects which hardware interface block controls each of the last 3 pins in bank 3. this field is divided into three 2 bit subfields, with bits [1:0] corresponding to pin 16, bits [3:2] corresponding to pin 17, etc. subfield definitions: 00= default peripheral 01= alternate peripheral1 or undefined 10= alternate peripheral2 or undefined 11= gpio table 637. hw_pinctrl_drive3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 drive8ma free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 467 description: the pinctrl bank 3 drive strength register selects the drive strength (4 ma or 8 ma) for pins in bank 3 that are configured for output. note that two pins, pwm3 and pwm4, corresponding to bits 13 and 14 repectively have stronger drivers than the other pins. when asserting these bits, their pins have 16-ma drive strength instead of 8-ma. example: empty example. 17.6.38. pinctrl bank 3 data output register description the pinctrl bank 3 data output register pr ovides data for all pins in bank 3 that are configured for gpio output mode. hw_pinctrl_dout3 0x80018350 hw_pinctrl_dout3_set 0x80018354 hw_pinctrl_dout3_clr 0x80018358 hw_pinctrl_dout3_tog 0x8001835c table 638. hw_pinctrl_dri ve3 bit field descriptions bits label rw reset definition 31:19 rsrvd1 ro 0x0 always write zeroes to this field. 18:0 drive8ma rw 0x0 this field selects the drive strength for pins configured as outputs. this field is segmented into 1 bit per pin subfields, with bit 0 corresponding to bank 3 pin 0, bit 1 corresponding to pin 1, etc. subfield definitions: 0= 4-ma drive strength 1= 8-ma drive strength (16-ma for pins pwm3 and pwm4) note that two pins, pwm3 and pwm4, corresponding to bits 13 and 14 repectively have stronger drivers than the other pins. when asserting these bits their pins have 16-ma drive strength instead of 8-ma. table 639. hw_pinctrl_dout3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 dataout table 640. hw_pinctrl_dout3 bit field descriptions bits label rw reset definition 31:19 rsrvd1 ro 0x0 always write zeroes to this field. 18:0 dataout rw 0x0 this field selects the output value (0 or 1) for pins configured as gpio outputs. each bit in this register corresponds to one of the 19 pins in bank 3. free datasheet http:/// STMP36XX official product documentation 5/3/06 468 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: this register contains the data that will be driven out a ll bank 3 pins that are config- ured for gpio output mo de. for example, if hw_pinctrl_muxsel6 contains 0x0000000f and hw_pinctrl_doe3 contai ns 0x00000001, then gpio3[0] will be driven with the value from bit 0 of this register, gpio3[1] w ill not be driven, and gpio3[2:15] will be controlled by th e associated primary interfaces. example: empty example. 17.6.39. pinctrl bank 3 data input register description the current value of all bank 3 pins may be read from the pinctrl bank 3 data input register. hw_pinctrl_din3 0x80018360 hw_pinctrl_din3_set 0x80018364 hw_pinctrl_din3_clr 0x80018368 hw_pinctrl_din3_tog 0x8001836c description: this register reflects the current values of all the bank 3 pins. the register accu- rately reflects the state of the pin regardless of the setting of the hw_pinctrl_muxselx or hw_pinctrl_doe x registers. but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the hw_pinctrl_muxselx register should be set to 3 (gpio mode) and the pin's bit in the hw_pinctrl_doex register should be set to 0 (disabled) to ensure that the chip is not driving the pin. for example, if hw_pinctrl_muxsel6 contains 0x0000000f and hw_pinctrl_doe3 contains 0x00000001, th en pin gpio3[1] will be an input pin, and bit 1 of this register will reflect its current state. example: empty example. table 641. hw_pinctrl_din3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 datain table 642. hw_pinctrl_din 3 bit field descriptions bits label rw reset definition 31:19 rsrvd1 ro 0x0 always write zeroes to this field. 18:0 datain ro 0x0 each bit in this read-only register corresponds to one of the 19 pins in bank 2. the current state of each pin in bank 2, synchronized to hclk, may be read here. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 469 17.6.40. pinctrl bank 3 output enable register description the pinctrl bank 3 output enable regist er controls the output enable signal for all pins in bank 3 that are configured for gpio mode. hw_pinctrl_doe3 0x80018370 hw_pinctrl_doe3_set 0x80018374 hw_pinctrl_doe3_clr 0x80018378 hw_pinctrl_doe3_tog 0x8001837c description: for pins in bank 3 that are configured as gpios (by setting the pin's control field in hw_pinctrl_muxsel6/7 to 3) , a 1 in this register will enable the corresponding bit value from hw_pinctrl_dout3 to be dr iven out the pin, and a 0 in this regis- ter will disable the corresponding driver . for example, if hw_pinctrl_muxsel6 contains 0x0000000f and hw_pinctrl_d oe3 contains 0x00000001, then pin gpio3[0] will be driven with the value from hw_pin ctrl_dout3 bit 0, pin gpio3[1] will be three-stated , and pins gpio3[2-15] will be controlled by the default peripheral interface associated with each of those pins. example: empty example. 17.6.41. pinctrl bank 3 interrupt select register description the pinctrl bank 3 interrupt select regist er selects which of the bank 3 pins may be used as interrupt sources. hw_pinctrl_pin2irq3 0x80018380 hw_pinctrl_pin2irq3_set 0x80018384 hw_pinctrl_pin2irq3_clr 0x80018388 hw_pinctrl_pin2irq3_tog 0x8001838c table 643. hw_pinctrl_doe3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 dataoe table 644. hw_pinctrl_doe3 bit field descriptions bits label rw reset definition 31:19 rsrvd1 ro 0x0 always write zeroes to this field. 18:0 dataoe rw 0x0 each bit in this register corresponds to one of the 19 pins in bank 3. setting a bit in this register to one allows the STMP36XX to drive the corresponding pin in gpio mode. free datasheet http:/// STMP36XX official product documentation 5/3/06 470 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: as described earlier in this chapter, any digital i/o pin can be used as an interrupt source. this register selects which pins in bank 3 can be used to generate inter- rupts. if the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the hw_pinctrl_irqlevel3 and hw_pinctrl_irqpol3 regi sters) will set the corr esponding bit in the hw_pinctrl_irqstat3 register. if the pin is additionally enabled in the hw_pinctrl_irqen3 re gister, then the in terrupt will be prop agated to the inter- rupt collector as interrupt gpio3. for example, if this register contai ns 0x00000014, then pins gpio3[2] and gpio3[4] can be used as in terrupt pins, and no other pins in bank 3 will cause bits to be set in the hw_pinctrl_irqstat3 register. example: empty example. 17.6.42. pinctrl bank 3 interrupt mask register description the pinctrl bank 3 interrupt mask regist er contains interrupt enable masks for the pins in bank 3. hw_pinctrl_irqen3 0x80018390 hw_pinctrl_irqen3_set 0x80018394 hw_pinctrl_irqen3_clr 0x80018398 hw_pinctrl_irqen3_tog 0x8001839c table 645. hw_pinctrl_pin2irq3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 enable2irq table 646. hw_pinctrl_pin 2irq3 bit field descriptions bits label rw reset definition 31:19 rsrvd1 ro 0x0 always write zeroes to this field. 18:0 enable2irq rw 0x0 each bit in this register corresponds to one of the 19 pins in bank 0: 0= deselect the pin's interrupt functionality. 1= select the pin to be used as an interrupt source. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 471 description: as described earlier in this chapter, any digital i/o pin can be used as an interrupt source. this register masks the interrupt sour ces from the pins in bank 3. if a bit is set in this register and the same bit is set in hw_pinctrl_irqstat3, an interrupt will be propagated to the interrupt collector as interrupt gpio3. for example, if this register contai ns 0x00000014, then only bits 2 and 4 in hw_pinctrl_irqstat3 (corresponding to pins gpio3[2] and gpio3[4]) will cause interrupts from bank 3. example: empty example. 17.6.43. pinctrl bank 3 interrupt level/edge register description the pinctrl bank 3 interrupt level/edge register selects level or edge sensitivity for interrupt requests for the pins in bank 3. hw_pinctrl_irqlevel3 0x800183a0 hw_pinctrl_irqlevel3_set 0x800183a4 hw_pinctrl_irqlevel3_clr 0x800183a8 hw_pinctrl_irqlevel3_tog 0x800183ac table 647. hw _pinctrl_irqen3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 irqenable table 648. hw_pinctrl_irq en3 bit field descriptions bits label rw reset definition 31:19 rsrvd1 ro 0x0 always write zeroes to this field. 18:0 irqenable rw 0x0 each bit in this register corresponds to one of the 19 pins in bank 3: 1= enable interrupts from the corresponding bit in hw_pinctrl_irqstat3. 0= disable interrupts from the corresponding bit in hw_pinctrl_irqstat3. table 649. hw_p inctrl_irqlevel3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 bitirqlevel free datasheet http:/// STMP36XX official product documentation 5/3/06 472 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 description: this register selects level or edge detection for interrupt generation. each pin in bank 3 that is configured for interrupt generation can be independently set to inter- rupt on low level, high level, rising edge, or falling edge by setting bits in this register and hw_pinctrl_irqpol3 (see below) appropriately. example: empty example. 17.6.44. pinctrl bank 3 interrupt polarity register description the pinctrl bank 3 interrupt polarity regi ster selects the pola rity for interrupt requests for the pins in bank 3. hw_pinctrl_irqpol3 0x800183b0 hw_pinctrl_irqpol3_set 0x800183b4 hw_pinctrl_irqpol3_clr 0x800183b8 hw_pinctrl_irqpol3_tog 0x800183bc description: this register selects the polarity for in terrupt generation. each pin in bank 3 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or fa lling edge by setting this register and hw_pinctrl_irqlevel3 (see above) appropriately. example: table 650. hw_pinctrl_irq level3 bit field descriptions bits label rw reset definition 31:19 rsrvd1 ro 0x0 always write zeroes to this field. 18:0 bitirqlevel rw 0x0 each bit in this register corresponds to one of the 19 pins in bank 3: 1= level detection 0= edge detection table 651. hw_pinctrl_irqpol3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 irqpol table 652. hw_pinctrl_irqpo l3 bit field descriptions bits label rw reset definition 31:19 rsrvd1 ro 0x0 always write zeroes to this field. 18:0 irqpol rw 0x0 each bit in this register corresponds to one of the 19 pins in bank 3: 0= low or falling edge 1= high or rising edge free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 17: pin control and gpio 473 empty example. 17.6.45. pinctrl bank 3 interrupt status register description the pinctrl bank 3 interrupt status regist er reflects pending interrupt status for the pins in bank 3. hw_pinctrl_irqstat3 0x800183c0 hw_pinctrl_irqstat3_set 0x800183c4 hw_pinctrl_irqstat3_clr 0x800183c8 hw_pinctrl_irqstat3_tog 0x800183cc description: this register reflects the pending interrupt status for pins in bank 3. bits in this reg- ister are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling e dge) occurs on a bank 3 pin that has been enabled as an interrupt source in the hw _pinctrl_pin2irq3 register. software may clear any bit in this register by writing a 1 to the bit at the sct clear address, e.g., hw_pinctrl_irqstat3_clr. status bits fo r pins configured as level-sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in hw_pinctrl_pin2irq3. if a bit is set in this register, and the corresponding bit is also set in the hw_pincntrl_irqen3 mask register, then the gpio3 interrupt will be asserted to the interrupt collector. example: empty example. pinctrl xml revision: 1.20 table 653. hw_pinctrl_irqstat3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 stat table 654. hw_pinctrl_irq stat3 bit field descriptions bits label rw reset definition 31:19 rsrvd1 ro 0x0 always write zeroes to this field. 18:0 stat rw 0x0 each bit in this register corresponds to one of the 19 pins in bank 3: 0= no interrupt pending 1= interrupt pending free datasheet http:/// STMP36XX official product documentation 5/3/06 474 chapter 17: pin control and gpio 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 475 18. timers and rotary decoder this chapter describes the timers and rotary decoder included on the STMP36XX. programmable registers are described in section 18.4 . 18.1. overview the STMP36XX implements four timers and a rotary decoder, as shown in figure 80 . the timers and decoder can take their inputs from any of the pins defined for pwm, rotary encoders, or certain divi sions from the 32-khz clock input. thus, the pwm pins can be inputs or outputs, depending on the application. the timer/rotary decoder block is a programmed i/o interface connected to the apbx bus. recall that the apbx typically runs at a divided clock rate from the 24- mhz crystal clock (6 mhz). each timer and rotary channel can sample at a rate that is further subdivided from the apbx clock. each timer can select a different pre- scaler value. 24-mhz xtal osc. divide by n timers and rotary decoder timer/rotary decoder programmable registers arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram timer 0 pwm[0] 1/1, 1/ 2, 1/8, 1/16 timer 1 1/1, 1/ 2, 1/8, 1/16 timer 2 1/1, 1/ 2, 1/8, 1/16 timer 3 1/1, 1/ 2, 1/8, 1/16 rotary up/down counter pwm[1] pwm[2] pwm[3] pwm[4] rotary_a rotary_b 32-khz osc. figure 80. timers and rotary decoder block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 476 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 18.2. timers each of the four timers consists of a 16-bit fixed count value and a 16-bit free-run- ning count value. in most cases, the free-running count decrements to zero. when it decrements to zero, it sets an interrupt status bit associated with the counter. ? if the reload bit is set to one, then the fixed count is automatically copied to the free-running counter and the count continues. ? if the reload bit is not set, the timer stalls when it reaches zero. figure 81 shows a detailed view of either timer 0, timer 1, or timer 2. timer 3 has additional functionality, which is shown in figure 82 . timer i/o divide by 1, 2, 4, 8 24-mhz xtal osc. 16-bit running count 16-bit fixed count mode controller gated clk hold, down, load, copy pwm[0] pwm[1] pwm[2] pwm[3] pwm[4] rotary_a rotary_b edge detect tick apbx clk divide by n hold, load, copy ==0 ? always tick divide by 1, 4, 8, 32 32-khz input never tick figure 81. timer 0, timer 1, or timer 2 detail free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 477 each timer has an update bit that cont rols whether the fr ee-running-counter is loaded at the same time the fixed-count regi ster is written from the cpu. the output of each timer?s source select has a polarity control that allows the timer to operate on either edge. table 655 lists the timer state machine transitions. when generating a periodic timer interr upt using the reload bit, the user must compute the proper fixed-count value (count_value) based on clock speeds and clock divider settings. note that, in this case, the actual value written to the fixed_count register field should be co unt_value ? 1. for one-shot interrupts (reload bit not set), the value written should be count_value. for proper detection of the input source signal, it should be much slower than the pre-scaled apbx clock (no greater than one- third the frequency of the pre-scaled apbx clock). selecting the always tick causes the timer to decrement continuously at the rate established by the pre-sca led apbx clock. the never tick selection causes the timer to stall. setting the fixed-count to 0xffff and setting the reload bit causes the timer to operate in a continuous-count 65536 count mode. the state of the 16-bit free-running count can be read by the cpu for each timer. 18.2.1. using external signals as inputs external signals can be used as inputs to the block. they can be used as either the test signal or sampling input signals (duty cycle or normal timer mode). this can be accomplished by using the rotary input pins or any unused pwm pins. if pwm pins are being used for this purpose, conflicts with the pwm or other blocks that could drive the pins as outputs must be avoide d. in this case, the pwm pins being used should be programmed as gpio inputs. (see chapter 17 , ?pin control and gpio? on page 429 for details.) then, the external signal can be wired to the pin, and the pwm number selected in the appropriate timrot registers. table 655. timer state machine transitions update reload running 0 0 pio writes to the fixed-count bit field have no effect on the running count. 0 1 the value written to the fixed count is used to reload the running count the next time it reaches zero. when the fixed count has been written with a value of zero and the running count reaches zero, it continuously copies the fixed count value to the running count. thus, writing a non- zero value to the fixed count register ki cks off a continuous count and update operation. 1 0 the value written to the fixed count bit field is copied, immediately, to the running count, restarting any existing running count operation. when the new running count reaches zero, it freezes. 1 1 the value written to the fixed count bit field is copied, immediately, to the running count, restarting any existing running count operation. when the new running count reaches zero, it is reloaded from the value in the fixed coun t bit field, thus running continuously using the newly supplied fixed count. free datasheet http:/// STMP36XX official product documentation 5/3/06 478 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 18.2.2. timer 3 and duty cycle mode timer 3 can operate in the same modes as timer 0, timer 1, and timer 2. however, it has an additional duty cycle measurement mode. figure 82 shows a detailed view of timer 3. timer i/o divide by 1, 2, 4, 8 24-mhz xtal osc. 16-bit running count 16-bit fixed count mode controller gated clk hold, down, load, copy pwm[0] pwm[1] pwm[2] pwm[3] pwm[4] rotary_a rotary_b edge detect tick apbx clk divide by n hold, load, copy ==0 ? always tick 32-khz input 16-bit low count lvl divide by 1, 4, 8, 32 never tick figure 82. timer 3 detail free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 479 in the duty cycle mode, timer 3 samples th e free-running counter at the rising and falling edges of the in put test signal, resetting the fr ee-running coun ter on the same clock that is sampled. ? on the rising edge of the test signal, the free-running count is copied to the low_running_count bit field of the hw_timrot_timcount3 register. ? on the falling edge of the source clock, the free-running count is copied to the high_fixed_count bit field (as shown in figure 83 ). ? once duty cycle mode is programmed and the input signal is stable, software should poll the duty_valid bit in the hw_timrot_timctrl3 register. ? this bit is automatically set and cleared by the hardware. when this bit is set, count values in the hw_timrot_timcount3 register are stable and ready to be read. refer to the timer 3 control and status register, hw_timrot_timctrl3, where the duty_cycle bit controls whether hw_timrot_timcount3 register?s low_running_count bit field reads back the running count or the low count of a duty cycle measurement. the duty_cycle bit also controls whether the high_fixed_count bit field reads back the fixed-count value used in normal timer operations or the duty cycle high-time measurement. it should be noted that for duty cycle mo de to function properly, the timer ?tick? source selected (select field of the hw_timrot_timctrl3 register) should be an appropriate frequency to sample the test signal. the never_tick value should never be used in this mode, as it will yield incorrect count results. 18.2.3. testing timer 3 duty cycle modes to test the duty cycle modes of time r3, select pwm1 as the input. pwm1 can gen- erate waveforms of arbitrary duty cycle su itable for testing the duty cycle measure- ment capability. input high count low count figure 83. pulse-width measurement mode free datasheet http:/// STMP36XX official product documentation 5/3/06 480 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 18.3. rotary decoder the rotary decoder uses two input sele ctors and edge detectors, as shown in figure 84 . it includes a debounce circuit for each input, as shown in figure 85 . this figure shows the debounce circuit for inpu t a, though the circuit is identical for input b. timer i/o signed 16-bit up/down count mode controller and debounce circuit hold, load, inc/dec pwm[0] pwm[1] pwm[2] pwm[3] pwm[4] rotary_a rotary_b never tick pwm[0] pwm[1] pwm[2] pwm[3] pwm[4] rotary_a rotary_b never tick rot sela rot selb edge detect edge detect 32-khz input apbx clock figure 84. detail of rotary decoder free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 481 a rotary decoder transition-following state machine is provided to detect the direc- tion of rotation and the time at which to increment or decrement the 16-bit signed counter in hw_timrot_rotcount. the updown counter can be treated as either a relative count or an absolute count, depending on the state of the hw_timrot_rotctrl_relative bit. when set to the relative mode, each read of the counter has the side effect of resetting it. the edge detectors respond to both edges of each input to determine the self-timed transition inputs to the state machine (see figure 86 ). pwm[0] pwm[1] pwm[2] pwm[3] pwm[4] rotary_a rotary_b never tick q q* k j q *q d q *q d q *q d q *q d q *q d q *q d q *q d q *q d ~oversamp_by_8 adebounce ~oversamp_by_8 flip-flops sample and advance at a divided 32-khz rate figure 85. rotary decoding mode?debouncing rotary a and b inputs free datasheet http:/// STMP36XX official product documentation 5/3/06 482 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 figure 86 shows that each detected edge causes a transition in the decoder state machine. not all transitions are legal (see table 656 ). for example, there is no legal way to transition directly from state 11 to 00 using normal inputs. in the cases where this occurs, the state machine goes to an alternate set of states and follows the input sequence until a valid sequence leading to state 00 is detected. no increment or decrement action is taken from the alternate state sequence. 18.3.1. testing the rotary decoder to test the rotary decoder, select pwm1 and pwm2 as inputs to rotarya and rotaryb. since pwm1 and pwm2 can be started with known phase offsets and duty cycles, a continuous increment or decrement stream can be generated. since pwm1 and pwm2 can be used as gpio device s, the final part of the test is to gen- erate and test a sequence of clockwise and counter-clockwise rotations to cover the entire state machine transitions, including the error conditions. 18.3.2. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. table 656. rotary decoder state machine transitions current state ?input? ba=00 ?input? ba=01 ? input? ba=10 ?input? ba=11 00 00 01 10 error 01 00, dec 01 error 11 10 00, inc error 10 11 11 error 01 10 11 input a input b 11 10 00 inc 10 11 01 00 dec 01 figure 86. rotary decoding mode?input transitions free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 483 18.4. programmable registers the following registers describe the programming interface for the timers and the rotary decoder. 18.4.1. rotary decoder control register description the rotary decoder control register specifies the reset state and the source selec- tion for the rotary decoder. in addition, it specifies the polarity of any external input source that is used. this register also contains some general block controls includ- ing soft reset, clock gate, and present bits. hw_timrot_rotctrl 0x80068000 hw_timrot_rotctrl_set 0x80068004 hw_timrot_rotctrl_clr 0x80068008 hw_timrot_rotctrl_tog 0x8006800c table 657. hw_timrot_rotctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rotary_present tim3_present tim2_present tim1_present tim0_present state divider rsrvd3 relative oversample polarity_b polarity_a rsrvd2 select_b rsrvd1 select_a table 658. hw_timrot_rotc trl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 this bit must be set to zero to enable operation of any timer or the rotary decoder. when set to one, it forces a block-level reset and gates off the clocks to the block. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. 29 rotary_present ro 0x1 0= rotary decoder is not present in this product. 1= rotary decoder is present is in this product. 28 tim3_present ro 0x1 0= timer 3 is not present in this product. 1= timer3 is present is in this product. 27 tim2_present ro 0x1 0= timer 2 is not present in this product. 1= timer2 is present is in this product. 26 tim1_present ro 0x1 0= timer 1 is not present in this product. 1= timer1 is present is in this product. 25 tim0_present ro 0x1 0= timer 0 is not present in this product. 1= timer0 is present is in this product. 24:22 state ro 0x0 read-only view of the rotary decoder transition detecting state machine. free datasheet http:/// STMP36XX official product documentation 5/3/06 484 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 description: this register contains control paramete rs to specify the rotary decoder setup. it also contains some general block controls including soft reset, clock gate, and present bits. example: empty example. 18.4.2. rotary decoder up/down counter register description the rotary decoder up/down counter regi ster contains the timer counter value that counts up or down as the rotary encoder is rotated. 21:16 divider rw 0x0 this bit field determines the divisor used to divide the 32-khz on chip clock rate for oversampling (debouncing) the rotary a and b inputs. note that the divider value is actually the (value of this field+1). 15:13 rsrvd3 ro 0x0 always write zeroes to this bit field. 12 relative rw 0x0 set this bit to one to cause the rotary decoders updown counter to be reset to zero whenever it is read. 11:10 oversample rw 0x0 this bit field determines the oversample rate to use in debouncing rotary a and b inputs. 8x = 0x0 8x oversample: 8 successi ve ones or zeroes to transition. 4x = 0x1 4x oversample: 4 successi ve ones or zeroes to transition. 2x = 0x2 2x oversample: 2 successi ve ones or zeroes to transition. 1x = 0x3 1x oversample: trans ition on each first input change. 9 polarity_b rw 0x0 set this bit to one to invert the input to the edge detector. 8 polarity_a rw 0x0 set this bit to one to invert the input to the edge detector. 7 rsrvd2 ro 0x0 always write zeroes to this bit field. 6:4 select_b rw 0x0 selects the source for the timer "tick" that increments the free-running counter that measures the a2b and b2a overlap counts. never_tick = 0x0 selectb: never tick. pwm0 = 0x1 selectb: input from pwm0. pwm1 = 0x2 selectb: input from pwm1. pwm2 = 0x3 selectb: input from pwm2. pwm3 = 0x4 selectb: input from pwm3. pwm4 = 0x5 selectb: input from pwm4. rotarya = 0x6 selectb: input from rotary a. rotaryb = 0x7 selectb: input from rotary b. 3 rsrvd1 ro 0x0 always write zeroes to this bit field. 2:0 select_a rw 0x0 selects the source for the timer "tick" that increments the free-running counter that measures the a2b and b2a overlap counts. never_tick = 0x0 selecta: never tick. pwm0 = 0x1 selecta: input from pwm0. pwm1 = 0x2 selecta: input from pwm1. pwm2 = 0x3 selecta: input from pwm2. pwm3 = 0x4 selecta: input from pwm3. pwm4 = 0x5 selecta: input from pwm4. rotarya = 0x6 selecta: input from rotary a. rotaryb = 0x7 selecta: input from rotary b. table 658. hw_timrot_rotc trl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 485 hw_timrot_rotcount 0x80068010 description: this register contains the read-only current count for the rotary decoder. example: empty example. 18.4.3. timer 0 control and status register description the timer 0 control and status register sp ecifies timer control parameters, as well as interrupt status and the enable for timer 0. hw_timrot_timctrl0 0x80068020 hw_timrot_timctrl0_set 0x80068024 hw_timrot_timctrl0_clr 0x80068028 hw_timrot_timctrl0_tog 0x8006802c table 659. hw_timrot_rotcount 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 updown table 660. hw_timrot_rotcount bit field descriptions bits label rw reset definition 31:16 rsrvd1 ro 0x0 always write zeroes to this bit field. 15:0 updown ro 0x00 at each edge of the rotary a input, the rotary b value is sampled, similarly at each edge of the rotary b input, the rotary a input is sampled. these values drive a rotary decoder state machine that determines when this counter is incremented or decremetned. when set in the relative mode, reads from this register clear this register as a side effect. counter values in this register are signed 16-bit values. table 661. hw_timrot_timctrl0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 irq irq_en rsrvd1 polarity update reload prescale select free datasheet http:/// STMP36XX official product documentation 5/3/06 486 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 description: this control register spec ifies control parameters, as well as interrupt status and the enable for timer 0. example: empty example. table 662. hw_timrot_timc trl0 bit field descriptions bits label rw reset definition 31:16 rsrvd2 ro 0x0 always write zeroes to this bit field. 15 irq rw 0x0 this bit is set to one when timer 0 decrements to zero. write a zero to clear it or use clear sct mode. 14 irq_en rw 0x0 set this bit to one to enable the generation of a cpu interrupt when the count reaches zero in normal counter mode. 13:9 rsrvd1 ro 0x0 always write zeroes to this bit field. 8 polarity rw 0x0 set this bit to one to invert the input to the edge detector. 0: positive edge detection. 1: invert to negative edge detection. 7 update rw 0x0 set this bit to one to cause the running count to be written from the cpu at the same time a new fixed count register value is written. 6 reload rw 0x0 set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. when set to zero, the timer enters a mode that freezes at a count of zero. when the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. 5:4 prescale rw 0x0 selects the divisor used for clock generation. the apbx clock is divided by the following amount. note the apbx clock itself is initially divided down from the 24.0-mhz crystal clock frequency. div_by_1 = 0x0 prescale: divide the apbx clock by 1. div_by_2 = 0x1 prescale: divide the apbx clock by 2. div_by_4 = 0x2 prescale: divide the apbx clock by 4. div_by_8 = 0x3 prescale: divide the apbx clock by 8. 3:0 select rw 0x0 selects the source for the timer "tick" that decrements the free running counter. note: programming an undefined value will result in "always tick" behavior. never_tick = 0x0 never tick. pwm0 = 0x1 input from pwm0. pwm1 = 0x2 input from pwm1. pwm2 = 0x3 input from pwm2. pwm3 = 0x4 input from pwm3. pwm4 = 0x5 input from pwm4. rotarya = 0x6 input from rotary a. rotaryb = 0x7 input from rotary b. 32khz_xtal = 0x8 input from 32-khz crystal. 8khz_xtal = 0x9 input from 8-khz (divided from 32-khz crystal). 4khz_xtal = 0xa input from 4-kh z (divided from 32-khz crystal). 1khz_xtal = 0xb input from 1-kh z (divided from 32-khz crystal). tick_always = 0xc always tick. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 487 18.4.4. timer 0 count register description the timer 0 count register contains the timer counter values for timer 0. hw_timrot_timcount0 0x80068030 description: this timer count register contains the programable and readback counter values for timer 0. example: empty example. 18.4.5. timer 1 control and status register description the timer 1 control and status register sp ecifies timer control parameters, as well as interrupt status and the enable for timer 1. hw_timrot_timctrl1 0x80068040 hw_timrot_timctrl1_set 0x80068044 hw_timrot_timctrl1_clr 0x80068048 hw_timrot_timctrl1_tog 0x8006804c table 663. hw_timrot_timcount0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 running_count fixed_count table 664. hw_timrot_timcount0 bit field descriptions bits label rw reset definition 31:16 running_count ro 0x00 this bit field shows the current state of the running count as it decrements. 15:0 fixed_count rw 0x00 software loads the fixed count bit field with the value to count down. if the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. if the update bit is set to one, then the new value is also copied into the running count, immediately. if both the reload and update bits are set to zero, then the new value is never picked up by the running count. free datasheet http:/// STMP36XX official product documentation 5/3/06 488 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 table 665. hw_timrot_timctrl1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 irq irq_en rsrvd1 polarity update reload prescale select table 666. hw_timrot_timc trl1 bit field descriptions bits label rw reset definition 31:16 rsrvd2 ro 0x0 always write zeroes to this bit field. 15 irq rw 0x0 this bit is set to one when timer 1 decrements to zero. write a zero to clear it or use clear sct mode. 14 irq_en rw 0x0 set this bit to one to enable the generation of a cpu interrupt when the count reaches zero in normal counter mode. 13:9 rsrvd1 ro 0x0 always write zeroes to this bit field. 8 polarity rw 0x0 set this bit to one to invert the input to the edge detector. 0: positive edge detection. 1: invert to negative edge detection. 7 update rw 0x0 set this bit to one to cause the running count to be written from the cpu at the same time a new fixed count register value is written. 6 reload rw 0x0 set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. when set to zero, the timer enters a mode that freezes at a count of zero. when the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 489 description: this control register spec ifies control parameters, as well as interrupt status and the enable for timer 1. example: empty example. 18.4.6. timer 1 count register description the timer 1 count register contains the timer counter values for timer 1. hw_timrot_timcount1 0x80068050 5:4 prescale rw 0x0 selects the divisor used for clock generation. the apbx clock is divided by the following amount. note the apbx clock itself is initially divided down from the 24.0-mhz crystal clock frequency. div_by_1 = 0x0 prescale: divide the apbx clock by 1. div_by_2 = 0x1 prescale: divide the apbx clock by 2. div_by_4 = 0x2 prescale: divide the apbx clock by 4. div_by_8 = 0x3 prescale: divide the apbx clock by 8. 3:0 select rw 0x0 selects the source for the timer "tick" that decrements the free running counter. note: programming an undefined value will result in "always tick" behavior. never_tick = 0x0 never tick. pwm0 = 0x1 input from pwm0. pwm1 = 0x2 input from pwm1. pwm2 = 0x3 input from pwm2. pwm3 = 0x4 input from pwm3. pwm4 = 0x5 input from pwm4. rotarya = 0x6 input from rotary a. rotaryb = 0x7 input from rotary b. 32khz_xtal = 0x8 input from 32-khz crystal. 8khz_xtal = 0x9 input from 8 khz (divided from 32-khz crystal). 4khz_xtal = 0xa input from 4 khz (divided from 32-khz crystal). 1khz_xtal = 0xb input from 1 khz (divided from 32-khz crystal). tick_always = 0xc always tick. table 667. hw_timrot_timcount1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 running_count fixed_count table 666. hw_timrot_timc trl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 490 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 description: this timer count register contains the programable and readback counter values for timer 1. example: empty example. 18.4.7. timer 2 control and status register description the timer 2 control and status register sp ecifies timer control parameters, as well as interrupt status and the enable for timer 2. hw_timrot_timctrl2 0x80068060 hw_timrot_timctrl2_set 0x80068064 hw_timrot_timctrl2_clr 0x80068068 hw_timrot_timctrl2_tog 0x8006806c table 668. hw_timrot_timcount1 bit field descriptions bits label rw reset definition 31:16 running_count ro 0x00 this bit field shows the current state of the running count as it decrements. 15:0 fixed_count rw 0x00 software loads the fixed count bit field with the value to count down. if the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. if the update bit is set to one, then the new value is also copied into the running count, immediately. if both the reload and update bits are set to zero, then the new value is never picked up by the running count. table 669. hw_timrot_timctrl2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 irq irq_en rsrvd1 polarity update reload prescale select table 670. hw_timrot_timc trl2 bit field descriptions bits label rw reset definition 31:16 rsrvd2 ro 0x0 always write zeroes to this bit field. 15 irq rw 0x0 this bit is set to one when timer 2 decrements to zero. write a zero to clear it or use clear sct mode. 14 irq_en rw 0x0 set this bit to one to enable the generation of a cpu interrupt when the count reaches zero in normal counter mode. 13:9 rsrvd1 ro 0x0 always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 491 description: this control register specifies control pa rameters as well as interrupt status and the enable for timer 2. example: empty example. 18.4.8. timer 2 count register description the timer 2 count register contains the timer counter values for timer 2. hw_timrot_timcount2 0x80068070 8 polarity rw 0x0 set this bit to one to invert the input to the edge detector. 0: positive edge detection. 1: invert to negative edge detection. 7 update rw 0x0 set this bit to one to cause the running count to be written from the cpu at the same time a new fixed count register value is written. 6 reload rw 0x0 set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. when set to zero, the timer enters a mode that freezes at a count of zero. when the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. 5:4 prescale rw 0x0 selects the divisor used for clock generation. the apbx clock is divided by the following amount. note the apbx clock itself is initially divided down from the 24.0-mhz crystal clock frequency. div_by_1 = 0x0 prescale: divide the apbx clock by 1. div_by_2 = 0x1 prescale: divide the apbx clock by 2. div_by_4 = 0x2 prescale: divide the apbx clock by 4. div_by_8 = 0x3 prescale: divide the apbx clock by 8. 3:0 select rw 0x0 selects the source for the timer "tick" that decrements the free running counter. note: programming an undefined value will result in "always tick" behavior. never_tick = 0x0 never tick. pwm0 = 0x1 input from pwm0. pwm1 = 0x2 input from pwm1. pwm2 = 0x3 input from pwm2. pwm3 = 0x4 input from pwm3. pwm4 = 0x5 input from pwm4. rotarya = 0x6 input from rotary a. rotaryb = 0x7 input from rotary b. 32khz_xtal = 0x8 input from 32-khz crystal. 8khz_xtal = 0x9 input from 8 khz (divided from 32-khz crystal). 4khz_xtal = 0xa input from 4 khz (divided from 32-khz crystal). 1khz_xtal = 0xb input from 1 khz (divided from 32-khz crystal). tick_always = 0xc always tick. table 670. hw_timrot_timc trl2 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 492 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 description: this timer count register contains the programable and readback counter values for timer 2. example: empty example. 18.4.9. timer 3 control and status register description the timer 3 control and status register sp ecifies timer control parameters, as well as interrupt status and the enable for timer 3. hw_timrot_timctrl3 0x80068080 hw_timrot_timctrl3_set 0x80068084 hw_timrot_timctrl3_clr 0x80068088 hw_timrot_timctrl3_tog 0x8006808c table 671. hw_timrot_timcount2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 running_count fixed_count table 672. hw_timrot_timcount2 bit field descriptions bits label rw reset definition 31:16 running_count ro 0x00 this bit field shows the current state of the running count as it decrements. 15:0 fixed_count rw 0x00 software loads the fixed count bit field with the value to count down. if the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. if the update bit is set to one, then the new value is also copied into the running count, immediately. if both the reload and update bits are set to zero, then the new value is never picked up by the running count. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 493 table 673. hw_timrot_timctrl3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 test_signal irq irq_en rsrvd1 duty_valid duty_cycle polarity update reload prescale select table 674. hw_timrot_timc trl3 bit field descriptions bits label rw reset definition 31:20 rsrvd2 ro 0x0 always write zeroes to this bit field. 19:16 test_signal rw 0x0 selects the source of the signal to be measured in duty cycle mode. never_tick = 0x0 never tick. freeze the count. pwm0 = 0x1 input from pwm0. pwm1 = 0x2 input from pwm1. pwm2 = 0x3 input from pwm2. pwm3 = 0x4 input from pwm3. pwm4 = 0x5 input from pwm4. rotarya = 0x6 input from rotary a. rotaryb = 0x7 input from rotary b. 32khz_xtal = 0x8 input from 32-khz crystal. 8khz_xtal = 0x9 input from 8 khz (divided from 32-khz crystal). 4khz_xtal = 0xa input from 4 khz (divided from 32-khz crystal). 1khz_xtal = 0xb input from 1 khz (divided from 32-khz crystal). tick_always = 0xc always tick. 15 irq rw 0x0 this bit is set to one when timer 3 decrements to zero. write a zero to clear it or use clear sct mode. 14 irq_en rw 0x0 set this bit to one to enable the generation of a cpu interrupt when the count reaches zero in normal counter mode. 13:11 rsrvd1 ro 0x0 always write zeroes to this bit field. 10 duty_valid ro 0x0 this bit is set and cleared by the hardware. it is set only when in duty cycle measuring mode and the hw_timrot_timcount3 has valid duty cycle data to be read. this register will be cleared if not in duty cycle mode or on writes to this register. in the case that it is written while in duty cycle mode, this bit will clear but will again be set at the appropriate time for reading the count register. 9 duty_cycle rw 0x0 set this bit to one to cause the timer to operate in duty cycle measuring mode. 8 polarity rw 0x0 set this bit to one to invert the input to the edge detector. 0: positive edge detection. 1: invert to negative edge detection. 7 update rw 0x0 set this bit to one to cause the running count to be written from the cpu at the same time a new fixed count register value is written. free datasheet http:/// STMP36XX official product documentation 5/3/06 494 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 description: this control register spec ifies control parameters, as well as interrupt status and the enable for timer 3. example: empty example. 18.4.10. timer 3 count register description the timer 3 count register contains the timer counter values for timer 3. note: this timer can be put in a special duty cy cle mode that will measure the duty cycle of an input test signal. hw_timrot_timcount3 0x80068090 6 reload rw 0x0 set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. when set to zero, the timer enters a mode that freezes at a count of zero. when the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. 5:4 prescale rw 0x0 selects the divisor used for clock generation. the apbx clock is divided by the following amount. note the apbx clock itself is initially divided down from the 24.0-mhz crystal clock frequency. div_by_1 = 0x0 prescale: divide the apbx clock by 1. div_by_2 = 0x1 prescale: divide the apbx clock by 2. div_by_4 = 0x2 prescale: divide the apbx clock by 4. div_by_8 = 0x3 prescale: divide the apbx clock by 8. 3:0 select rw 0x0 selects the source for the timer "tick" that decrements the free running counter. note: programming an undefined value will result in "always tick" behavior. in duty cycle mode it increments the counter used to calculate the high and low cycle counts. never_tick = 0x0 never tick. freeze the count. pwm0 = 0x1 input from pwm0. pwm1 = 0x2 input from pwm1. pwm2 = 0x3 input from pwm2. pwm3 = 0x4 input from pwm3. pwm4 = 0x5 input from pwm4. rotarya = 0x6 input from rotary a. rotaryb = 0x7 input from rotary b. 32khz_xtal = 0x8 input from 32-khz crystal. 8khz_xtal = 0x9 input from 8 khz (divided from 32-khz crystal). 4khz_xtal = 0xa input from 4 khz (divided from 32-khz crystal). 1khz_xtal = 0xb input from 1 khz (divided from 32-khz crystal). tick_always = 0xc always tick. table 674. hw_timrot_timc trl3 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 18: timers and rotary decoder 495 description: this timer count register contains the programable and readback counter values for timer 3. the definitions of the fields change depending whether the timer is in normal or duty cycle mode. example: empty example. timrot xml revision: 1.39 table 675. hw_timrot_timcount3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 low_running_count high_fixed_count table 676. hw_timrot_timcount3 bit field descriptions bits label rw reset definition 31:16 low_running_count ro 0x00 in duty cycle mode, this bit field is loaded from the running counter when it has just finished measuring the low portion of the duty cycle. in normal timer mode, it shows the running count as a read-only value. 15:0 high_fixed_count rw 0x00 software loads the fixed count bit field with the value to count down. if the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. if the update bit is set to one, then the new value is also copied into the running count, immediately. if both the reload and update bits are set to zero, then the new value is never picked up by the running count. in duty cycle mode, this bit field is loaded from the running counter when it has finished measuring the high portion of the duty cycle. free datasheet http:/// STMP36XX official product documentation 5/3/06 496 chapter 18: timers and rotary decoder 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 497 19. real-time clock, alarm, watchdog, and persistent bits this chapter describes the real-time cloc k, alarm clock, watchdog reset, persistent bits, and millisecond counter included on the STMP36XX. progr ammable registers are described in section 19.7 . 19.1. overview the real-time clock (rtc), alarm, watchdog reset, and persistent bits share a com- mon source of one-millisecon d and one-second time pu lses and utiliz e persistent storage when the chip is in its powered-down state. figure 87 illustrates this block. note: the term power-down , as used here, refers to a state in which the dc-dc converter and various parts of the crystal power domain are still powered up, but the rest of the chip is powered down. if the batt ery is removed, then the persistent bits, the alarm value, and the second counter value will be lost. the crystal power domain powers both the 32-khz and 24-mhz crystals. upon battery insertion, the crystals (32- khz and 24-mhz) are in a quiescent state. whether and when either or both of these crystals are activated is under software control through the rtc persistent bits , as described later in this chapter. moreover, whether either or both of the crystals remain active during a power-down state is similarly controlled by software. the one-second time ba se is derived either from th e 24.0-mhz crys tal oscillator or the 32.768-khz crystal oscillator, as contro lled by the value of the corresponding bit in persistent register 0. the time base thus generated is used to increment the value of the persistent seconds count regist er. like the values of the other persistent registers, the value of the persistent seco nds count register is not lost across a power down state. whether this register continues to count seconds through a power down state or simply retains its value is under control of software. contrary to the one-second ti me base, no record or count is made of the one-milli- second time base in the crystal power domain. the on e-millisecond time base is always derived from the 24.0-mhz crysta l oscillator and is no t available when the chip is powered down. the real-time clock seconds counter, alarm functions, and persistent bit storage are kept in the crystal oscillator clock and po wer domain. shadow ve rsions of these val- ues are maintained in the cpu?s power and apbx clock domain when the chip is in a power-up state. when the chip transitions from power-off to power-on, the master values are copied to shadow values by the copy controller. whenever software writes to a shadow register, then the copy controller copies the new value into the master register in the cr ystal oscillator power domain. some of the persistent bits are used to control features that can continue to operate after power-down, such as the second counter and the alarm function. other persis- tent bits are available to store applic ation state informati on over power-downs. 64-bits are used to hold the sram repair configuration. this value is computed immediately after battery insertion (cold start) and stored for use in each subse- quent warm start. free datasheet http:/// STMP36XX official product documentation 5/3/06 498 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 immediately after reset, it can take severa l hundred clocks for the copy controller to complete the copy process from the analog domain to the digital domain. software cannot rely on the contents of the seconds co unter, alarm, or persistent bits until this copy is complete. therefore, software must wait until all bits of interest in the hw_rtc_stat_stale_regs field have been reset to zero by the copy controller before reading the initial state of these values (see figure 88 ). note that hw_rtc_persistent2 and hw_rtc_persi stent3 are the first ones read by the copy controller, so that the sram configuration data is available first. 1 khz 32-bit rtc seconds 32-bit rtc shadow counter 32-bit milliseconds counter 32-bit alarm master 32-bit alarm shadow == alarm event 32-bit master persistent 1 32-bit shadow persistent 1 32-bit master persistent 0 32-bit shadow persistent 0 copy controller crystal power and clock domain fixed divide by 24000 24-mhz xtal osc. divide by n rtc/wd/alarm/ persistent i/o arm core ahb slave ahb shared dma ahb master apbx master ahb-to-apbx bridge sram 32-bit master persistent 3 32-bit shadow persistent 3 32-bit master persistent 2 32-bit shadow persistent 2 1/768 = 31250hz 32.76-khz xtal osc. 32-bit laser fuse reg. 0 32-bit laser fuse reg. b . . . reader fsm 6 x 64 bit laser fuse array 32-bit watchdog counter divide by 31,250 or 32,768 1 hz 1 hz apbx figure 87. rtc, watchdog, alarm, and persistent bits block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 499 the rtc functions that are implemented in the crystal power domain are referred to as the rtc analog functions. these functi ons operate at 32.768 khz, generated by the 32.768-khz crystal oscillator when the clock source bi t is set to one (hw_rtc_persistent0_clock_source). when the clock source bit is set to zero, these functions operate on a clock domain derived from the 24.0-mhz crystal return rtc_first_init ultemp == 0 ? no yes wait for copy controller to complete for persistent 2 and 3. hw_rtc_ctrl_sftrst_write (bm_rtc_ctrl_sftrst); hw_rtc_ctrl_clkgate_write (bm_rtc_ctrl_clkgate); call during initialization remove soft reset and clock gate. this releases the copy controller. return rtc_second_init call at some point in initialization, after copy controller has had time to complete. ultemp3= hw_rtc_persistent3_rd(); hw_digctl_ramrepair0_wr (ultemp2); hw_digctl_ramrepair1_wr (ultemp3); copy persistent 2 and 3 to on-chip ram configuration. copy controller is finished, so it is safe to read a persistent register value. ultemp= hw_rtc_stat_stale_regs() & 0xc0; // persistent 2,3 ultemp2= hw_rtc_persistent2_read(); ultemp2[31] == 0 ? yes return no cold or warm start?? figure 88. rtc initialization sequence free datasheet http:/// STMP36XX official product documentation 5/3/06 500 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 oscillator divided by 768 to yield 31.250 khz. switching betw een these two clock domains is handled by a glitch-free clock mux. the 1-hz time base is derived by dividing either 32.768 khz by 32768 or by dividing 31.250 khz by 31,250, controlled by the clock_source bit. note that the clock mux is only glitch-free when switching from the 24.0-mhz crystal to the 32.768-khz crystal. the automatic write-back that occurs for each register as the copy controller ser- vices writes to the shadow registers can lead to some very long timing loops if effi- cient write procedures are not used. writing all six shadow registers can take up to 4 milliseconds to complete. a si ngle word write can be tr ansferred to the analog side of the rtc within 40 microseconds. do not attempt to write to more than one shadow register immediately before power down. registers are copied as pairs to the rtc analog section. while persistent registers 2 and 3 are marked as holding on-chip ram configuration information, software is free to reorder the location where this data is retained. there are no hardwired uses for any of the bits of persistent register s 1, 2, and 3. in addition there are no hard- wired uses for the upper portion of persistent register 0, i.e., hw_rtc_persistent0[31:16]. the lower half of persistent register 0 has spe- cific hardwired uses for each bit. figure 89 illustrates the timing of the analog/digital interf ace. registers are read in pairs from the rtc analog section, starting with persistent registers 2 and 3 (sram configuration information is needed very soon after power up), followed by the alarm register and persistent register 1, and finally the seconds counter and per- sistent register 0. rtc_d2a_req rtc_a2d_ack rtc_d2a_load rtc_d2a_shift rtc_d2a_data[7:0] rtc_a2a_data[7:0] cmd byte 0 byte 1 cmd byte 0 byte 1 clock-cross rtc_a2d_ack wait for rtc_a2d_ack complete xfer 6-cycles (rtc_d2a_shift) <3-cycles (apb_clk) <6-cycles (xtal_clk32k) read (hw_rtc_seconds) write (all_persistent_regs) read (all_persistent_regs, exclude (hw_rtc_seconds)) apbx_clk/hw_rtc_ctrl_clkdiv) command/address figure 89. analog/digital interface timing free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 501 note: copying registers in pairs to and from the analog side is basically an imple- mentation detail that has a minor effect on the time required to transfer a register write to the analog side. before a new value is written to a shadow register by the cpu, software must first confirm that the corresponding bit of hw_rtc_stat_newregs is a zero, as shown in figure 90 . this ensures that a value previ ously written to the register has been completely handled by the copy state machine. failure to obey this constraint could cause a newer updated value to be lost. return rtc_write2master testvalue == 0 no yes extract corresponding bit. testvalue = hw_rtc_stat_new_regs how to write any master register on analog side. do not call until after rtc_second_init. write new value to shadow that will be automatically copied to analog side. use this same technique for milliseconds, alarm, or other persistent registers. wait for previous write to this register to complete. hw_rtc_persistent2_wr(0xdeadbeef); testvalue=hw_rtc_stat_new_regs testvalue == 0 no hw_rtc_ctrl_force_update_wr(1); testvalue=hw_rtc_stat_stale_regs testvalue == 0 no state machine implementation errata requires this forced read before a second register is written. figure 90. rtc writing to a master register from cpu free datasheet http:/// STMP36XX official product documentation 5/3/06 502 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 19.2. real-time clock the real-time clock is a cpu-accessible, continuously-running 32-bit counter that increments every second and that can be derived from either the 24-mhz or the 32- mhz clock, as determined by a writable bit value in the rtc control register. a 32-bit second counter has enough resolution to count up to 136 years with one- second increments. the rtc can continue to count time as long as a voltage is applied to the batt pin, irrespective of w hether the rest of the chip is powered up. the normal digital reset has no effect on the master rtc registers located in the crystal power and clock domain. a special first-power-on reset establishes the default value of the master rtc registers. for consistency across applications, it is recommended that the second timer should be referenced to january 1, 1980 at a 32-bit value of zero (same epoch ref- erence as pc) in applications that use it as a time-of-day clock. if the real-time clock function is not present on a specific chip, as indicated in the control and status reg- ister (hw_rtc_stat_rtc_present), then no real-time epoch is maintained over power-down cycles. 19.2.1. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 19.3. millisecond resolu tion timing facility a millisecond counter facilit y is provided based on a 1-khz signal derived from either the 24-mhz clock. the count value is neither maintained nor incremented dur- ing power-down cycles. at each power-up, th is register is set to its reset state. on each tick of the 1-khz so urce, the milliseconds counter increments. with a 32-bit counter, a kernel can run up to 4,294,967,294 millisecon ds or 49.7 days before it must deal with a counter wrap. warning: when the 32.768-khz cryst al oscillator is selected as the source for the seconds counter, an anomaly is created be tween the time interv als of the millisec- ond counter and the seconds counter. that is, the manufacturing tolerance of the two crystals are such that 1000 millisecond coun ter increments are not exactly one second as measured by the real-time clock seconds counter. 19.4. alarm clock the alarm clock function allows an applicat ion to specify a future instant at which the chip should be awakened, i.e., if powered down, it can be powered up and the cpu can be interrupted. the alarm clock setting is a cpu-accessible, 32-bit value that is continuously matched against th e 32-bit real-time clock seconds counter. when the two values are equal, an alarm event is triggered. persistent bits indicate whether an alarm event should power up the chip from its powered-down state. in addition to or instead of powering up the chip, the alarm event can also cause a cpu interrupt. note: if the alarm is set to power up the chip in the event of an alarm and such an event occurs, then the only record of the wake-up cause is located in the analog side. at power-up, the analog side registers are copied to the digital shadow regis- ters and the alarm-wake bit is visible in the digital shadow register. if an alarm event free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 503 occurs that is not associated with a power up condition, the wake-up bit is only valid on the analog side. in this case, diagnostic software should force a copy from the analog side back to the digital shadow register before reading the alarm_wake status bit. 19.5. watchdog reset register the watchdog reset is a cpu-configurable device. it is programmed by software to generate a chip wide re set after hw_rtc_watchdo g milliseconds. the module generates this reset if software does not rewrite this register before this time elapses. the watchdog timer decrements once for every tick of the 1-khz clock sup- plied from the rtc analog section (see figure 87 ). the reset generated by the watchdog timer has no effect on the values retained in the master registers of the real-time clock seconds counter, alarm, or persistent registers. the watchdog timer is initially disabled and set to count 4,294,967,295 milliseconds before generating a watchdog reset. the watchdog timer does not run when the chip is in its powered-down state. there- fore, there is no master/shadow register pairing for the watchdog timer. the watch- dog timer must be ?present? on an actual chip to perform this function (see the hw_rtc_stat_watchdog_present bit description). 19.6. laser fuse bits the STMP36XX contains 384 laser programmable fuse bits. these bits are pro- grammed at the end of wafer processing and cannot be changed once the parts are packaged. separate documentation descri bes the usage and mapping of laser fuse bits to functions. the laser fuse bits can be read from registers contained in this block, if unlocked. refer to the register descriptions for information about unlocking and reading the laser fuse registers. provided that neither hw_laserfuse8_bits[31] nor hw_laserfu se8_bits[30] is set to one, then the laser fuse registers can be written by software. once either one of these bits is set, the laser fuse registers become strictly read-only. implementation note : this is different from the way the stmp35xx behaves. 19.7. programmable registers this section describes the programmable regi sters of the real-time clock, including the watchdog register, alarm register, laser fuse registers, and persistent registers. 19.7.1. real-time clock control register description hw_rtc_ctrl is the control register for the real-time clock, alarm, and watchdog timer. hw_rtc_ctrl 0x8005c000 hw_rtc_ctrl_set 0x8005c004 hw_rtc_ctrl_clr 0x8005c008 hw_rtc_ctrl_tog 0x8005c00c free datasheet http:/// STMP36XX official product documentation 5/3/06 504 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 table 677. hw_rtc_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsvd2 clkdiv rsvd1 suppress_copy2analog force_update watchdogen onemsec_irq alarm_irq onemsec_irq_en alarm_irq_en table 678. hw_rtc_ctrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 1= hold real-time clock digital side in soft reset state. this bit has no effect on the rtc analog section. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. this bit has no effect on the rtc analog section. 29:28 rsvd2 ro 0x0 reserved, write only zeroes. 27:24 clkdiv rw 0x2 sets the apbx clock divisor used to generate the rtc analog/digital interface clock. 0,1: interface clock is disabled. 2-15: interface clock divisor. 23:7 rsvd1 ro 0x0 reserved, write only zeroes. 6 suppress_copy2analog rw 0x0 this bit is used for diagnostic purposes. 1= suppress the automatic copy that normally occurs to the analog side, whenever a shadow register is written. 0= normal operation. use sct writes to set clear or toggle. normal = 0x0 data written to shadow registers is automatically copied to the analog side. no_copy = 0x1 suppress the automatic copying of write data to the analog side. 5 force_update rw 0x0 this bit is used for diagnostic purposes. 1= force analog side update. 0 = normal operation. use sct writes to set clear or toggle. as long as this bit is set, the copy controller will attempt to copy all six registers from the analog side to the digital side. software should set this bit, then reset it as soon as practical. then software should poll the hw_rtc_stat_stale bit field until it goes to zero. normal = 0x0 stale data on the anlog side is copied to the shadows as appropriate. force_copy = 0x1 force automatic copying of write data from the analog side to the shadow registers. 4 watchdogen rw 0x0 1= enable watchdog timer to force chip wide resets. use sct writes to set clear or toggle. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 505 description: the contents of this register control th e operation of the rtc portions implemented as an apbx peripheral running in the apbx clock domain. thes e functions operate only when the chip is in its full power-up state. example: hw_rtc_ctrl_clr(bm_rtc_ctrl_sftrst); // remove the soft reset condition hw_rtc_ctrl_clr(bm_rtc_ctrl_clkgate); // enable clocks within the rtc while(hw_rtc_stat.stale_regs !=0) { printf(" something is stale in one of the digital side registers // the copy controller will copy analog registers to digtial registers as required, // turning off staleregs bits as it goes about its business. } if(hw_rtc_stat.watchdog_present != 0) // then you can use the watchdog timer on this chip 19.7.2. real-time clock status register description hw_rtc_stat is the status register for the real-time clock, alarm, and watchdog timer. hw_rtc_stat 0x8005c010 hw_rtc_stat_set 0x8005c014 hw_rtc_stat_clr 0x8005c018 hw_rtc_stat_tog 0x8005c01c 3 onemsec_irq rw 0x0 1= one-millisecond interrupt request status. use sct writes to clear this interrupt status bit. 2 alarm_irq rw 0x0 1= alarm interrupt status. use sct writes to clear this interrupt status bit. 1 onemsec_irq_en rw 0x0 1= enable one-millisecond interrupt. use sct writes to set clear or toggle. 0 alarm_irq_en rw 0x0 1= enable alarm interrupt. use sct writes to set clear or toggle. table 679. hw_rtc_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rtc_present alarm_present watchdog_present xtal32768_present rsvd3 stale_regs rsvd2 new_regs rsvd1 fuse_unlock fuse_done table 678. hw_rtc_ctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 506 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 description: the contents of this register control the operation of the portions of the rtc that are implemented as an apbx per ipheral running in the apbx clock domain. these functions operate only when the chip is in its full power-up state. example: hw_rtc_ctrl_clr(bm_rtc_ctrl_sftrst); // remove the soft reset condition hw_rtc_ctrl_clr(bm_rtc_ctrl_clkgate); // enable clocks within the rtc hw_rtc_ctrl_clr(bm_rtc_ctrl_alarm_irq); // reset the alarm interrupt by clearing its sta- tus bit while(hw_rtc_stat.stale_regs !=0) { printf(" something is stale in one of the digital side registers // the copy controller will copy analog registers to digtial registers as required, // turning off staleregs bits as it goes about its business. } 19.7.3. real-time clock milliseconds counter description the real-time clock millisec onds counter register pr ovides a reliable elapsed time reference to the kernel with millisecond resolution. hw_rtc_milliseconds 0x8005c020 hw_rtc_milliseconds_set 0x8005c024 hw_rtc_milliseconds_clr 0x8005c028 table 680. hw_rtc_stat bit field descriptions bits label rw reset definition 31 rtc_present ro 0x1 this read-only bit reads back a one if the rtc is present in the device. 30 alarm_present ro 0x1 this read-only bit reads back a one if the alarm function is present in the device. 29 watchdog_present ro 0x1 this read-only bit reads back a one if the watchdog timer function is present in the device. 28 xtal32768_present ro 0x1 this read-only bit reads back a one if the 32.768-khz crystal oscillator function is present in the device. 27:22 rsvd3 ro 0x0 reserved, write only zeroes. 21:16 stale_regs ro 0x3f these read-only bits are set to one whenever the corresponding shadow register contents are older than the analog side contents. these bits are set by reset and cleared by the copy controller. they are also set by writing a one to the force_update bit. 15:14 rsvd2 ro 0x0 reserved, write zeroes only. 13:8 new_regs ro 0x00 these read-only bits are set to one whenever the corresponding shadow register contents are newer than the analog side contents. these bits are set by writing to the corresponding register and cleared by the copy controller. 7:2 rsvd1 ro 0x0 reserved, write zeroes only. 1 fuse_unlock ro 0x0 this read-only bit reads back a one if the laser fuse registers are unlocked. 0 fuse_done ro 0x1 reflects the state of the laser fuse reader. 1=laser fuse reader has finished. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 507 hw_rtc_milliseconds_tog 0x8005c02c description: hw_rtc_mseconds provides access to the 32-bit millisec onds counter. this counter is not a shadow register, i.e., the contents of this register are not preserved over power-down states. this counter incr ements once per millis econd from a clock source derived from the 24.0-mhz crystal cl ock. this 1-khz source does not vary as the apbx clock frequency is changed. the millisecond counter wraps at 4, 294,967,294 millisecon ds or 49.7 days. example: hw_rtc_milliseconds_wr(0); // write an initial starting value to the milliseconds counter count = hw_rtc_milliseconds_rd(); // read the current value of the milliseconds counter. 19.7.4. real-time clock seconds counter register description the real-time clock seconds counter register is used to maintain real time for applications, even across cert ain chip power-down states. hw_rtc_seconds 0x8005c030 hw_rtc_seconds_set 0x8005c034 hw_rtc_seconds_clr 0x8005c038 hw_rtc_seconds_tog 0x8005c03c description: hw_rtc_seconds provides access to the 32-bit real-time seconds counter. both the shadow register on the digi tal side and the analog side register update every second. when the chip enters the po wer-down state, the shadow register is powered down and loses its state value. when the chip powers up, the analog side register contents are automatically copied to the shadow register. the reset value of table 681. hw_rtc_milliseconds 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 count table 682. hw_rtc_milliseconds bit field descriptions bits label rw reset definition 31:0 count rw 0x00000000 32-bit milliseconds counter. table 683. hw_rtc_seconds 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 count table 684. hw_rtc_seconds bit field descriptions bits label rw reset definition 31:0 count rw 0x00000000 increments once per second. free datasheet http:/// STMP36XX official product documentation 5/3/06 508 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 0x22222222 for the digital side register is only visible until the copy controller over- writes with the value from the analog side . the analog side register resets to zero upon power-on reset (por), i.e., when the battery is first inserted or whenever a battery-less part is plugged into usb power or into a wall transformer. example: hw_rtc_seconds_wr(0); // write an initial value to the digital side. this value will // be automatically copied to the analog side rt_clock = hw_rtc_seconds_rd(); // read the 32 seconds counter value 19.7.5. real-time clock alarm register description the 32-bit alarm value is matched against the 32-bit seconds counter to detect an alarm condition. hw_rtc_alarm 0x8005c040 hw_rtc_alarm_set 0x8005c044 hw_rtc_alarm_clr 0x8005c048 hw_rtc_alarm_tog 0x8005c04c description: the 32-bit alarm value can be used to awaken the chip from a power-down state or simply to cause an interrupt at a specific time. when the chip enters the power-down st ate, the shadow register is powered down and loses its state value. when the chip powers up, the analog side register con- tents are automatically copied to the shadow register. the reset value of 0x33333333 for the digital side register is only visible until the copy controller over- writes with the value from the analog side . the analog side register resets to zero upon power-on reset (por), i.e., when the battery is first inserted or whenever a battery-less part is plugged into a power usb or into a wall transformer. example: hw_rtc_alarm_wr(60); // generate rtc alarm after 60 seconds 19.7.6. watchdog timer register description the 32-bit watchdog timer can be used to reset the chip if enabled and not ade- quately serviced. hw_rtc_watchdog 0x8005c050 hw_rtc_watchdog_set 0x8005c054 hw_rtc_watchdog_clr 0x8005c058 hw_rtc_watchdog_tog 0x8005c05c table 685. hw_rtc_alarm 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 value table 686. hw_rtc_alarm bit field descriptions bits label rw reset definition 31:0 value rw 0x00000000 seconds match-value used to trigger assertion of the rtc alarm. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 509 description: the 32-bit watchdog time r will reset the chip upon dec rementing to zero, if this function is enabled and present on the chip. the 1-khz source is derived from the 24-mhz crystal osc illator and does no t vary when the apbx clock is changed. example: hw_rtc_watchdog_wr(10000); // reload the watchdog and keep it from resetting the chip 19.7.7. persistent state register 0 description the 32-bit persistent registers are used to retain certain control states during chip- wide power-down states. bits in this register are used by the rom and the sdk. refer to the sdk documentation for more specific information about the bits in this register and how they are allocated. hw_rtc_persistent0 0x8005c060 hw_rtc_persistent0_set 0x8005c064 hw_rtc_persistent0_clr 0x8005c068 hw_rtc_persistent0_tog 0x8005c06c table 687. hw_rtc_watchdog 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 count table 688. hw_rtc_watchdog bit field descriptions bits label rw reset definition 31:0 count rw 0xffffffff if the watc hdog timer decrements to zero and the watchdog timer reset is enabled, then the chip will be reset. the watchdog timer decrements once per millisecond, when enabled. table 689. hw_rtc_persistent0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 general dcdc_ctrl xtal32_pdown xtal24_pdown alarm_wake_en alarm_en alarm_wake clocksource free datasheet http:/// STMP36XX official product documentation 5/3/06 510 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 table 690. hw_rtc_persistent0 bit field descriptions bits label rw reset definition 31:16 general rw 0x0000 firmware use, defined as follows: sdram_boot = 0x8000 boot from sdram. enumerate_500ma_twice = 0x4000 enumerate at 500ma twice before dropping back to 100ma. usb_boot_player_mode = 0x2000 boot to player when connected to usb. skip_checkdisk = 0x1000 run checkdisk flag. usb_low_power_mode = 0x0800 usb hi/lo current select. otg_hnp_bit = 0x0400 hnp has been required if set to one. otg_atl_role_bit = 0x0200 usb role. sdram_cs_hi = 0x0100 msb of two bit field recording which chip select (0-3) the sdram is connected to. sdram_cs_lo = 0x0080 lsb of two bit field recording which chip select (0-3) the sdram is connected to. sdram_ndx_3 = 0x0040 sdram configuration table index bit 3 sdram_ndx_2 = 0x0020 sdram configuration table index bit 2 sdram_ndx_1 = 0x0010 sdram configuration table index bit 1 sdram_ndx_0 = 0x0008 sdram configuration table index bit 0 etm_enable = 0x0004 etm enable bit (0 = disabled, 1 = enabled) 15:6 dcdc_ctrl rw 0x1 these bits are proprietary to sigmatel. customers should contact sigmatel before changing them from their default value. sd_present = 0x200 set to one to disable startup using internal oscillator. this bit should be set when using 24mhz as the source for the rtc. setting this bit from 0 to 1 will also powerdown the 3600 after 500ns , so this should only be set immediately before powering down the chip via the pwd bit in hw_power_reset. lowbat_3p0 = 0x100 set to one to change lithium-ion low-battery threshold to 3.0 v. set to zero for 2.7-v threshold. selfbias_pwrup = 0x080 set to one to enable the self bias circuit to remain powered up when the device is powered down. this bit must also be set to allow 24-mhz crystal to be used as an rtc. auto_restart = 0x040 set to one to enable the chip to automatically power up approxima tely 180 ms after powering down. detect_lowbat = 0x020 set to one to enable 24-mhz crystal, in an rtc application, to turn off when the battery falls below threshold. the threshold is determined by lowbat_3p0. drop_bias1 = 0x010 set to one to decrease 24-mhz crystal bias current. drop_bias2 = 0x008 set to one to decrease 24-mhz crystal bias current an additional amount to take it a 50 percent reduction. spare = 0x004 not connected to an y specific hardware function. disable_xtalstop = 0x002 set to one to disable the circuit that resets the chip if 24-mhz frequency falls below 2 mhz. the circuit defaults to enabled and will power dow n the device if the 24-mhz stop oscillating for any reason. spare2 = 0x001 not connected to any specific hardware function. 5 xtal32_pdown rw 0x1 set to one to power down the 32.768-khz crystal oscillator and its power domain, including the real time clock and persistent bits (default). set to zero to enable the crystal oscillator and its power domain to remain on while the rest of the chip is in the power-down state. 4 xtal24_pdown rw 0x1 set to one to power down the 24.0-mhz crystal oscillator, including the re al-time clock and persistent bits (default). set to zero to enable the crystal oscillator and its power domain to remain on while the rest of the chip is in the power down state. when setting this bit to zero, it is also necessary to set selfbias_pwrup, and sd_present. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 511 description: the register initalizes to a known reset pattern. the copy controller overwrites the digital reset values very soon after power on, but not in zero time. example: hw_rtc_persistent0_set(bm_rtc_persistent0_alarm_wake_en); // wake up the chip if the alarm event occurs hw_rtc_persistent0_set(bm_rtc_persistent0_clocksource); // select the 32khz oscillator as the source for the rtc analog clock 19.7.8. persistent state register 1 description the 32-bit persistent registers are used to retain certain control states during chip- wide power-down states. bits in this register are used by the rom and the sdk, and some are reserved for customers. refer to the sdk documentation for more specific information about the bits in this register and how they are allocated. hw_rtc_persistent1 0x8005c070 hw_rtc_persistent1_set 0x8005c074 hw_rtc_persistent1_clr 0x8005c078 hw_rtc_persistent1_tog 0x8005c07c 3 alarm_wake_en rw 0x0 set this bit to one to wake up the chip upon the arrival of an alarm event. alarm_en must be set to one to enable the detection of an alarm event. when the alarm is not present in the device (as indicated by the fuse bits) the copy of shadow0 to persistent0 will not allow bits[2:3] to be written and persistent bits[2:3] will always read back 0, regardless of the values in the shadow register. 2 alarm_en rw 0x0 set this bit to one to enable the detection of an alarm event. this bit must be turned on before an alarm event can awaken a powered-down device, or before it can generate an alarm interrupt to a powered-up cpu. when the alarm is not present in the device (as indicated by the fuse bits) the copy of shadow0 to persistent0 will not allow bits[2:3] to be written and persistent bits[2:3] will always read back 0, regardless of the values in the shadow register. 1 alarm_wake rw 0x0 this bit is set to one to upon the arrival of an alarm event that powers up the chip. alarm_en must be set to one to enable the detection of an alarm event. this bit is reset by writing a zero directly to the shadow register, which causes the copy controller to move it across to the analog domain. 0 clocksource rw 0x0 set to one to select the 32-khz crystal oscillator as the source for the 32-khz clock domain used by the rtc analog domain circuits. set to zero to select the 24-mhz crystal oscillator as the source for generating the 32-khz clock domain used by the rtc analog domain circuits. table 690. hw_rtc_persistent0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 512 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 description: the register initalizes to a known reset pattern. the copy controller overwrites this digital reset value very soon after power on, but not in zero time. example: hw_rtc_persistent1_wr(0x12345678); // this write will ultimately push data to the analog side via the copy controller 19.7.9. persistent state (on-chip ram configuration) register 2 description the 32-bit persistent registers are used to retain certain control states during chip- wide power-down states. bits in this regist er are used by the sdk. refer to the sdk documentation for more specific information. hw_rtc_persistent2 0x8005c080 hw_rtc_persistent2_set 0x8005c084 hw_rtc_persistent2_clr 0x8005c088 hw_rtc_persistent2_tog 0x8005c08c description: after the post runs and determines the necessary startup conditions, software copies the setup information here. at each subsequent power-up, these values are copied to the sram configuration. the register initalizes to a known reset pattern. the copy controller overwrites this digital reset value very soon afte r power-on, but no t in zero time. example: hw_rtc_persistent2_wr(0x12345678); // this write will ultimately push data to the analog side via the copy controller table 691. hw_rtc_persistent1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 general table 692. hw_rtc_persistent1 bit field descriptions bits label rw reset definition 31:0 general rw 0x00000000 general-use persistent bits. table 693. hw_rtc_persistent2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sram_lo table 694. hw_rtc_persistent2 bit field descriptions bits label rw reset definition 31:0 sram_lo rw 0x00000000 see the sdk documentation. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 513 19.7.10. persistent state (on-chip ram configuration) register 3 description the 32-bit persistent registers are used to retain certain control states during chip- wide power-down states. bits in this regist er are used by the sdk. refer to the sdk documentation for more specific information. hw_rtc_persistent3 0x8005c090 hw_rtc_persistent3_set 0x8005c094 hw_rtc_persistent3_clr 0x8005c098 hw_rtc_persistent3_tog 0x8005c09c description: after the post runs and determines the necessary startup conditions, software copies the setup information here. at each subsequent power up, these values are copied to the sram configuration. the register initalizes to a known reset pattern. the copy controller overwrites this digital reset value very soon after power on, but not in zero time. example: hw_rtc_persistent3_wr(0x12345678); // this write will ultimately push data to the analog side via the copy controller 19.7.11. real-time clock debug register description this 32-bit register provides debug read access to various internal states for diag- nostic purposes. hw_rtc_debug 0x8005c0a0 hw_rtc_debug_set 0x8005c0a4 hw_rtc_debug_clr 0x8005c0a8 hw_rtc_debug_tog 0x8005c0ac table 695. hw_rtc_persistent3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sram_hi table 696. hw_rtc_persistent3 bit field descriptions bits label rw reset definition 31:0 sram_hi rw 0x00000000 see the sdk documentation. free datasheet http:/// STMP36XX official product documentation 5/3/06 514 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 description: read-only view into the internals of th e digital side of the rtc for diagnostic pur- poses. example: debugvalue = hw_rtc_debug_rd(); // read debug register value 19.7.12. rtc unlock register description when the rtc unlock register is written with a specific key, then the laser fuse reg- isters become readable. they may be writable, provided the laser fuse contents have not locked out write operations. hw_rtc_unlock 0x8005c200 hw_rtc_unlock_set 0x8005c204 hw_rtc_unlock_clr 0x8005c208 hw_rtc_unlock_tog 0x8005c20c table 697. hw_rtc_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 watchdog_reset_mask watchdog_reset table 698. hw_rtc_debug bit field descriptions bits label rw reset definition 31:2 rsvd0 ro 0x0 debug read-only view of various state machine bits. 1 watchdog_reset_mask rw 0x0 when set, masks the reset generation by the watchdog timer for testing purposes. 0 watchdog_reset ro 0x0 reflects the state of the watchdog reset. used for testing purposes so that the watchdog can be tested without resetting part. when set, watchdog reset is asserted. table 699. hw_rtc_unlock 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 key free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 515 description: when access to th e laser fuse registers is unlocked, they read back the actual val- ues. when access is denied, all 12 laser fuse registers read back all zeroes. in addi- tion to this lock field, there are two lock bits within the laser fuse registers (rtc_laserfuse9 bits 31:30). if either one of these two bits is set to one, then further writes to the laser fuse registers are denied under any condition. the rtc_unlock register always reads back 0x0, use the rtc_stat fuse_unlock status bit to determine the current lock status. the rtc unlock register has no persistence over any power-down state. example: hw_rtc_unlock_wr(bv_rtc_unlock_key__val); // unlock laser fuse access hw_rtc_unlock_wr(0); // lock them back up so they can't be read or written 19.7.13. hw laser fuse register 0 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse0 0x8005c300 hw_rtc_laserfuse0_set 0x8005c304 hw_rtc_laserfuse0_clr 0x8005c308 hw_rtc_laserfuse0_tog 0x8005c30c description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(0); // read laser fuse register value table 700. hw_rtc_unlock bit field descriptions bits label rw reset definition 31:0 key rw 0x0 write 0xc6a83957 (bv_rtc_unlock_key__val) to unlock access to the lase r fuse registers. this register always reads back 0x0. use the rtc_stat fuse_unlock status bit to determine whether laserfuses are currently locked or not. val = 0xc6a83957 key value needed to unlock laser fuse registers. table 701. hw_rtc_laserfuse0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 702. hw_rtc_laserfuse0 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r1f31 through r1f00. free datasheet http:/// STMP36XX official product documentation 5/3/06 516 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 19.7.14. hw laser fuse register 1 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse1 0x8005c310 hw_rtc_laserfuse1_set 0x8005c314 hw_rtc_laserfuse1_clr 0x8005c318 hw_rtc_laserfuse1_tog 0x8005c31c description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(1); // read laser fuse register value 19.7.15. hw laser fuse register 2 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse2 0x8005c320 hw_rtc_laserfuse2_set 0x8005c324 hw_rtc_laserfuse2_clr 0x8005c328 hw_rtc_laserfuse2_tog 0x8005c32c description: table 703. hw_rtc_laserfuse1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 704. hw_rtc_laserfuse1 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r1f63 through r1f32. table 705. hw_rtc_laserfuse2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 706. hw_rtc_laserfuse2 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r2f31 through r2f00. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 517 these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(2); // read laser fuse register value 19.7.16. hw laser fuse register 3 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse3 0x8005c330 hw_rtc_laserfuse3_set 0x8005c334 hw_rtc_laserfuse3_clr 0x8005c338 hw_rtc_laserfuse3_tog 0x8005c33c description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(3); // read laser fuse register value 19.7.17. hw laser fuse register 4 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse4 0x8005c340 hw_rtc_laserfuse4_set 0x8005c344 hw_rtc_laserfuse4_clr 0x8005c348 hw_rtc_laserfuse4_tog 0x8005c34c table 707. hw_rtc_laserfuse3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 708. hw_rtc_laserfuse3 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r2f63 through r2f32. table 709. hw_rtc_laserfuse4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits free datasheet http:/// STMP36XX official product documentation 5/3/06 518 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(4); // read laser fuse register value 19.7.18. hw laser fuse register 5 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse5 0x8005c350 hw_rtc_laserfuse5_set 0x8005c354 hw_rtc_laserfuse5_clr 0x8005c358 hw_rtc_laserfuse5_tog 0x8005c35c description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(5); // read laser fuse register value 19.7.19. hw laser fuse register 6 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse6 0x8005c360 hw_rtc_laserfuse6_set 0x8005c364 hw_rtc_laserfuse6_clr 0x8005c368 hw_rtc_laserfuse6_tog 0x8005c36c table 710. hw_rtc_laserfuse4 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r3f31 through r3f00. table 711. hw_rtc_laserfuse5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 712. hw_rtc_laserfuse5 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r3f63 through r3f32. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 519 description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(6); // read laser fuse register value 19.7.20. hw laser fuse register 7 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse7 0x8005c370 hw_rtc_laserfuse7_set 0x8005c374 hw_rtc_laserfuse7_clr 0x8005c378 hw_rtc_laserfuse7_tog 0x8005c37c table 713. hw_rtc_laserfuse6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 714. hw_rtc_laserfuse6 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r4f31 through r4f00. table 715. hw_rtc_laserfuse7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 716. hw_rtc_laserfuse7 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r4f63 through r4f32. alt_force_post = 0x80000000 or with force_post, below. alt_force_repair = 0x40000000 or with force_repair, below. alt_disable_recovery_mode = 0x20000000 or with disable_recovery, below. alt_icache_ctrl = 0x10000000 or with icache_ctrl, below. alt_ils_margin_bits = 0x00070000 or with ils_margin_bits, below. force_post = 0x00008000 or with alt_force_post, above. force_repair = 0x00004000 or with alt_force_repair, above. disable_recovery_mode = 0x00002000 or with alt_disable_recovery, above. icache_ctrl = 0x00001000 or with alt_icache_ctrl, above. ils_margin_bits = 0x00000007 or with alt_ils_margin_bits, above. free datasheet http:/// STMP36XX official product documentation 5/3/06 520 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(7); // read laser fuse register value 19.7.21. hw laser fuse register 8 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse8 0x8005c380 hw_rtc_laserfuse8_set 0x8005c384 hw_rtc_laserfuse8_clr 0x8005c388 hw_rtc_laserfuse8_tog 0x8005c38c description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(8); // read laser fuse register value 19.7.22. hw laser fuse register 9 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse9 0x8005c390 hw_rtc_laserfuse9_set 0x8005c394 hw_rtc_laserfuse9_clr 0x8005c398 hw_rtc_laserfuse9_tog 0x8005c39c table 717. hw_rtc_laserfuse8 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 718. hw_rtc_laserfuse8 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r5f31 through r5f00. table 719. hw_rtc_laserfuse9 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 19: real-time cloc k, alarm, watchdog, and persistent bits 521 description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. bits [31:24] contain the alternate device identifier extension that appears in the chip revision register. example: fusevalue = hw_rtc_laserfusen_rd(9); // read laser fuse register value 19.7.23. hw laser fuse register 10 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse10 0x8005c3a0 hw_rtc_laserfuse10_set 0x8005c3a4 hw_rtc_laserfuse10_clr 0x8005c3a8 hw_rtc_laserfuse10_tog 0x8005c3ac description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked, then they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. example: fusevalue = hw_rtc_laserfusen_rd(10); // read laser fuse register value 19.7.24. hw laser fuse register 11 description this 32-bit laser fuse register provides software access to a portion of the 384-bit laser fuse. hw_rtc_laserfuse11 0x8005c3b0 hw_rtc_laserfuse11_set 0x8005c3b4 hw_rtc_laserfuse11_clr 0x8005c3b8 table 720. hw_rtc_laserfuse9 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r5f63 through r5f32. alt_skip_repair = 0x00040000 or with skip_repair, below. skip_repair = 0x00000400 or with alt_skip_repair, above. table 721. hw_rtc_laserfuse10 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 722. hw_rtc_laserfu se10 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r6f31 through r6f00. free datasheet http:/// STMP36XX official product documentation 5/3/06 522 chapter 19: real-time clock, alarm, watch dog, and persistent bits 5-36xx-d1-1.02-050306 hw_rtc_laserfuse11_tog 0x8005c3bc description: these bits are loaded from the laser fuse blocks at first power on. if the laser fuse bits are not locked then, they can be written by the cpu. setting either hw_laserfuse8_bits[31] or hw_laserfu se8_bits[30] to on e locks all sub- sequent writes. bits [31:24] contain the de vice identifier extension which appears in the chip revision register. example: fusevalue = hw_rtc_laserfusen_rd(11); // read laser fuse register value rtc xml revision: 1.82 table 723. hw_rtc_laserfuse11 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 bits table 724. hw_rtc_laserfuse11 bit field descriptions bits label rw reset definition 31:0 bits rw 0x0 laser fuse bits r6f63 through r6f32. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 20: pulse-width modulator (pwm) controller 523 20. pulse-width modula tor (pwm) controller this chapter describes the pulse-width modulator (pwm) controller included on the STMP36XX and how to use it. programmable registers are described in section 20.5 . 20.1. overview the STMP36XX contains five pwm output co ntrollers that can be used in place of gpio pins. applications include led bright ness control and high voltage generators for electroluminescent lamp (e.l.) display back lights. independent output control of each phase allows zero, one, or high-z to be independently selected for the active and inactive phases. individual outputs can be run in lock step with guaranteed non- overlapping portions for differential drive applications. figure 91 shows the block diagram of the pwm controller. the controller does not use dma. initial values of period, active, and inactive widths are set for each desired channel. the outputs are selected by phase and then the desired pwm channels are simultaneously enabled. this effectively launches the pwm outputs to autonomously drive their loads without further intervention. in backlit high-voltage applications, a fe ed-forward control can be periodically used to change the count parameters based on lradc evaluation of the battery state. feedback control can be provided by assigning one lradc channel to monitor the integrating capacitor voltage. care must be taken to protect the lradc from cata- strophic over-voltage in this case. for mo st electroluminescent (el) backlight appli- cations, open loop control with precisio n pwm timers based on a stable crystal oscillator is sufficient. 20.2. operation each pwm channel has two control register s that are used to specify the channel output: hw_pwm_activex and hw_pwm_periodx. when programming a channel, it is important to remember that there is an order dependence for register writes. ? the hw_pwm_activex register mu st be written first, followed by hw_pwm_periodx. ? if the order is reversed, the parame ters written to the hw_pwm_activex register will not take ef fect in th e hardware. the hardware waits for a hw_pwm_periodx register write to update the hard- ware with the values in both registers. this register write order dependence allows smooth on-the-fly reprogramming of the channel. also, when the user reprograms the channel in this manner, the new register va lues will not take effect until the beginning of a new output period. this eliminates the potential for output glitches that could occur if the registers were updated while the channel was enabled and in the middle of a cycle. free datasheet http:/// STMP36XX official product documentation 5/3/06 524 chapter 20: pulse-width modulator (pwm) controller 5-36xx-d1-1.02-050306 pwm programmable registers 1/m, m=1,2,4, 8,16, 64, 256,1024 24-mhz xtal osc. period 0 active 1 ,inactive 1 count1 resets at period 1 pwm1 count2 resets at period 2 pwm2 count3 resets at period 3 pwm3 active 0 ,inactive 0 count0 resets at period 0 pwm0 act act.,inact. state 0 active 2 ,inactive 2 active 3 ,inactive 3 act act act 24-mhz xtal osc. divide by n arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram 1/m, m= 1,2,4, 8,16, 64, 256,1024 1/m, m=1,2,4, 8,16, 64, 256,1024 count4 resets at period 4 pwm4 active 4 ,inactive 4 act active 3 >= count 3 count 3 < inactive 3 active 0 >= count 0 count 0 < inactive 0 active 2 >= count 2 count 2 < inactive 2 active 1 >= count 1 count 1 < inactive 1 active 4 >= count 4 count 4 < inactive 4 1/m, m=1,2,4, 8,16, 64, 256,1024 1/m, m=1,2,4, 8,16, 64, 256,1024 e.l. backlight e.l. backlight e.l. backlight application otg power figure 91. pulse-width modulation controller (pwm) block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 20: pulse-width modulator (pwm) controller 525 each channel has a dedicated internal 16-bit counter that increments once for each divided clock period presented from the clock divider. ? the internal counter resets when it reaches the value stored in the channel control registers, e.g., hw_pwm_period0_period. ? the active flip-flop is set to one when the internal counter reaches the value stored in hw_pwm_active0_active. ? it remains high until the internal counter exceeds the value stored in hw_pwm_active0_inactive. these two values define the starting and ending points for the logically ?active? por- tion of the waveform. as shown in figure 92 , the actual state on the output for each phase, e.g., active or inactive, is comple tely controlled by the active and inactive state values in the channel control registers. the actual values obtainable on the output are shown in figure 93 . notice that one possible state is to turn off the output driver to provide a high-z output. this is useful for external circuits that drive e.l. backlights and for direct drive of leds. by setting up two channels in lock step and by setting their low and high states to opposite values, one can generate a differen tial signal pair that alternates between pulling to vss and floating to high-z. by crea ting an appropriate of fset in the settings of the two channels with the same period and the same enables, one can generate differential drive pulses with digitally guaranteed non-overlapping intervals suitable for controlling high-voltage switches. active_ff period pwm0 output inactive_state[1:0] active_state[1:0] active hw_pwm_period0_period inactive_state[1:0] active_state[1:0] hw_pwm_active0_active hw_pwm_period0_active_state hw_pwm_period0_inactive_state inactive hw_pwm_active0_inactive figure 92. pwm output example free datasheet http:/// STMP36XX official product documentation 5/3/06 526 chapter 20: pulse-width modulator (pwm) controller 5-36xx-d1-1.02-050306 in figure 93 , a differential pair is established using channel zero and channel one. the period is set for 1280 divided clocks for both channels. all active phases are set for 600 divided clocks. there is a 40 divided clock guaranteed off-time between each active phase. since this is based on a crystal oscillato r, it is a very stable non- overlapping period. the tota l period is also a very st able crystal-oscillator-based time interval. in this example, the active phases are pulled to vss (ground), while the inactive phases are allowed to float to a high-z state. figure 94 shows the generation of the pwm channel 3 output. this channel controls the output pin when pwm control is selected in pinctrl block and hw_pwm_ctrl_pwm3_enable is set to on e. the output pin can be set to a zero, a one, or left to float in the high-impedance state. these choices can be made independently for either the active or inactive phase of the output. 20.3. multi-chip attachment mode the multi-chip attachment mode (matt) allows a 24-mhz crystal clock that is an input to the STMP36XX to be routed to the pwm output pins. in this case, the normal pwm programming parameters (e.g., pe riod, active, etc.) are ignored. this mode allows for supplying and controlling the crystal clo ck for external application interfaces, as shown in figure 94 . active_ff0 pwm0 output hi-z pwm1 output vss active_ff1 600 600 40 40 640 680 digitally guaranteed hw_pwm_period0_period = 1280 hw_pwm_active0_active = 0 hw_pwm_active0_inactive = 600 hw_pwm_period0_active_state = 10 hw_pwm0br_inacti ve_state = 00 hw_pwm_period1= 1280 hw_pwm_active1 = 640 hw_pwm_inactive1 = 1240 hw_pwm_active1_state = 10 hw_pwm_inactive1_state = 00 figure 93. pwm differential output pair example free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 20: pulse-width modulator (pwm) controller 527 20.4. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 20.5. programmable registers the following registers are available for cpu programmer access and control of the pwm controller. 20.5.1. pwm control and status register 0 description the pwm control and status re gister 0 specifies the rese t state, availability, and the enables for the five pwm units. hw_pwm_ctrl 0x80064000 hw_pwm_ctrl_set 0x80064004 hw_pwm_ctrl_clr 0x80064008 hw_pwm_ctrl_tog 0x8006400c table 725. hw_pwm_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate pwm4_present pwm3_present pwm2_present pwm1_present pwm0_present rsrvd1 pwm4_enable pwm3_enable pwm2_enable pwm1_enable pwm0_enable pwm output pwm active_state [bit 1] pwm inactive_state [bit 1] pwm active_state [bit 0] pwm inactive_state [bit 0] pwm enable bit 24 mhz xtal clk 1 active ff 0 1 0 1 0 matt mode bit figure 94. pwm output driver free datasheet http:/// STMP36XX official product documentation 5/3/06 528 chapter 20: pulse-width modulator (pwm) controller 5-36xx-d1-1.02-050306 description: the pwm control and status register 0 sp ecifies the reset stat e, availability, and the enables for the five pwm elements. example: empty example. 20.5.2. pwm channel 0 active register description the pwm channel 0 active register specifie s the active time and inactive time for channel 0. hw_pwm_active0 0x80064010 hw_pwm_active0_set 0x80064014 hw_pwm_active0_clr 0x80064018 hw_pwm_active0_tog 0x8006401c table 726. hw_pwm_ctr l bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 this bit must be set to zero for normal operation. when set to one, it forces a block-wide reset. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. 29 pwm4_present ro 0x1 0= pwm4 is not present in this product. 28 pwm3_present ro 0x1 0= pwm3 is not present in this product. 27 pwm2_present ro 0x1 0= pwm2 is not present in this product. 26 pwm1_present ro 0x1 0= pwm1 is not present in this product. 25 pwm0_present ro 0x1 0= pwm0 is not present in this product. 24:5 rsrvd1 ro 0x0 always write zeroes to this bit field. 4 pwm4_enable rw 0x0 enables pwm channel 4 to begin cycling when set to one. to enable pwm4 onto the output pin, the pinctl registers must programmed accordingly. 3 pwm3_enable rw 0x0 enables pwm channel 3 to begin cycling when set to one. to enable pwm3 onto the output pin, the pinctl registers must programmed accordingly. 2 pwm2_enable rw 0x0 enables pwm channel 2 to begin cycling when set to one. to enable pwm2 onto the output pin, the pinctl registers must programmed accordingly. 1 pwm1_enable rw 0x0 enables pwm channel 1 to begin cycling when set to one. to enable pwm1 onto the output pin, the pinctl registers must programmed accordingly. 0 pwm0_enable rw 0x0 enables pwm channel 0 to begin cycling when set to one. to enable pwm0 onto the output pin, the pinctl registers must programmed accordingly. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 20: pulse-width modulator (pwm) controller 529 description: the pwm channel 0 active register specif ies the active time and inactive time for channel 0. example: empty example. 20.5.3. pwm channel 0 period register description the pwm channel 0 period register specifies the multi-chip attachment mode, clock divider value, active high/low values, and period. hw_pwm_period0 0x80064020 hw_pwm_period0_set 0x80064024 hw_pwm_period0_clr 0x80064028 hw_pwm_period0_tog 0x8006402c table 727. hw_pwm_active0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 inactive active table 728. hw_pwm_active0 bit field descriptions bits label rw reset definition 31:16 inactive rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. the internal count of the channel is compared for greater than this value to change to the inactive state. 15:0 active rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output to the active state. the internal count of the channel is compared for greater than this value to change to the active state. table 729. hw_pwm_period0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 matt cdiv inactive_state active_state period free datasheet http:/// STMP36XX official product documentation 5/3/06 530 chapter 20: pulse-width modulator (pwm) controller 5-36xx-d1-1.02-050306 description: the pwm channel 0 period register specifies the multi-chip attachment mode, clock divider value, active high/low values, and period. example: empty example. 20.5.4. pwm channel 1 active register description the pwm channel 1 active register specifie s the active time and inactive time for channel 1. hw_pwm_active1 0x80064030 hw_pwm_active1_set 0x80064034 hw_pwm_active1_clr 0x80064038 hw_pwm_active1_tog 0x8006403c table 730. hw_pwm_perio d0 bit field descriptions bits label rw reset definition 31:24 rsrvd2 ro 0x0 always write zeroes to this bit field. 23 matt rw 0x0 multichip attachment mode. this bit overrides the normal signal generation parameters and enables the 24-mhz crystal clock on the pwm0 output pin for inter- chip signaling. 22:20 cdiv rw 0x0 clock divider ratio to apply to the crystal clock frequency (24.0 mhz) that times the pwm output signal. div_1 = 0x0 divide by 1. div_2 = 0x1 divide by 2. div_4 = 0x2 divide by 4. div_8 = 0x3 divide by 8. div_16 = 0x4 divide by 16. div_64 = 0x5 divide by 64. div_256 = 0x6 divide by 256. div_1024 = 0x7 divide by 1024. 19:18 inactive_state rw 0x0 the logical inactive state that is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 inactive state sets pwm output to high-impendance. 0 = 0x2 inactive state sets pwm output to 0 (low). 1 = 0x3 inactive state sets pwm output to 1 (high). 17:16 active_state rw 0x0 the logical active state is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 active state sets pwm output to high-impendance. 0 = 0x2 active state sets pwm output to 0 (low). 1 = 0x3 active state sets pwm output to 1 (high). 15:0 period rw 0x0 number of divided xtal clock cycles in the entire period of the pwm waveform, minus one. for example, to obtain six clock cycles in the actual period, then set this field to five. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 20: pulse-width modulator (pwm) controller 531 description: the pwm channel 1 active register specif ies the active time and inactive time for channel 1. example: empty example. 20.5.5. pwm channel 1 period register description the pwm channel 1 period register specifies the multi-chip attachment mode, clock divider value, active high/low values, and period. hw_pwm_period1 0x80064040 hw_pwm_period1_set 0x80064044 hw_pwm_period1_clr 0x80064048 hw_pwm_period1_tog 0x8006404c table 731. hw_pwm_active1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 inactive active table 732. hw_pwm_active1 bit field descriptions bits label rw reset definition 31:16 inactive rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. the internal count of the channel is compared for greater than this value to change to the inactive state. 15:0 active rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output to the active state. the internal count of the channel is compared for greater than this value to change to the active state. table 733. hw_pwm_period1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 matt cdiv inactive_state active_state period free datasheet http:/// STMP36XX official product documentation 5/3/06 532 chapter 20: pulse-width modulator (pwm) controller 5-36xx-d1-1.02-050306 description: the pwm channel 1 period register specifies the multi-chip attachment mode, clock divider value, active high/low values, and period. example: empty example. 20.5.6. pwm channel 2 active register description the pwm channel 2 active register specifie s the active time and inactive time for channel 2. hw_pwm_active2 0x80064050 hw_pwm_active2_set 0x80064054 hw_pwm_active2_clr 0x80064058 hw_pwm_active2_tog 0x8006405c table 734. hw_pwm_perio d1 bit field descriptions bits label rw reset definition 31:24 rsrvd2 ro 0x0 always write zeroes to this bit field. 23 matt rw 0x0 multichip attachment mode. this bit overrides the normal signal generation parameters and enables the 24-mhz crystal clock on the pwm1 output pin for inter- chip signaling. 22:20 cdiv rw 0x0 clock divider ratio to apply to the crystal clock frequency (24.0 mhz) that times the pwm output signal. div_1 = 0x0 divide by 1. div_2 = 0x1 divide by 2. div_4 = 0x2 divide by 4. div_8 = 0x3 divide by 8. div_16 = 0x4 divide by 16. div_64 = 0x5 divide by 64. div_256 = 0x6 divide by 256. div_1024 = 0x7 divide by 1024. 19:18 inactive_state rw 0x0 the logical inactive state that is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 inactive state sets pwm output to high-impendance. 0 = 0x2 inactive state sets pwm output to 0 (low). 1 = 0x3 inactive state sets pwm output to 1 (high). 17:16 active_state rw 0x0 the logical active state is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 active state sets pwm output to high-impendance. 0 = 0x2 active state sets pwm output to 0 (low). 1 = 0x3 active state sets pwm output to 1 (high). 15:0 period rw 0x0 number of divided xtal clock cycles in the entire period of the pwm waveform, minus one. for example, to obtain six clock cycles in the actual period, then set this field to five. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 20: pulse-width modulator (pwm) controller 533 description: the pwm channel 2 active register specif ies the active time and inactive time for channel 2. example: empty example. 20.5.7. pwm channel 2 period register description the pwm channel 2 period register specifies the multi-chip attachment mode, clock divider value, active high/low values, and period. hw_pwm_period2 0x80064060 hw_pwm_period2_set 0x80064064 hw_pwm_period2_clr 0x80064068 hw_pwm_period2_tog 0x8006406c table 735. hw_pwm_active2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 inactive active table 736. hw_pwm_active2 bit field descriptions bits label rw reset definition 31:16 inactive rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. the internal count of the channel is compared for greater than this value to change to the inactive state. 15:0 active rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output to the active state. the internal count of the channel is compared for greater than this value to change to the active state. table 737. hw_pwm_period2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 matt cdiv inactive_state active_state period free datasheet http:/// STMP36XX official product documentation 5/3/06 534 chapter 20: pulse-width modulator (pwm) controller 5-36xx-d1-1.02-050306 description: the pwm channel 2 period register specifies the multi-chip attachment mode, clock divider value, active high/low values, and period. example: empty example. 20.5.8. pwm channel 3 active register description the pwm channel 3 active register specifie s the active time and inactive time for channel 3. hw_pwm_active3 0x80064070 hw_pwm_active3_set 0x80064074 hw_pwm_active3_clr 0x80064078 hw_pwm_active3_tog 0x8006407c table 738. hw_pwm_perio d2 bit field descriptions bits label rw reset definition 31:24 rsrvd2 ro 0x0 always write zeroes to this bit field. 23 matt rw 0x0 multichip attachment mode. this bit overrides the normal signal generation parameters and enables the 24-mhz crystal clock on the pwm2 output pin for inter- chip signaling. 22:20 cdiv rw 0x0 clock divider ratio to apply to the crystal clock frequency (24.0 mhz) that times the pwm output signal. div_1 = 0x0 divide by 1. div_2 = 0x1 divide by 2. div_4 = 0x2 divide by 4. div_8 = 0x3 divide by 8. div_16 = 0x4 divide by 16. div_64 = 0x5 divide by 64. div_256 = 0x6 divide by 256. div_1024 = 0x7 divide by 1024. 19:18 inactive_state rw 0x0 the logical inactive state that is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 inactive state sets pwm output to high-impendance. 0 = 0x2 inactive state sets pwm output to 0 (low). 1 = 0x3 inactive state sets pwm output to 1 (high). 17:16 active_state rw 0x0 the logical active state is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 active state sets pwm output to high-impendance. 0 = 0x2 active state sets pwm output to 0 (low). 1 = 0x3 active state sets pwm output to 1 (high). 15:0 period rw 0x0 number of divided xtal clock cycles in the entire period of the pwm waveform, minus one. for example, to obtain six clock cycles in the actual period, then set this field to five. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 20: pulse-width modulator (pwm) controller 535 description: the pwm channel 3 active register specif ies the active time and inactive time for channel 3. example: empty example. 20.5.9. pwm channel 3 period register description the pwm channel 3 period register specifies the multi-chip attachment mode, clock divider value, active high/low values, and period. hw_pwm_period3 0x80064080 hw_pwm_period3_set 0x80064084 hw_pwm_period3_clr 0x80064088 hw_pwm_period3_tog 0x8006408c table 739. hw_pwm_active3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 inactive active table 740. hw_pwm_active3 bit field descriptions bits label rw reset definition 31:16 inactive rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. the internal count of the channel is compared for greater than this value to change to the inactive state. 15:0 active rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output to the active state. the internal count of the channel is compared for greater than this value to change to the active state. table 741. hw_pwm_period3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 matt cdiv inactive_state active_state period free datasheet http:/// STMP36XX official product documentation 5/3/06 536 chapter 20: pulse-width modulator (pwm) controller 5-36xx-d1-1.02-050306 description: the pwm channel 3 period register specifies the multi-chip attachment mode, clock divider value, active high/low values, and period. example: empty example. 20.5.10. pwm channel 4 active register description the pwm channel 4 active register specifie s the active time and inactive time for channel 4. hw_pwm_active4 0x80064090 hw_pwm_active4_set 0x80064094 hw_pwm_active4_clr 0x80064098 hw_pwm_active4_tog 0x8006409c table 742. hw_pwm_perio d3 bit field descriptions bits label rw reset definition 31:24 rsrvd2 ro 0x0 always write zeroes to this bit field. 23 matt rw 0x0 multichip attachment mode. this bit overrides the normal signal generation parameters and enables the 24-mhz crystal clock on the pwm3 output pin for inter- chip signaling. 22:20 cdiv rw 0x0 clock divider ratio to apply to the crystal clock frequency (24.0 mhz) that times the pwm output signal. div_1 = 0x0 divide by 1. div_2 = 0x1 divide by 2. div_4 = 0x2 divide by 4. div_8 = 0x3 divide by 8. div_16 = 0x4 divide by 16. div_64 = 0x5 divide by 64. div_256 = 0x6 divide by 256. div_1024 = 0x7 divide by 1024. 19:18 inactive_state rw 0x0 the logical inactive state that is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 inactive state sets pwm output to high-impendance. 0 = 0x2 inactive state sets pwm output to 0 (low). 1 = 0x3 inactive state sets pwm output to 1 (high). 17:16 active_state rw 0x0 the logical active state is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 active state sets pwm output to high-impendance. 0 = 0x2 active state sets pwm output to 0 (low). 1 = 0x3 active state sets pwm output to 1 (high). 15:0 period rw 0x0 number of divided xtal clock cycles in the entire period of the pwm waveform, minus one. for example, to obtain six clock cycles in the actual period, then set this field to five. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 20: pulse-width modulator (pwm) controller 537 description: the pwm channel 4 active register specif ies the active time and inactive time for channel 4. example: empty example. 20.5.11. pwm channel 4 period register description the pwm channel 4 period register specifies the multi-chip attachment mode, clock divider value, active high/low values, and period. hw_pwm_period4 0x800640a0 hw_pwm_period4_set 0x800640a4 hw_pwm_period4_clr 0x800640a8 hw_pwm_period4_tog 0x800640ac table 743. hw_pwm_active4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 inactive active table 744. hw_pwm_active4 bit field descriptions bits label rw reset definition 31:16 inactive rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. the internal count of the channel is compared for greater than this value to change to the inactive state. 15:0 active rw 0x0 number of divided xtal clock cycles to count from the beginning of the period before changing the output to the active state. the internal count of the channel is compared for greater than this value to change to the active state. table 745. hw_pwm_period4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 matt cdiv inactive_state active_state period free datasheet http:/// STMP36XX official product documentation 5/3/06 538 chapter 20: pulse-width modulator (pwm) controller 5-36xx-d1-1.02-050306 description: the pwm channel 4 period register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. example: empty example. pwm xml revision: 1.24 table 746. hw_pwm_perio d4 bit field descriptions bits label rw reset definition 31:24 rsrvd2 ro 0x0 always write zeroes to this bit field. 23 matt rw 0x0 multichip attachment mode. this bit overrides the normal signal generation parameters and enables the 24-mhz crystal clock on the pwm4 output pin for inter- chip signaling. 22:20 cdiv rw 0x0 clock divider ratio to apply to the crystal clock frequency (24.0 mhz) that times the pwm output signal. div_1 = 0x0 divide by 1. div_2 = 0x1 divide by 2. div_4 = 0x2 divide by 4. div_8 = 0x3 divide by 8. div_16 = 0x4 divide by 16. div_64 = 0x5 divide by 64. div_256 = 0x6 divide by 256. div_1024 = 0x7 divide by 1024. 19:18 inactive_state rw 0x0 the logical inactive state that is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 inactive state sets pwm output to high-impendance. 0 = 0x2 inactive state sets pwm output to 0 (low). 1 = 0x3 inactive state sets pwm output to 1 (high). 17:16 active_state rw 0x0 the logical active state is mapped to the pwm output signal. note that the undefined state of 0x1 is mapped to high-z. hi_z = 0x0 active state sets pwm output to high-impendance. 0 = 0x2 active state sets pwm output to 0 (low). 1 = 0x3 active state sets pwm output to 1 (high). 15:0 period rw 0x0 number of divided xtal clock cycles in the entire period of the pwm waveform, minus one. for example, to obtain six clock cycles in the actual period, then set this field to five. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 539 21. i 2 c interface this chapter describes the i 2 c interface implemented on the STMP36XX. it includes sections on the external pins, interrupt sources, i 2 c bus protocol, and programming examples. programmable registers are included in section 21.7 . 21.1. overview the i 2 c is a standard two-wire serial interfac e used to connect the chip with periph- erals or host controllers. this interface provides a standard speed (up to 100 kbps), and a fast speed (up to 400 kbps) i 2 c connection to multiple devices with the chip acting in either i 2 c master or i 2 c slave mode. typical applications for the i 2 c bus include: eeprom, led/lcd, fm tuner, cell phone baseband chip connection, etc. the i 2 c port supports multi-master configurations. as implemented on the STMP36XX, the i 2 c block includes the following functions: ?the i 2 c block can be configured as either a master or slave device. in master mode, it generates the clock (i2c_scl) an d initiates transactions on the data line (i2c_sda). ?the i 2 c block packs/unpacks data into 8-, 16-, 24-, or 32-bit words for dma transactions. data on the i 2 c bus is always byte-oriented. short transmission (up to three bytes plus address) can be easily triggered using only pio operations, i.e., no dma setup required. ?the i 2 c block has programmable device addresses for master transactions. it also has a programmable 7-bit address that defaults to 0x43 = 7?b1000011 for slave transactions. as seen in the 8- bit device address byte, this address corresponds to 0x86 where the least significant bit (lsb) is the r/w bit. ? master transactions are composed of one or more dma commands chained together. the first byte conveys the slave address and read/write bit for the first command. if the entire transaction is an i 2 c write command, then it can be sent by a single dma command. if the command is an i 2 c read transaction, then at least two dma commands are required to handle it. ? when the slave interface is enabled, it immediately goes into address search mode and searches for a start event. it then looks for a match on its programmable device address. as soon as the address byte is matched, it is acknowledged on the i 2 c bus and then the scl clock is held low until released by software. the address phase initiates a cpu interrupt if a slave address match is detected. software then reads the address lsb to determine whether to use a read or write dma command to complete the slave transaction. figure 95 shows a block diagram of the i 2 c interface implemented on the STMP36XX. 21.2. i 2 c interface external pins i2c_sdaq: i 2 c serial data ?this pin carries all address and data bits. i2c_scl: i 2 c serial clock ?this pin carries the clock used to time the address and data. pullup resistors are required on both of the i 2 c lines as all of the i 2 c drivers are open drain (pulldown only). typically, external 2k ? resistors are used to pull the sig- nals up to vddio for normal and fast speeds. free datasheet http:/// STMP36XX official product documentation 5/3/06 540 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 21.3. i 2 c interrupt sources the i 2 c port can be used in either interrupt-driven or polled modes. an interrupt can be generated by the comp letion of a dma command in the apbx dma. dma inter- rupts are the reporting mechanism for i 2 c transactions that terminate normally. abnormal terminations or partial completions are signaled by interrupts generated within the i 2 c controller. if i 2 c interrupts are enab led, a level-sensitive interrupt will be signaled to the pro- cessor upon one of the events listed in ta b l e 7 4 7 . 24-mhz xtal osc. divide by n i 2 c i 2 c programmable registers and fifos arm core ahb slave ahb shared dma ahb master apbx master ahb-to-apbx bridge sram dma interface fsm i2c_scl i2c_sda input sync and i2c_ck generation slave search engine apbx figure 95. i 2 c interface block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 541 the interrupt lines are tied directly to the bits of control register 1. clearing these bits through software removes the interrupt request. table 747. i 2 c slave and master interrupt conditions source bit name description slave address hw_i2c_ctrl1_slave_ irq this interrupt is generated when an address match occurs. it indicates that the cpu should read the captured rw bit from the i 2 c address byte to determine the type of dma to use for the data transfer phase. slave stop hw_i2c_ctrl1_slave_ stop_irq this interrupt is generated when a stop condition is detected after a slave address has been matched. oversize xfer hw_i2c_ctrl1_oversize_ xfer_term_irq the dma and i 2 c controller are initialized for an expected transfer size. if the data phase is not terminated within this transfer size then over size transfer processing goes into effect and the cpu is alerted via this interrupt. early termination hw_i2c_ctrl1_early_ term_irq the dma and i 2 c controller are initialized for an expected transfer size. if the data phase is terminated before this transfer size then early termination processing goes into effect and the cpu is alerted via this interrupt. master loss hw_i2c_ctrl1_master_ loss_irq a master begins transmission on an idle i 2 c bus and monitors the data line. if it ever attempts to send a one on the line and notes that a zero has been sent instead, then it notes that it has lost mastership of the i 2 c bus. it terminates its transfer and reports the condition to the cpu via this interrupt. this detection only happens on master transmit operations. no slave ack hw_i2c_ctrl1_no_ slave_ack_irq when a start condition is transmitted in master mode, the next byte contains an address for a targeted slave. if the targeted slave does not acknowledge the address byte, then this interrupt is set, no further i 2 c protocol is processed, and the i 2 c bus returns to the idle state. data engine complete hw_i2c_ctrl1_data_ engine_cmplt_irq this bit is set whenever the dma interface state machine completes a transaction and resets its run bit. this is useful for pio mode transmit transactions that are not mediated by the dma and therefore cannot use the dma command completion interrupt. this bit is still set for master completions when the dma is used, but can be ignored in that case. bus free hw_i2c_ctrl_bus_ free_irq when bus mastership is lost during the i 2 c arbitration phase, the bus becomes busy running services for another master. this interrupt is set whenever a stop command is detected so the master transaction can attempt a retry. free datasheet http:/// STMP36XX official product documentation 5/3/06 542 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 21.4. i 2 c bus protocol the i 2 c interface operates as shown in figure 96 and figure 97 . ? a start condition is defined as a high-to-low transition on the data line while the i2c_scl line is held high. ? after this has been transmitted by t he master, the bus is considered busy. ? the next byte of data transmitted after the start condition contains the address of the slave in the first seven bits, and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. ? when an address is sent, each device in the system compares the first seven bits after a start condition with its address. ? if they match, the device considers itself addressed by the master. in slave mode, the default i 2 c write address is 86h, and its default read address is 87h. the slave address is programmable. data transfer with acknowledge is obligatory. ? the transmitter must release the i2c_ sda line during the acknowledge pulse. ? the receiver must then pull the data line lo w, so that it remain s stable low during the high period of the acknowledge clock pulse. ? a receiver that has been addressed is obliged to generate an acknowledge after each byte of data has been received. ? a slave device can terminate a transfer by withholding its acknowledgement. the clock is generated by the master, according to parameters set in the hw_i2c_timing register. this register al so provides programmable timing for cap- turing received data, as well as for changing the transmitted data bit. 8 bits 8 bits slave address and r/w data acknowledge signal acknowledge signal start condition stop condition scl sda end of the slave address search engine processing beginning of dma transfer engine processing i 2 c clock held figure 96. i 2 c data and clock timing free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 543 21.4.1. simple device transactions the simplest transfer of interest on an i 2 c bus is writing a single data byte from a master to a slave, for example, writing a single byte to an fm tuner. in this transac- tion, a start condition is transmitted, followed by the device address byte, followed by a single byte of write data. this sequ ence always ends with a stop condition. table 749 defines the symbols used in describing i 2 c transactions. for example, in the single byte write operation, st is a start condition, and sp is a stop condition. the data transfer occurs between these two bus events. it starts with a slave address plus write byte (sad+w) addressin g the targeted slave. a slave-generated acknowledge bit (sak) tells the master that a slave has recognized th e address and will accept the transfer. the master se nds the data byte (data), and the slave acknowledges it with an sak. table 748. i 2 c transfer when the interface is transmitting as a master st sad+w sak data sak sp table 749. i 2 c slave and master mode address definitions bit description st start condition sr repeated start condition sad slave address sak slave acknowledge sub sub-address, e.g., for eeproms data data sp stop condition mak master acknowledge nmak no master acknowledge sclin sdain hold clock sak t dhd bit 0 t dsu bit 1 bit 2 grab read data change write data scloe slave low clk high clk master figure 97. i 2 c data and clock timing generation free datasheet http:/// STMP36XX official product documentation 5/3/06 544 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 to receive one data byte from a slave device such as an fm tuner, the following bus transaction takes place. in this transaction: ? the master first generates a start condition, st. ? it then sends the seven-bit slave address for the fm tuner plus a read bit (sad+r). ? the slave in the fm tuner responds with a slave acknowledge bit (sak). ? the master then generates i 2 c clocks for a data byte to be transferred (data). ? the slave provides data to the i 2 c data bus during the data byte transfer. ? next, the master generates a master ackn owledge to the slave (mak), indicating its acceptance of the data byte. ? finally, the master generates a stop condition (sp), terminating the transaction and freeing the i 2 c bus for other masters to use. the following example shows a multiple byte read from an fm tuner or other slave device: 21.4.2. typical eeprom transactions i 2 c eeproms typically have a specific transaction sequence for reading and writ- ing data bytes to and from the eeprom array. table 752 through table 755 show the first two bytes of data as a sub-address fo r purposes of illu stration. the sub- address is used to address the memory space inside the device. table 749 defines each element of the transactions shown. when writing a single byte of data to the eeprom, one must first transfer two bytes of sub-address as follows: the sub-address only needs to be specified once for a multibyte transfer, as shown here. note that the sub-address must be sent for each start condition that initiates a transaction. one must also provide th e sub-address befo re reading bytes from the eeprom. the sub-address is transmitted from the ma ster to the slave before it can receive data bytes. the two transfers are joined into a single bus transaction though the use of a repeated start condition (sr). normally, a stop condition precedes a start condi- tion. however, when a start condition is pr eceded by another start condition, it is known as a repeated start (sr). note that the two-byte sub address is transferred using an sad+w address, while the data is received using a sad+r address. table 750. i 2 c transfer ?fm tuner? read of one byte st sad+r sak data mak sp table 751. i 2 c transfer ?fm tuner? read of three bytes st sad+r sak data mak data mak data nmak sp table 752. i 2 c transfer when master is writing one byte of data to a slave st sad+w sak sub sak sub sak data sak sp table 753. i 2 c transfer when master is writing multiple bytes to a slave st sad+w sak sub sak sub sak data sak data sak sp free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 545 21.4.3. master mode protocol in master mode, the i 2 c interface generates the clock and initiates all transfers. 21.4.3.1. clock generation the i 2 c clock is generated fr om the apbx clock, as described in the register description. ? if another device pulls the clock low before the i 2 c block has counted the high period, then the i 2 c block immediately pulls the clock low as well and starts counting its low period. ? once the low period has been counted, the i 2 c block releases the clock line high, but must then check to see if another device stills ho lds the line low, in which case it enters a high wait state. in this way, the i2c_scl clock is generated, with its low period determined by the device with the longest clock low period and its high period determined by the one with the shortest clock high period. 21.4.3.2. master mode operation the finite state machine for master mode operation is shown in figure 98 through figure 101 . figure 98 shows the generation of the optional start condition. figure 99 shows the receive states, figure 100 shows the transmit states. figure 101 shows the generation of the optional stop state. table 756 through ta b l e 7 5 9 show examples of master mode i 2 c transactions. table 749 defines each sub-address shown. the following read-after-write transac- tions are performed using the restart technique. table 754. i 2 c transfer when master is receiv ing one byte of data from a slave st sad+w sak sub sak sub sak sr sad+r sak data nmak sp table 755. i 2 c transfer when master is receiving multiple bytes of data from a slave st sad+w sak sub sak sub sak sr sad+r sak data mak data mak data nmak sp table 756. i 2 c transfer when the interface as master is transmitting one byte of data st sad+w sak sub sak sub sak data sak sp table 757. i 2 c transfer when the interface as master is receiving >1 byte of data from slave st sad+r sak data mak data mak data nmak sp table 758. i 2 c transfer when master is receiving 1 byte of data from slave internal subaddress st sad+w sak sub sak sub sak sr sad+r sak data nmak sp table 759. i 2 c transfer when master is receiving >1 byte of data from slave internal subaddress st sad+w sak sub sak sub sak sr sad+r sak data mak data mak data nmak sp free datasheet http:/// STMP36XX official product documentation 5/3/06 546 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 bus idle i2c_sda_en=1 start condition w ait for start hold time receive states multi master & start cond. ? no yes run? no yes bus busy stop cond. ? no yes presend start? no yes multi master? no yes receive mode? transmit states no master loss yes wait for run release held clock release held clock figure 98. i 2 c master mode flow chart?initial states free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 547 receive 1 bit got 8 bits? send ack, flush dma reset run no yes check xfer_count and decide on ack rcv states last byte? no no yes hold clock? send data to dma send ack yes send stop set hold i 2 c clock low post send stop? wait for run no yes figure 99. i 2 c master mode flow chart?receive states free datasheet http:/// STMP36XX official product documentation 5/3/06 548 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 send 1 bit 8 bits sent? reset run no yes check xfer_count xmit states last byte? no no yes hold clock? check ack yes send stop set hold i 2 c clock low post send stop? wait for run no yes get byte from dma ack ? figure 100. i 2 c master mode flow chart?transmit states free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 549 21.4.4. slave mode protocol the i 2 c slave protocol is handled by a combination of i 2 c functional block hard- ware, the dma, and some supporting software to intervene in the transaction. the flow chart for slave mode is shown in figure 102 . ? at device start-up, all the registers are rese t so that the state is known from that time onward. ? once the i 2 c slave search engine is enabled, the slave waits to detect a start condition on the i2c_scl and i2c_sda lines. ? once this is detected, the slave read s in eight bits and checks against its programmed device address (which defaults to 0x86 == 7?b1000011) to see if a master device is trying to start a transfer with STMP36XX operating as a slave. ? if it is the programmed address, an acknowledge is sent; otherwise the slave does not acknowledge and returns to state idle. ? once the slave search engine detects an address, it holds the clock line and interrupts the cpu. ? next the software checks the rw bit. ? if it is a write operation, then the software programs the dma channel for a dma_write (to on-chip ram or off-chip sdram). ? the slave search engine leaves the programmable state set up for the dma transfer engine to send the address acknowledge for the address byte as soon as the clock is released. i2c_sda_en = 0 reset run, reset post send send stop wait for run release held clock wait for stop setup time i2c_sda_en = 1 force sda to zero release sda figure 101. i 2 c master mode flow chart?send stop states free datasheet http:/// STMP36XX official product documentation 5/3/06 550 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 ? it then accepts eight-bit bytes and pushes them into the dma data register, acknowledging each data byte as it is received, until the transfer count reaches zero. ? the dma engine stops with the clock held and the hardware ready to acknowledge the last byte when the clock is released. software decides whether the last byte is acknowledged or not. ? if the master is requesting a read operation, then the STMP36XX slave must start sending data on the i2c_sda bus immediately after acknowledging the slave address and rw bit. ? after each byte, the acknowledge from the master must be checked. when the master has received the last byte, it does not send an acknowledge, and the slave terminates while setting the earl y termination interrupt request. this notifies software that the dma will not be interrupting fo r the termination and that software should deal with a shorter than expected packet of data. ? if the transfer count reaches zero and the master has not sent an mnak or stop condition, then the slave dma transfer controller terminates the transfer while setting the oversize transfer interrupt reque st. this notifies soft ware to set up for an additional buffer of data to transmit to the master. data is transmitted in byte format. each da ta transfer has to contain eight bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiv er cannot receive another complete byte of data until it has performed some other function, it can hold the i2c_scl clock line low to force the transmitter into a wait state. data transfer can only continue when the receiver is ready for another byte and releases the clock line. if a slave receiver does not acknowledge the slave address (e.g., it is unable to receive because it is performing some real -time function), the data line must be left high by the slave. the master can then abort the transfer. a low-to-high transition on the i2c_sd a line while the i2c_scl line is high is defined as a stop condition. each data transfer must be terminated by the genera- tion of a stop condition. a write transfer from a master can be terminated by the master by sending a stop condition instead of an additional data byte. the STMP36XX slave dma transfer engine reports this to software as an early termina- tion interrupt request. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 551 wait for start condition and slave enable receive slave address stop | restart no yes receive 8 data bits send data to dma stop | restart no yes our address no yes hold i 2 c clock low cpu release no yes last byte no yes holdclock? no yes read yes no a get 1 byte from dma stop | restart no yes last byte no yes holdclock? no yes a receive master ack m ack? no yes reset send slave ack and interrupt cpu send 8 data bits send slave ack slave search engine figure 102. i 2 c slave mode flow chart free datasheet http:/// STMP36XX official product documentation 5/3/06 552 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 21.5. programming examples 21.5.1. five byte master write using dma the example in figure 103 shows sending five bytes from an STMP36XX operating as an i 2 c master to another device acting as an i 2 c slave. the dma command is initialized to send six bytes to the i 2 c controller and one word of pio information to the hw_i2c_ctrl0 register. the following c code is used to send a five-byte transmission: // send: start, 0x56, 0x01,0x02,0x03,0x04,0x05,stop //------------------------------------------------------ #define i2c_channel_num 3 // dma buffer of 6 bytes (i2c address + 5 data bytes) static reg32_t i2c_data_buffer[2]= { 0x03020156, //slave address 56+w 0x00000504 // last two data bytes }; // dma command chain const static reg32_t i2c_dma_cmd[4] = { (reg32_t) i2c_dma_cmd2, (bf_apbx_chn_cmd_xfer_count(6) | bf_apbx_chn_cmd_cmdwords(1) | bf_apbx_chn_cmd_wait4endcmd(1)| bf_apbx_chn_cmd_chain(0) | bv_fld(apbx_chn_cmd, command, dma_read)), (reg32_t) &eeprom_command_buffer[0], bf_i2c_ctrl0_post_send_stop(bv_i2c_ctrl0_post_send_stop__send_stop)| bf_i2c_ctrl0_pre_send_start(bv_i2c_ctrl0_pre_send_start__send_start) | bf_i2c_ctrl0_master_mode(bv_i2c_ctrl0_master_mode__master) | bf_i2c_ctrl0_direction(bv_i2c_ctrl0_direction__transmit) | table 760. i 2 c transfer when the master transmits 5 bytes of data to the slave st sad+w sak data sak data mak d a d a d a d a data nmak sp nextcmd_addr 6 buffer address hw_i2c_ctrl0= 0x001b0006 data2,data1, data0, i2caddr+w 0 0 1 10 1 1pio, no chaining, irq,dma read pointer to next ccw pointer to dma buffer 0 0x0000,data4, data3 figure 103. i 2 c writing five bytes free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 553 bf_i2c_ctrl0_xfer_count(6) }; void sendfivebytes(){ // reset the apbx dma channels associated with i2c. reset_mask = bf_apbx_ctrl0_reset_channel((1 << i2c_channel_num)); hw_apbx_ctrl0_set(reset_mask); // poll for reset to clear the channel. for (retries = 0; retries < reset_timeout; retries++) if ((reset_mask & hw_apbx_ctrl0_rd()) == 0) break; if( retries == reset_timeout) exit(1); // setup dma channel configuration. bf_wrn(apbx_chn_nxtcmdar,i2c_channel_num, cmd_addr,(reg32_t) i2c_dma_cmd); bf_wr(apbx_ctrl1, ch3_cmdcmplt_irq, 0); // clear interrupt // start the dma channel by incrementing semaphore. bf_wrn(apbx_chn_sema, i2c_channel_num, increment_sema, 1); // poll for the semaphore to decrement to zero on the dma channel. for (retries = 0; retries < semaphore_timeout; retries++) if (0 == bf_rdn(apbx_chn_sema, i2c_channel_num, phore)) break; // a frame with one byte of address and five bytes of data was just sent } 21.5.2. reading 256 bytes from an eeprom nextcmd_addr 3 buffer address hw_i2c_ctrl0= 0x000b0003 nextcmd_addr=0 256 buffer address 256-byte data block 0x00,sub1, sub0, i2caddr+w 1 0 1 10 0 1pio, chaining, dma read 1 pio,irq, no chaining, dma write 0 0 1 01 1 pointer to next ccw pointer to dma buffer 0 0 hw_i2c_ctrl0= 0x00130100 nextcmd_addr 1 buffer address hw_i2c_ctrl0= 0x002b0001 0x000000, i2caddr+r 1 0 1 10 0 1pio, chaining, dma read 0 figure 104. i 2 c reading 256 bytes from an eeprom free datasheet http:/// STMP36XX official product documentation 5/3/06 554 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 //---------------------------------------------------------------------- // dma buffers to hold i2c command string for slave addres+w plus sub0, // sub 1 and the second command, a slave address+r // eeprom write address == 0xa0, read address == 0xa1 //---------------------------------------------------------------------- unsigned char eeprom_command_buffer[4] = {0xa0,0x34,0x12,0xa1}; //---------------------------------------------------------------------- // i2c dma chain //---------------------------------------------------------------------- const static reg32_t i2c_dma_cmd3[4] = { 0x0, (bf_apbx_chn_cmd_xfer_count(256) | bf_apbx_chn_cmd_semaphore(1) | bf_apbx_chn_cmd_cmdwords(1) | bf_apbx_chn_cmd_chain(0) | // last command bv_fld(apbx_chn_cmd, command, dma_read)), (reg32_t) &eeprom_command_buffer[3], bf_i2c_ctrl0_post_send_stop(bv_i2c_ctrl0_post_send_stop__send_stop)| bf_i2c_ctrl0_master_mode(bv_i2c_ctrl0_master_mode__master) | bf_i2c_ctrl0_direction(bv_i2c_ctrl0_direction__receive) | bf_i2c_ctrl0_xfer_count(256) }; const static reg32_t i2c_dma_cmd2[4] = { (reg32_t) i2c_dma_cmd3, (bf_apbx_chn_cmd_xfer_count(1) | bf_apbx_chn_cmd_semaphore(1) | bf_apbx_chn_cmd_cmdwords(1) | bf_apbx_chn_cmd_wait4endcmd(1)| bf_apbx_chn_cmd_chain(1) | bv_fld(apbx_chn_cmd, command, dma_read)), (reg32_t) &eeprom_command_buffer[3], bf_i2c_ctrl0_retain_clock(bv_i2c_ctrl0_retain_clock__hold_low)| bf_i2c_ctrl0_pre_send_start(bv_i2c_ctrl0_pre_send_start__send_start)| bf_i2c_ctrl0_master_mode(bv_i2c_ctrl0_master_mode__master) | bf_i2c_ctrl0_direction(bv_i2c_ctrl0_direction__transmit) | bf_i2c_ctrl0_xfer_count(1) }; const static reg32_t i2c_dma_cmd1[4] = { (reg32_t) i2c_dma_cmd2, (bf_apbx_chn_cmd_xfer_count(3) | bf_apbx_chn_cmd_cmdwords(1) | bf_apbx_chn_cmd_wait4endcmd(1)| bf_apbx_chn_cmd_chain(1) | bv_fld(apbx_chn_cmd, command, dma_read)), (reg32_t) &eeprom_command_buffer[0], bf_i2c_ctrl0_pre_send_start(bv_i2c_ctrl0_pre_send_start__send_start) | bf_i2c_ctrl0_master_mode(bv_i2c_ctrl0_master_mode__master) | bf_i2c_ctrl0_direction(bv_i2c_ctrl0_direction__transmit) | bf_i2c_ctrl0_xfer_count(3) }; ///////////////////////////////////////////////////// //read256bytesfromeeprom returns 1 for errors and 0 for ok ///////////////////////////////////////////////////// int read256bytesfromeeprom(unsigned short usaddress){ // insert eeprom addres param into dma command buffer i2c_cmd_buffer[1] = (unsigned char) (usaddress &0x00ff); i2c_cmd_buffer[2] = (unsigned char) ((usaddress>>8) &0x00ff); // reset the apbx dma channels associated with i2c. reset_mask = bf_apbx_ctrl0_reset_channel((1 << i2c_channel_num)); hw_apbx_ctrl0_set(reset_mask); // poll for reset to clear the channel. for (retries = 0; retries < reset_timeout; retries++) if ((reset_mask & hw_apbx_ctrl0_rd()) == 0) break; if (retries == reset_timeout)exit(1); // setup dma channel configuration. bf_wrn(apbx_chn_nxtcmdar,i2c_channel_num, cmd_addr,(reg32_t) i2c_dma_cmd_subaddr); free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 555 bf_wr(apbx_ctrl1, ch3_cmdcmplt_irq, 0); // start the dma channel by incrementing semaphore. bf_wrn(apbx_chn_sema, i2c_channel_num, increment_sema, 1); // poll for the semaphore to decrement to zero on the dma channel. for (retries = 0; retries < semaphore_timeout; retries++)} if (0 == bf_rdn(apbx_chn_sema, i2c_channel_num, phore)) break; if (1 == hw_i2c_ctrl1.master_loss_irq) return 1; // error if (1 == hw_i2c_ctrl1.oversize_xfer_term_irq) return 1; // error if (1 == hw_i2c_ctrl1.no_slave_ack_irq) return 1; // error if (1 == hw_i2c_ctrl1.early_term_irq) return 1; // error } ferreters == semaphore_timeout) exit(2); // the 256 bytes were read from the eeprom so return with no error return 0; } 21.6. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 21.7. programmable registers the following registers describe the prog ramming interface for the slave and master i 2 c controller. 21.7.1. i2c control register 0 description the i2c control register specifies the reset state and the command and transfer size information fo r the i2c controller. hw_i2c_ctrl0 0x80058000 hw_i2c_ctrl0_set 0x80058004 hw_i2c_ctrl0_clr 0x80058008 hw_i2c_ctrl0_tog 0x8005800c table 761. hw_i2c_ctrl0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate run rsvd1 pre_ack acknowledge send_nak_on_last pio_mode multi_master clock_held retain_clock post_send_stop pre_send_start slave_address_enable master_mode direction xfer_count free datasheet http:/// STMP36XX official product documentation 5/3/06 556 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 table 762. hw_i2c_ctrl0 bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 set to zero for normal operation. when this bit is set to one (default), then the entire block is held in its reset state. run = 0x0 allow i2c to operate normally. reset = 0x1 hold i2c in reset. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. run = 0x0 allow i2c to operate normally. no_clks = 0x1 do not clock i2c gates in order to minimize power consumption. 29 run rw 0x0 set this bit to one to enable the i2c controller operation. this bit is automatically set by dma commands that write to ctrl1 after the last pio write of the dma command. for soft dma operation, software can set this bit to enable the controller. halt = 0x0 no i2c command in progress. run = 0x1 process a slave or master i2c command. 28 rsvd1 ro 0x0 always set this bit field to zero. 27 pre_ack rw 0x0 reserved for sigmatel use. 26 acknowledge rw 0x0 set this bit to one to cause a pending acknowledge bit (prior to dma transfer) to be acknowledged. set it to zero to nak the pending acknowledge bit. this bit is set to one by the slave search engine if the criteria is met for acknowledging a slave address. software can reset the bit to slave-not-acknowledge the address. this bit defines the state of the i2c_data line during the address acknowledge bit time. the slave search engine holds the clock at this point for a software decision. this bit has no effect when the presend start option is selected. snak = 0x0 slave not acknowledg e when the held clock is released. ack = 0x1 slave acknowledge when the held clock is released. 25 send_nak_on_last rw 0x0 set this bit to one to cause the dma transfer engine to send a nak on the last byte. ack_it = 0x0 send an ack on the last byte received. nak_it = 0x1 send a nak on the last byte received. 24 pio_mode rw 0x0 set this bit to one to enable pio mode of operation for the i2c master. one can preload up to four bytes into hw_i2c_data register before setting the run bit. the state machine will not attempt to use the dma for master transmit operation. the normal start and stop conditions can be sent and the clock can be held at the end of the transfer, if desired. note: all receive operations must use the dma mode, not the pio mode. 23 multi_master rw 0x0 set this bit to one to enable the master state machine to monitor the start conditions generated by other masters. the bus is assumed to be busy from the first start condition generated by another master until a stop condition is generated. single = 0x0 assume we are the only master. multiple = 0x1 enable multiple master bus busy monitoring from start detects. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 557 description: this register is either written by the dma or the cpu depending on the state of an i2c transaction. 22 clock_held rw 0x0 this bit is set to one by the i2c controller state machines. it holds the i2c clock line low until cleared. it must be cleared by firmware, either by cpu instructions or dma pio transactions. it is set high when a slave address is matched by the slave controller. it is also set high at the end of a master or slave transaction that had the retain_clock bit set high. software should not set this bit to one. release = 0x0 release the clock line. held_low = 0x1 the clock line is currently being held low. 21 retain_clock rw 0x0 set this bit to one to retain the clock at the end of this transaction. this has the effect of holding the clock low until the start of the next transaction. release = 0x0 release the clock line after this data transfer. hold_low = 0x1 hold the clock line low after this data transfer. 20 post_send_stop rw 0x0 set this bit to one to send a stop condition after transferring the data associated with this transaction. this bit is automatically cleared by the hardware after the operation has been performed. no_stop = 0x0 do not send a stop condition before this transaction. send_stop = 0x1 send a stop condition before this transaction. 19 pre_send_start rw 0x0 set this bit to one to send a start condition before transferring the data associated with this transaction. this bit is automatically cleared by the hardware after the operation has been performed. no_start = 0x0 do not send a start condition before this transaction. send_start = 0x1 send a start condition before this transaction. 18 slave_address_enable rw 0x0 set this bit to one to enable the slave address decoder. when an address match occurs, the i2c bus clock is frozen, by setting hw_i2c_ctrl0_clock_held, and an interrupt is generated. disabled = 0x0 disable the slave address decoder. enabled = 0x1 enable the slave address decoder. 17 master_mode rw 0x0 set this bit to one to select master mode. set it zero to select slave mode. slave = 0x0 operate in slave mode. master = 0x1 operate in master mode. 16 direction rw 0x0 set this bit to one to select an i2c transmit operation in either slave or master mode. xmit = write in master mode, read in slave mode. set this bit to zero to select an i2c receive operation in either slave or master mode. receive = 0x0 i2c receive operation for slave or master. transmit = 0x1 i2c transmit operation for slave or master. 15:0 xfer_count rw 0x0000 number of bytes to tran sfer. this field decrements as bytes are transferred. table 762. hw_i2c_ctrl0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 558 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 example: // turn off soft reset and clock gating hw_i2c_ctrl0_clr(bm_i2c_ctrl0_sftrst | bm_i2c_ctrl0_clkgate); 21.7.2. i2c timing register 0 description the timing for various phases of i2c co ntroller commands are further defined by fields in the i2c timing register 0. hw_i2c_timing0 0x80058010 hw_i2c_timing0_set 0x80058014 hw_i2c_timing0_clr 0x80058018 hw_i2c_timing0_tog 0x8005801c description: this register is primarily used for clock and timing generation. example: hw_i2c_timing0_wr(0x00780030); // high time = 120 clocks, read bit at 48 for 95 khz at 24 mhz hw_i2c_timing0_wr(0x000f0007); // high time = 15 clocks, read bit at 7 for 400 khz at 24 mhz 21.7.3. i2c timing register 1 description the timing for various phases of i2c co ntroller commands are further defined by fields in the i2c timing register 1. hw_i2c_timing1 0x80058020 hw_i2c_timing1_set 0x80058024 hw_i2c_timing1_clr 0x80058028 hw_i2c_timing1_tog 0x8005802c table 763. hw_i2c_timing0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 high_count rsvd1 rcv_count table 764. hw_i2c_timing0 bit field descriptions bits label rw reset definition 31:26 rsvd2 ro 0x0 always set this bit field to zero. 25:16 high_count rw 0x78 load this bit field with the apbx clock count for the high period of the i2c clock. 15:10 rsvd1 ro 0x0 always set this bit field to zero. 9:0 rcv_count rw 0x30 load this bit field with the apbx clock count for capturing read data after the i2c clock goes high. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 559 description: this register is primarily used for clock and timing generation. example: hw_i2c_timing1_wr(0x00800030); // low time at 128, write bit at 48 for 95 khz at 24 mhz hw_i2c_timing1_wr(0x001f000f); // low time at 31, write bit at 15 for 400 khz at 24 mhz 21.7.4. i2c timing register 2 description the timing for various phases of i2c co ntroller commands are further defined by fields in the i2c timing register 2. hw_i2c_timing2 0x80058030 hw_i2c_timing2_set 0x80058034 hw_i2c_timing2_clr 0x80058038 hw_i2c_timing2_tog 0x8005803c table 765. hw_i2c_timing1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 low_count rsvd1 xmit_count table 766. hw_i2c_timing1 bit field descriptions bits label rw reset definition 31:26 rsvd2 ro 0x0 always set this bit field to zero. 25:16 low_count rw 0x80 load this bit field with the apbx clock count for the low period of the i2c clock. 15:10 rsvd1 ro 0x0 always set this bit field to zero. 9:0 xmit_count rw 0x30 load this bit field with the apbx clock count for changing transmitted data after the i2c clock goes low. set this value to produce valid i2c setup and hold times at the desired bit rate for the current apbx clock rate. table 767. hw_i2c_timing2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 bus_free rsvd1 leadin_count free datasheet http:/// STMP36XX official product documentation 5/3/06 560 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 description: this register is primarily used for clock and timing generation. example: hw_i2c_timing2_wr(0x0015000d); // bus free count of 21 lead in count of 13 21.7.5. i2c control register 1 description the i2c controller command is further defined by fields in this control extension reg- ister. the i2c control register 1 is where the i2c slave address is specified. fast or normal mode is selected here. hw_i2c_ctrl1 0x80058040 hw_i2c_ctrl1_set 0x80058044 hw_i2c_ctrl1_clr 0x80058048 hw_i2c_ctrl1_tog 0x8005804c table 768. hw_i2c_timing2 bit field descriptions bits label rw reset definition 31:26 rsvd2 ro 0x0 always set this bit field to zero. 25:16 bus_free rw 0x30 load this bit field with the apbx clock count for delaying the transition to the bus idle state after entering stop state in the clock generator. 15:10 rsvd1 ro 0x0 always set this bit field to zero. 9:0 leadin_count rw 0x30 load this bit field with the apbx clock count for delaying the rising edge of i2c_sck after the kick. table 769. hw_i2c_ctrl1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 bcast_slave_en slave_address_byte bus_free_irq_en data_engine_cmplt_irq_en no_slave_ack_irq_en oversize_xfer_term_irq_en early_term_irq_en master_loss_irq_en slave_stop_irq_en slave_irq_en bus_free_irq data_engine_cmplt_irq no_slave_ack_irq oversize_xfer_term_irq early_term_irq master_loss_irq slave_stop_irq slave_irq free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 561 table 770. hw_i2c_ctrl1 bit field descriptions bits label rw reset definition 31:25 rsvd1 ro 0x0 always set this bit field to zero. 24 bcast_slave_en rw 0x0 set this bit to one to enable the slave address search machine to look for both a match to the programmed slave address, as well as a match to the broadcast address of all zeroes. no_bcast = 0x0 do not watch for broadcast address while matching programmed slave address. watch_bcast = 0x1 watch for the all zeroes broadcast address while matching programmed slave address. 23:16 slave_address_byte rw 0x86 slave address byte. note that the slave address is only seven bits long. the slave address search state machine will respond to either a read or a write command issued to the seven-bit address. set the lsb (bit 0) to one to match all 7 bit i2c addresses. 15 bus_free_irq_en rw 0x0 set this bit to one to enable bus free interrupt requests to be routed to the interrupt collector. set to zero to disable interrupts from the i2c controller. disabled = 0x0 no interrupt request pending. enabled = 0x1 interrupt request pending. 14 data_engine_cmplt_irq_ en rw 0x0 set this bit to one to enable data engine complete interrupt requests to be routed to the interrupt collector. set to zero to disable interrupts from the i2c controller. disabled = 0x0 no interrupt request pending. enabled = 0x1 interrupt request pending. 13 no_slave_ack_irq_en rw 0x0 set this bit to one to enable interrupt requests to be routed to the interrupt collector. set to zero to disable interrupts from the i2c controller. disabled = 0x0 no interrupt request pending. enabled = 0x1 interrupt request pending. 12 oversize_xfer_term_irq _en rw 0x0 set this bit to one to enable interrupt requests to be routed to the interrupt collector. set to zero to disable interrupts from the i2c controller. disabled = 0x0 no interrupt request pending. enabled = 0x1 interrupt request pending. 11 early_term_irq_en rw 0x0 set this bit to one to enable interrupt requests to be routed to the interrupt collector. set to zero to disable interrupts from the i2c controller. disabled = 0x0 no interrupt request pending. enabled = 0x1 interrupt request pending. 10 master_loss_irq_en rw 0x0 set this bit to one to enable interrupt requests to be routed to the interrupt collector. set to zero to disable interrupts from the i2c controller. disabled = 0x0 no interrupt request pending. enabled = 0x1 interrupt request pending. 9 slave_stop_irq_en rw 0x0 set this bit to one to enable interrupt requests to be routed to the interrupt collector. set to zero to disable interrupts from the i2c controller. disabled = 0x0 no interrupt request pending. enabled = 0x1 interrupt request pending. free datasheet http:/// STMP36XX official product documentation 5/3/06 562 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 8 slave_irq_en rw 0x0 set this bit to one to enable interrupt requests to be routed to the interrupt collector. set to zero to disable interrupts from the i2c controller. the corresponding hw_irq_stat_slave_irq interrupt bit is set by the slave search engine to indicate that it has stopped searching due to an address match or error. disabled = 0x0 no interrupt request pending. enabled = 0x1 interrupt request pending. 7 bus_free_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller because the bus has become free. this bit is cleared by software by writing a one to its sct clear address. this interrupt indicates that the i2c bus, which was busy, has just become free. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 6 data_engine_cmplt_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller because the data engine transfer has completed. this bit is cleared by software by writing a one to its sct clear address. this interrupt indicates that the data engine has completed a dma transfer in either master or slave mode. this notification is useful for pio mode master write (transmit) or slave read (transmit) operations, i.e., data engine transmit operations. pio receive operations are not supported. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 5 no_slave_ack_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller because the slave addressed by a master transfer did not respond with an acknowledge to its slave address. this bit is cleared by software by writing a one to its sct clear address. note: in master mode, the data engi ne checks the acknowledge of the first byte transmitted after a start condition is sent. if the slave does not acknowledge this specific byte, then this interrupt status bit is set. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 4 oversize_xfer_term_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. this bit is cleared by software by writing a one to its sct clear address. this interrupt indicates that a master dma transfer did not complete by the end of the transfer size. this is indicated by the slave acknowledging the last byte of a write transfer instead of naking it. the master should then send additional bytes of data if desired. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. table 770. hw_i2c_ctrl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 563 description: this control register is primarily used for interrupt management. it also controls the special slave address matching mode. in a ddition, it controls the protocol speed, i.e., fast or 400-khz versus normal or 100-khz operation. example: hw_i2c_ctrl1_clr(bm_i2c_ctrl1_slave_irq); // clear the slave interrupt 21.7.6. i2c status register description the i2c controller reports status information in the i2c status register. hw_i2c_stat 0x80058050 3 early_term_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. this bit is cleared by software by writing a one to its sct clear address. this interrupt indicates that a master write transfrom from the STMP36XX to a slave device was naked by the slave before the transfer was completed. in slave mode, it indicates that the master naked a byte transmitted by the slave causing early termination of the expected transfer. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 2 master_loss_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. this bit is cleared by software by writing a one to its sct clear address. this interrupt indicates that a master read or write transaction lost an arbitration with another master. master loss is indicated by the master attempting to transmit a one to the bus at the same time as another master writes a zero. the wired and bus produces a zero on the bus which is detected by the lossing master. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 1 slave_stop_irq rw 0x0 this bit is set to indicate that an i2c stop condition was received by the slave address search engine after it had found a start command addressed to its slave address. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 0 slave_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. this bit is cleared by software by writing a one to its sct clear address. this bit is set by the slave search engine to indicate that it has stopped searching due to an address match or error. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. table 770. hw_i2c_ctrl1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 564 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 table 771. hw_i2c_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 master_present slave_present any_enabled_irq rsvd1 rcvd_slave_addr slave_addr_eq_zero slave_found slave_searching data_engine_dma_wait bus_busy clk_gen_busy data_engine_busy slave_busy bus_free_irq_summary data_engine_cmplt_irq_summary no_slave_ack_irq_summary oversize_xfer_term_irq_summary early_term_irq_summary master_loss_irq_summary slave_stop_irq_summary slave_irq_summary table 772. hw_i2c_stat bit field descriptions bits label rw reset definition 31 master_present ro 0x1 this read-only bit indicates that the i2c master function is present when it reads back a one. this i2c function is not available on a device that returns a zero for this bit field. unavailable = 0x0 i2c is not present in this product. available = 0x1 i2c is present in this product. 30 slave_present ro 0x1 this read-only bit indicates that the i2c slave function is present when it reads back a one. this i2c function is not available on a device that returns a zero for this bit field. unavailable = 0x0 i2c is not present in this product. available = 0x1 i2c is present in this product. 29 any_enabled_irq ro 0x0 this read-only bit indicates that the i2c controller has at least one enable interrupt requesting service. it is the logic or of all of the irq summary bits. no_requests = 0x0 no enabled in terrupts are requesting service. at_least_one_request = 0x1 at least one of the summary interrupt bits is set. 28:24 rsvd1 ro 0x0 always set this bit field to zero. 23:16 rcvd_slave_addr ro 0x00 this read-only byte indicates that the state of the slave i2c address byte received, including the read/write bit received from an address byte that matched our slave address. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 565 15 slave_addr_eq_zero ro 0x0 this read-only bit indicates that the i2c slave function was searching for a transa ction that matches the current slave address. when set to one, it indicates that an address match was found for the exact adderss 0x00. zero_not_matched = 0x0 i2c slave search did not match a zero. was_zero = 0x1 i2c has found an address match against address 0x00. 14 slave_found ro 0x0 this read-only bit indicates that the i2c slave function was searching for a transa ction that matches the current slave address. when set to one, it indicates that an address match was found and the i2c clock is frozen by the slave search. this bit is cleared by starting the appropriate slave dma transfer or restarting a slave search. idle = 0x0 i2c slave search is idle. waiting = 0x1 i2c has found an address match and is holding the i2c clock line low. 13 slave_searching ro 0x0 this read-only bit indicates that the i2c slave function is searching for a transaction that matches the current slave address. idle = 0x0 i2c slave search is idle. active = 0x1 i2c is actively searching for an address match. 12 data_engine_dma_wait ro 0x0 this read-only bit is set to one when the data engine is waitng for data from a dma device. this bit can be used to transmit short i2c transactions without using a dma channel. this generally works for up to three data bytes transmitted with one address byte. continue = 0x0 i2c master is not waiting on data from the dma. waiting = 0x1 i2c master is waiting on data from the dma. 11 bus_busy ro 0x0 this read-only bit indicates that the i2c bus is busy with a transaction. it is set by a start condition and reset by a detected stop condition. idle = 0x0 i2c bus is idle, i.e., reset state or at least one stop condition detected. busy = 0x1 i2c bus is busy, i.e. , at least one start condition has been detected. 10 clk_gen_busy ro 0x0 this read-only bit indicates that the i2c clock generator is busy with a transaction. idle = 0x0 i2c clock generator is idle. busy = 0x1 i2c clock generator is busy performing a command. 9 data_engine_busy ro 0x0 this read-only bit indicates that the i2c data transfer engine is busy with a data transmit or recieve opertion. in addition, it can be busy, as a master, sending a start or stop condition. idle = 0x0 i2c data engine is idle. busy = 0x1 i2c is data engine busy performing a data transfer. table 772. hw_i2c_stat bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 566 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 8 slave_busy ro 0x0 this read-only bit indicates that the i2c slave address search engine is busy with a transaction. this bit will go high when an address search is started and will remain high until the slave search engine returns to its idle state. idle = 0x0 i2c slave search engine is idle. busy = 0x1 i2c slave search engine is busy searching for an address match. 7 bus_free_irq_summary ro 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. it is a logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 6 data_engine_cmplt_irq_ summary ro 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. it is a logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 5 no_slave_ack_irq_summ ary ro 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. it is a logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 4 oversize_xfer_term_irq _summary ro 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. it is a logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 3 early_term_irq_summa ry ro 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. it is a logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 2 master_loss_irq_summ ary ro 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. it is a logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. table 772. hw_i2c_stat bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 567 description: the status register provides read-only ac cess to the function presence bits, as well as the busy indicators for the slave and master state machines. example: while(hw_i2c_stat.slave_busy != bv_i2c_stat_slave_busy__idle_val);// then wait till it finishes 21.7.7. i2c controller dma read and write data register description the i2c controller dma read and write data register is the target for both source and destination dma transfers. this regi ster is backed by an eight-deep fifo. hw_i2c_data 0x80058060 description: dma reads and writes are directed to this register. example: the dma data register is used by the dma to read or write data from the i2c controller, as mediated by the i2c controller`s dma request signal. 21.7.8. i2c device debug register 0 description the i2c device debug register 0 provides a diagnostic view into the internal state machine and states of the i2c device. hw_i2c_debug0 0x80058070 1 slave_stop_irq_summar y ro 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. it is a logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 0 slave_irq_summary ro 0x0 this bit is set to indicate that an interrupt is requested by the i2c controller. it is a logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. table 773. hw_i2c_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 data table 774. hw_i2c_data bit field descriptions bits label rw reset definition 31:0 data rw 0x00000000 the source dma channel writes to this address. the destination dma channel reads from this address. table 772. hw_i2c_stat bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 568 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 hw_i2c_debug0_set 0x80058074 hw_i2c_debug0_clr 0x80058078 hw_i2c_debug0_tog 0x8005807c description: this register provides access to variou s internal states and controls that are used in diagnostic modes of operation. example: while(hw_i2c_debug0.dmareq == old_dma_req_value); // wait for next dma request toggle table 775. hw_i2c_debug0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dmareq dmaendcmd dmakick tbd dma_state start_toggle stop_toggle grab_toggle change_toggle testmode slave_hold_clk slave_state table 776. hw_i2c_debug0 bit field descriptions bits label rw reset definition 31 dmareq ro 0x0 read-only view of the toggle state of the dma request signal. 30 dmaendcmd ro 0x0 read-only view of the toggle state of the dma end command signal. 29 dmakick ro 0x0 read-only view of the toggle state of the dma kick signal. 28:26 tbd rw 0x0 reserved 25:16 dma_state ro 0x010 current state of the dma state machine. 15 start_toggle ro 0x0 read-only view of the start detector. toggles once for each detected start condition. 14 stop_toggle ro 0x0 read-only view of the stop detector. toggles once for each detected stop condition. 13 grab_toggle ro 0x0 read-only view of the grab receive data timing point. toggles once for each read timing point, as delayed from rising clock. 12 change_toggle ro 0x0 read-only view of the change transmit data timing point. toggles once for each change transmit data timing point, as delayed from falling clock. 11 testmode rw 0x0 to be completed by designer. 10 slave_hold_clk ro 0x0 current state of the slave address search fsm clock hold register. 9:0 slave_state ro 0x0000 current state of the slave address search fsm. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 21: i 2 c interface 569 old_dma_req_value = hw_i2c_debug0.dmareq; // remember the new state of the dma request tog- gle 21.7.9. i2c device debug register 1 description the i2c device debug register 1 provides a diagnostic view of the external bus and provides oe control for the clock and data. hw_i2c_debug1 0x80058080 hw_i2c_debug1_set 0x80058084 hw_i2c_debug1_clr 0x80058088 hw_i2c_debug1_tog 0x8005808c table 777. hw_i2c_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i2c_clk_in i2c_data_in rsvd4 dma_byte_enables rsvd3 clk_gen_state rsvd2 lst_mode local_slave_test rsvd1 force_clk_on force_clk_idle force_arb_loss force_rcv_ack force_i2c_data_oe force_i2c_clk_oe table 778. hw_i2c_debug1 bit field descriptions bits label rw reset definition 31 i2c_clk_in ro 0x1 a copy of the pad input signal for the i2c clock pad. 30 i2c_data_in ro 0x1 a copy of the pad input signal for the i2c data pad. 29:28 rsvd4 ro 0x0 always set this bit field to zero. 27:24 dma_byte_enables ro 0x0 a read-only view of the byte enables for hw_i2c_data register writes. these bits are used in the i2c dma state machine to track the number of bytes written by the dma. individual bits are cleared as they are consummed. 23 rsvd3 ro 0x0 always set this bit field to zero. 22:16 clk_gen_state ro 0x0 a read-only view of the byte enables for hw_i2c_data register writes. these bits are used in the i2c dma state machine to track the number of bytes written by the dma. individual bits are cleared as they are consummed. 15:11 rsvd2 ro 0x0 always set this bit field to zero. 10:9 lst_mode rw 0x0 when in local slave test mode, this bit field defines the type of address generated for the slave. bcast = 0x0 broadcast, i.e., i2c address 0x00. my_write = 0x1 send to my slave address with a rw bit equal 0. my_read = 0x2 send to my slave address with a rw bit equal 1. not me = 0x3 send to an address that is not mine, i.e., bit four is complemented. free datasheet http:/// STMP36XX official product documentation 5/3/06 570 chapter 21: i 2 c interface 5-36xx-d1-1.02-050306 description: this register provides access to the i2c clock and data pad cell state that are used in diagnostic modes of operation. example: while(hw_i2c_debug1.i2c_clk_in == 0); // wait for i2c clock line to go high i2c xml revision: 1.55 8 local_slave_test rw 0x0 writting a one to this bit places the slave in local test mode. one of three slave address can be sent in either read or write mode. 7:6 rsvd1 ro 0x0 always set this bit field to zero. 5 force_clk_on rw 0x0 writing a one to this bit will force the clock generator to send a continuous stream of clocks on the i2c bus. 4 force_clk_idle rw 0x0 writing a one to this bit will force the clock generator state machine to return to its idle state and stay there. 3 force_arb_loss rw 0x0 writing a one to this bit will force the appearance of an arbitration loss on the next one a master attempts to transmit. 2 force_rcv_ack rw 0x0 writing a one to this bit will force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer. 1 force_i2c_data_oe rw 0x0 writting a one to this bit will force an output enable at the pad. the pad data line is tied to zero. thus the i2c data line will either be hi-z or zero. 0 force_i2c_clk_oe rw 0x0 writing a one to this bit will force an output enable at the pad. the pad data line is tied to zero. thus the i2c clock line will either be hi-z or zero. table 778. hw_i2c_debug1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 22: application uart 571 22. application uart this chapter describes the application uart included on the STMP36XX, how to operate it, and how to disable the fifos. programmable registers are described in section 22.4 . 22.1. overview the application uart: ? performs serial-to-parallel conversion on data received from a peripheral device ? performs parallel-to-serial conversion on data transmitted to the peripheral device ? operates up to 1.5 mb/s the cpu or dma controller reads and writes data and control/status information through the apbx interface. the transmit and receive paths are buffered with inter- nal fifo memories, enabling up to 16-bytes to be stored independently in both transmit and receive modes. the application uart includes a programmable baud rate generator that generates a common transmit and receive internal clock from the 24-mhz uart internal refer- ence clock input uartclk, which is tied internally to xclk. it offers similar functionality to the industry-standard 16c550 uart device and sup- ports baud rates of up to 1mbits/s (in high-speed configuration). figure 105 shows a block diagram of the application uart. the application uart operation and baud rate values are co ntrolled by the line control re gister (hw_ua rtapp_linectrl). the application uart can generate a single combined interrupt, so that the output is asserted if any of the individual interrupts are asserted and unmasked. interrupt sources include the receive (including timeout), transmit, modem status, and error conditions. two dma channels are supported, one for transmit and one for receive. if a framing, parity, or break error occurs during reception, the appropriate error bit is set and stored in the fifo. if an overrun condition occurs, the overrun register bit is set immediately and fifo data is prevented from being overwritten. you can pro- gram the fifos to be one-byte deep, providing a conventional double-buffered uart interface. the modem status input signal clear to send (cts) and output modem control line request to send (rts) are supported. a programmable hardware flow control fea- ture uses the nuartcts input and the nu artrts output to automatically control the serial data flow. free datasheet http:/// STMP36XX official product documentation 5/3/06 572 chapter 22: application uart 5-36xx-d1-1.02-050306 22.2. operation control data is written to th e application uart line cont rol register. this register defines: ? transmission parameters ? word length ? buffer mode ? number of transmitted stop bits ?parity mode ? break generation ? baud rate divisor 22.2.1. fractional baud rate divider the baud rate divisor is calculated from the frequency of xclk and the desired baud rate by using the following formula: divisor = (xclk * 4) / baud rate, rounded to the nearest integer the divisor must be between 0x00000040 an d 0x003fffc0, inclusive. program the lowest 6 bits of the divisor into baud_divf rac, and the next 16 bits of the divisor into baud_divint. 24-mhz xtal osc. divide by n uart uart programmable registers and fifos arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram uart2rx baudrate rx fsm uart2rts uart2cts uart2tx tx fsm xclk uartclk figure 105. applicat ion uart block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 22: application uart 573 22.2.2. uart character frame figure 106 illustrates the uart character frame. 22.2.3. dma operation the application uart can generate a dma request signal for interfacing with a direct memory access (dma) controller. two dma channels are supported, one for transmit and one for receive. each c hannel has an associated 16-bit transfer counter for the number of bytes to transfer. each dma request is associated with one to four data bytes. for apbx dma channel 6, which is the uart rx channel, the first pio word in th e dma command is ctrl1. howe ver, for apbx dma chan- nel 7, which is the uart tx, the first pio word in a dma command is ctrl1. at the end of a receive dma block transfer , the status register indicates any error conditions. if a timeout condition occurs in the middle of a receive dma block trans- fer, then the uart sends dummy data to the dma controller until the transfer counter is decremented to zero. a receive dm a can be setup to get the status of the previous receive dma block transfer. the st atus indicates the amount of valid data bytes in the previous receive dma block transfer. 22.2.4. data transmission or reception data received or transmitted is stored in two 16-byte fifos, although the receive fifo has an extra four bits per character for status information. for transmission, data is wr itten into the transmit fifo. if the application uart is enabled, it causes a data frame to start transmitting with the parameters indicated in uartlcr_h. data continues to be transmitted until there is no data left in the transmit fifo. the busy signal goes high as soon as data is written to the transmit fifo (that is, the fifo is non-empty) and remains asserted high while data is being transmitted. busy is negated only when the transmit fi fo is empty, and the last character has been transmitted from the shift register, including the stop bits. busy can be asserted high, even though the application uart might no longer be enabled. for each sample of data, three readings are taken and the majority value is kept. in the following paragraphs, the middle sampling point is defined, and one sample is taken on either side of it. ? when the receiver is idle (uartrxd continuously 1, in the marking state) and a low is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by baud16, begins running and data is sampled on the eighth cycle of that counter in normal uart mode to allow for the shorter logic 0 pulses (half way through a bit period). figure 106. application uart character frame free datasheet http:/// STMP36XX official product documentation 5/3/06 574 chapter 22: application uart 5-36xx-d1-1.02-050306 ? the start bit is valid if uartrxd is still low on the eighth cycle of baud16, otherwise a false start bit is detected and it is ignored. if the start bit was valid, successive data bits are sampled on every 16th cycle of baud16 (that is, one bit period later) according to the programmed length of the data characters. the parity bit is then checked if parity mode was enabled. ? lastly, a valid stop bit is confirmed if uartrxd is high, otherwise a framing error has occurred. when a full word is received, the data is stored in the receive fifo, with any error bits associated with that word (see table 779 ). 22.2.5. error bits three error bits are stored in bits [10:8] of the receive fifo and are associated with a particular character. an additional error indicating an overrun error is stored in bit 11 of the receive fifo. 22.2.6. overrun bit the overrun bit is not associated with the character in the receive fifo. the over- run error is set when the fifo is full and th e next character is co mpletely received in the shift register. the data in the shift regist er is overwritten, but it is not written into the fifo. when an empty location is available in the receive fifo and another character is received, the state of the overrun bit is copied into the receive fifo along with the received character. the overrun state is then cleared. table 779 shows the bit functions of the receive fifo. 22.2.7. disabling the fifos fifos can be disabled. in this case, the transmit and receive sides of the applica- tion uart have one-byte holding registers (the bottom entry of the fifos). the overrun bit is set when a word has been received and the previous one was not yet read. in this implementation, the fifos are not physically disabled, but the flags are manipulated to give the illusi on of a one-byte register. 22.3. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. table 779. receive fifo bit functions fifo bit function 11 overrun indicator 10 break error 9 parity error 8 framing error 7:0 received data free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 22: application uart 575 22.4. programmable registers this section describes the applicat ion uart?s programable registers. 22.4.1. uart receive dma control register description the uart receive dma control register co ntains the dynamic information associ- ated with the receive command. hw_uartapp_ctrl0 0x8006c000 hw_uartapp_ctrl0_set 0x8006c004 hw_uartapp_ctrl0_clr 0x8006c008 hw_uartapp_ctrl0_tog 0x8006c00c table 780. hw_uartapp_ctrl0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsvd2 run rsvd1 rx_source rxto_enable rxtimeout xfer_count table 781. hw_uartapp_ct rl0 bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 set to zero for normal operation. when this bit is set to one (default), then the entire block is held in its reset state. 30 clkgate rw 0x1 set this bit zero for normal operation. setting this bit to one (default), gates all of the block level clocks off for miniminizing ac energy consumption. 29 rsvd2 ro 0x0 reserved, read as zero, do not modify. 28 run rw 0x0 tell the uart to execute the rx dma command. the uart will clear this bit at the end of receive execution. 27:26 rsvd1 ro 0x0 reserved, read as zero, do not modify. 25 rx_source rw 0x0 source of receive data. if this bit is set to 1, the status register will be the s ource of the dm a, otherwise rx data will be the source. 24 rxto_enable rw 0x0 rxtimeout enable: if this bit is set to 0, the rx timeout will not affect receive dma operation. if this bit is set to 1, a receive timeout will cause the receive dma logic to terminate by filling the remaining dma bytes with garbage data. free datasheet http:/// STMP36XX official product documentation 5/3/06 576 chapter 22: application uart 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 22.4.2. uart transmit dma control register description the uart transmit dma control register contains the dynamic information associ- ated with the transmit command. hw_uartapp_ctrl1 0x8006c010 hw_uartapp_ctrl1_set 0x8006c014 hw_uartapp_ctrl1_clr 0x8006c018 hw_uartapp_ctrl1_tog 0x8006c01c 23:16 rxtimeout rw 0x03 receive timeout counter value: number of 8-bit-time to wait before asserting timeout on the rx input. if the rxfifo is not empty and the rx input is idle, then the watchdog counter will decrement each bit-time. note 7-bit-time is added to the programmed value, so a value of zero will set the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. also note that the counter is reloaded at the end of each frame, so if the frame is 10 bits long and the timeout counter value is zero, then timeout will occur (when fifo is not empty) even if the rx input is not idle. the default value is 0x3 (31 bit-time). 15:0 xfer_count rw 0x00 number of bytes to receive. this must be a multiple of 4. table 782. hw_uartapp_ctrl1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 run rsvd1 xfer_count table 783. hw_uartapp_ct rl1 bit field descriptions bits label rw reset definition 31:29 rsvd2 ro 0x0 reserved, read as zero, do not modify. 28 run rw 0x0 tell the uart to execute the tx dma command. the uart will clear this bit at the end of transmit execution. 27:16 rsvd1 ro 0x0 reserved, read as zero, do not modify. 15:0 xfer_count rw 0x00 number of bytes to transmit. table 781. hw_uartapp_ct rl0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 22: application uart 577 description: empty description. example: empty example. 22.4.3. uart control register description the uart control register contains configuation, including interrupt fifo level select and the dma control. hw_uartapp_ctrl2 0x8006c020 hw_uartapp_ctrl2_set 0x8006c024 hw_uartapp_ctrl2_clr 0x8006c028 hw_uartapp_ctrl2_tog 0x8006c02c table 784. hw_uartapp_ctrl2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 invert_rts invert_cts invert_tx invert_rx rsvd1 dmaonerr txdmae rxdmae rsvd2 rxiflsel rsvd3 txiflsel ctsen rtsen out2 out1 rts dtr rxe txe lbe rsvd4 sirlp siren uarten table 785. hw_uartapp_ct rl2 bit field descriptions bits label rw reset definition 31 invert_rts rw 0x0 invert rts signal. if this bit is set to 1, the rts output is inverted before transmitted. 30 invert_cts rw 0x0 invert cts signal. if this bit is set to 1, the cts input is inverted before sampled. 29 invert_tx rw 0x0 invert tx signal. if this bit is set to 1, the tx output is inverted before transmitted. 28 invert_rx rw 0x0 invert rx signal. if this bit is set to 1, the rx input is inverted before sampled. 27 rsvd1 ro 0x0 reserved, do not modify, read as zero. 26 dmaonerr rw 0x0 dma on error. if this bit is set to 1, receive dma will terminate on error. (cmd_end signal may not be asserted when this occurs.) 25 txdmae rw 0x0 transmit dma enable. data register can be loaded with up to 4 bytes per write. txfifo must be enabled in txdma mode. 24 rxdmae rw 0x0 receive dma enable. data register can be contain up to 4 bytes per read. rxfifo must be enabled in rxdma mode. 23 rsvd2 ro 0x0 reserved, do not modify, read as zero. free datasheet http:/// STMP36XX official product documentation 5/3/06 578 chapter 22: application uart 5-36xx-d1-1.02-050306 22:20 rxiflsel rw 0x2 receive interrupt fifo level select. the trigger points for the receive interrupt are as follows: not_empty = 0x0 trigger on fifo not empty, i.e., at least 1 of 16 entries. one_quarter = 0x1 trigger on fifo full to at least 4 of 16 entries. one_half = 0x2 trigger on fifo full to at least 8 of 16 entries. three_quarters = 0x3 trigger on fifo full to at least 12 of 16 entries. seven_eighths = 0x4 trigger on fifo full to at least 14 of 16 entries. invalid5 = 0x5 reserved. invalid6 = 0x6 reserved. invalid7 = 0x7 reserved. 19 rsvd3 ro 0x0 reserved, do not modify, read as zero. 18:16 txiflsel rw 0x2 transmit interrupt fifo level select. the trigger points for the transmit interrupt are as follows: empty = 0x0 trigger on fifo empty, i.e., no entries. one_quarter = 0x1 trigger on fifo less than 4 of 16 entries. one_half = 0x2 trigger on fifo less than 8 of 16 entries. three_quarters = 0x3 trigger on fifo less than 12 of 16 entries. seven_eighths = 0x4 trigger on fifo less than 14 of 16 entries. invalid5 = 0x5 reserved. invalid6 = 0x6 reserved. invalid7 = 0x7 reserved. 15 ctsen rw 0x0 cts hardware flow control enable. if this bit is set to 1, cts hardware flow control is enabled. data is only transmitted when the nuartcts signal is asserted. 14 rtsen rw 0x0 rts hardware flow control enable. if this bit is set to 1, rts hardware flow control is enabled. data is only requested when there is space in the receive fifo for it to be received. the fifo space is controlled by rxiflsel value. 13 out2 rw 0x0 this bit is the complement of the uart out2 (nuartout2) modem status output. (unsupported in stmp3600.) that is, when the bit is programmed to a 1, the output is 0. for dte, this can be used as ring indicator (ri). 12 out1 rw 0x0 this bit is the complement of the uart out1 (nuartout1) modem status output. (unsupported in stmp3600.) that is, when the bit is programmed to a 1, the output is 0. for dte, this can be used as data carrier detect (dcd). 11 rts rw 0x0 request to send. software can manually control the nuartrts pin via this bit when rtsen = 0. this bit is the complement of the uart request to send (nuartrts) modem status output. that is, when the bit is programmed to a 1, the output is 0. 10 dtr rw 0x0 data transmit ready. this bit is the complement of the uart data transmit ready (nuartdtr) modem status output. (unsupported in stmp3600.) that is, when the bit is programmed to a 1, the output is 0. table 785. hw_uartapp_ct rl2 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 22: application uart 579 9 rxe rw 0x1 receive enable. if this bit is set to 1, the receive section of the uart is enabled. data reception occurs for either uart signals or sir signals according to the setting of sir enable (siren, bit 1). when the uart is disabled in the middle of reception, it completes the current character before stopping. 8 txe rw 0x1 transmit enable. if this bit is set to 1, the transmit section of the uart is enabled. data transmission occurs for either uart signals or sir signals according to the setting of sir enable (siren, bit 1). when the uart is disabled in the middle of transmission, it completes the current character before stopping. 7 lbe rw 0x0 loop back enable. if this bit is set to 1 and the sir enable bit is set to 1 and the test register tcr bit 2 (sirtest) is set to 1, then the nsirout path is inverted and fed through to the sirin path. the sirtest bit in the test register must be set to 1 to override the normal half-duplex sir operation. this must be the requirement for accessing the test registers during normal operation, and sirtest must be cleared to 0 when loopback testing is finished. this feature reduces the amount of external coupling required during system test. if this bit is set to 1 and the sirtest bit is set to 0, the uarttxd path is fed through to the uartrxd path. in either sir mode or normal mode, when this bit is set, the modem outputs are also fed through to the modem inputs. 6:3 rsvd4 ro 0x0 reserved, do not modify, read as zero. 2 sirlp rw 0x0 irda sir low power mode. this bit selects the irda encoding mode. (unsupported in stmp3600.) if this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. if this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the irlpbaud16 input signal, regardless of the selected bit rate. setting this bit uses less power, but might reduce tr ansmission distances. table 785. hw_uartapp_ct rl2 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 580 chapter 22: application uart 5-36xx-d1-1.02-050306 description: use this register to define the fifo level at which the uarttxintr and uartrx- intr are triggered. the interrupts are generated based on a transition through a level rather than being based on the level. that is, the design is such that the inter- rupts are generated when the fill level progresses through the trigger level. the bits are reset so that the trigger level is when the fifos are at the half-way mark. example: empty example. 22.4.4. uart line control register description the uart line control register contains integer and fractional part of the baud rate divisor value. it also contains the line control bits. hw_uartapp_linectrl 0x8006c030 hw_uartapp_linectrl_set 0x8006c034 hw_uartapp_linectrl_clr 0x8006c038 hw_uartapp_linectrl_tog 0x8006c03c 1 siren rw 0x0 sir enable. if this bit is set to 1, the irda sir endec is enabled. (unsupported in stmp3600.) this bit has no effect if the uart is not enabled by bit 0 being set to 1. when the irda sir endec is enabled, data is transmitted and received on nsirout and sirin. uarttxd remains in the marking state (set to 1). signal transitions on uartrxd or modem status inputs have no effect. when the irda sir endec is disabled, nsirout remains cleared to 0 (no light pulses generated), and signal transitions on sirin have no effect. 0 uarten rw 0x0 uart enable. if this bit is set to 1, the uart is enabled. data transmission and reception occurs for either uart signals or sir signals according to the setting of sir enable (siren, bit 1). when the uart is disabled in the middle of transmission or reception, it completes the current character before stopping. table 786. hw_uartapp_linectrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 baud_divint rsvd baud_divfrac sps wlen fen stp2 eps pen brk table 785. hw_uartapp_ct rl2 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 22: application uart 581 description: empty description. example: empty example. 22.4.5. uart interrupt register description the uart interrupt register contains the interrupt enables and the interrupt status. the interrupt status bits report the unmasked state of the interrupts. to clear a par- ticular interrupt status bit, write the bit-clear address with the particular bit set to 1. the enable bits control the ua rt interrupt output: a 1 w ill enable a particular inter- table 787. hw_uartapp_line ctrl bit field descriptions bits label rw reset definition 31:16 baud_divint rw 0x0 baud rate integer [15:0]. the integer baud rate divisor. 15:14 rsvd ro 0x0 reserved, do not modify, read as zero. 13:8 baud_divfrac rw 0x0 baud rate fraction [5:0]. the fractional baud rate divisor. 7 sps rw 0x0 stick parity select. when bits 1, 2, and 7 of this register are set, the parity bit is transmitted and checked as a 0. when bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. when this bit is cleared stick parity is disabled. 6:5 wlen rw 0x0 word length [1:0]. the select bits indicate the number of data bits transmitted or received in a frame as follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits. 4 fen rw 0x0 enable fifos. if this bit is set to 1, transmit and receive fifo buffers are enabled (fifo mode). when cleared to 0, the fifos are disabled (character mode); that is, the fifos become 1-byte-deep holding registers. 3 stp2 rw 0x0 two stop bits select. if this bit is set to 1, two stop bits are transmitted at the end of the frame. the receive logic does not check for two stop bits being received. 2 eps rw 0x0 even parity select. if this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. when cleared to 0, then odd parity is performed which checks for an odd number of 1s. this bit has no effect when parity is disabled by parity enable (pen, bit 1) being cleared to 0. 1 pen rw 0x0 parity enable. if this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no parity bit added to the data frame. 0 brk rw 0x0 send break. if this bit is set to 1, a low-level is continually output on the uarttxd output, after completing transmission of the current character. for the proper execution of the break command, the software must set this bit for at least two complete frames. for normal use, this bit must be cleared to 0. free datasheet http:/// STMP36XX official product documentation 5/3/06 582 chapter 22: application uart 5-36xx-d1-1.02-050306 rupt to assert the ua rt interrupt output, wh ile a 0 will disable the particular interrupt from affecting the inte rrupt output. all the bits, except for the modem status interrupt bits, are cleared to 0 when reset. the modem status interrupt bits are undefined after reset. hw_uartapp_intr 0x8006c040 hw_uartapp_intr_set 0x8006c044 hw_uartapp_intr_clr 0x8006c048 hw_uartapp_intr_tog 0x8006c04c table 788. hw_uartapp_intr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 oeien beien peien feien rtien txien rxien dsrmien dcdmien ctsmien rimien rsvd2 oeis beis peis feis rtis txis rxis dsrmis dcdmis ctsmis rimis table 789. hw_uartapp_intr bit field descriptions bits label rw reset definition 31:27 rsvd1 ro 0x0 reserved, read as zero, do not modify. 26 oeien rw 0x0 overrun error interrupt enable. 25 beien rw 0x0 break error interrupt enable. 24 peien rw 0x0 parity error interrupt enable. 23 feien rw 0x0 framing error interrupt enable. 22 rtien rw 0x0 receive timeout interrupt enable. 21 txien rw 0x0 transmit interrupt enable. 20 rxien rw 0x0 receive interrupt enable. 19 dsrmien rw 0x0 nuartdsr modem interrupt enable. (unsupported in stmp3600.) 18 dcdmien rw 0x0 nuartdcd modem interrupt enable. (unsupported in stmp3600.) 17 ctsmien rw 0x0 nuartcts modem interrupt enable. 16 rimien rw 0x0 nuartri modem interrupt enable. (unsupported in stmp3600.) 15:11 rsvd2 ro 0x0 reserved, read as zero, do not modify. 10 oeis rw 0x0 overrun error interrupt status. to clear this bit, write the bit-clear address with the particular bit set to 1. 9 beis rw 0x0 break error interrupt status. to clear this bit, write the bit-clear address with the particular bit set to 1. 8 peis rw 0x0 parity error interrupt status. to clear this bit, write the bit-clear address with the particular bit set to 1. 7 feis rw 0x0 framing error interrupt status. to clear this bit, write the bit-clear address with the particular bit set to 1. 6 rtis rw 0x0 receive timeout interrupt status. to clear this bit, write the bit-clear address with the particular bit set to 1. 5 txis rw 0x0 transmit interrupt status. to clear this bit, write the bit-clear address with the particular bit set to 1. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 22: application uart 583 description: empty description. example: empty example. 22.4.6. uart data register description the uart data register is the receive and transmit data register. receive (read) and transmit (write) up to four data characters per apb cycle. hw_uartapp_data 0x8006c050 description: for words to be transmitted: 1) if the fifos are enabled, data written to this loca- tion is pushed onto the transmit fifo; 2) if the fifos are not enabled, data is stored in the transmitter holding register (the bo ttom word of the transmit fifo). the write operation initiates transmission from the primecell uart. the data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. the resultant word is then transmitte d. note: with the use of apb byte-enables you can write 1, 2, or 4 valid bytes sumult aneously to the txfifo. the invalid bytes will also take up space in the txfifo. so every write cycle w ill consume 4 bytes in 4 rxis rw 0x0 receive interrupt status. to clear this bit, write the bit- clear address with the particular bit set to 1. 3 dsrmis rw 0x0 nuartdsr modem interrupt status. (unsupported in stmp3600.) to clear this bit, write the bit-clear address with the particular bit set to 1. 2 dcdmis rw 0x0 nuartdcd modem interrupt status. (unsupported in stmp3600.) to clear this bit, write the bit-clear address with the particular bit set to 1. 1 ctsmis rw 0x0 nuartcts modem interrupt status. to clear this bit, write the bit-clear address with the particular bit set to 1. 0 rimis rw 0x0 nuartri modem interrupt status. (unsupported in stmp3600.) to clear this bit, write the bit-clear address with the particular bit set to 1. table 790. hw_uartapp_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 data table 791. hw_uartapp_data bit field descriptions bits label rw reset definition 31:0 data rw 0x0 in dma mode, up to 4 received/transmit characters can be accessed at a time. in pio mode, only one character can be accessed at a time. the status register contains the receive data flags and valid bits. table 789. hw_uartapp_intr bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 584 chapter 22: application uart 5-36xx-d1-1.02-050306 the txfifo. if txfifo is disabled, you must only write the lsbyte of the data reg- ister. for received words: 1) if the fifos are enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive fifo; 2) if the fifos are not enabled, the data byte and status are stored in the receiving hold- ing register (the bottom word of the receive fifo). the received data bytes (up to 4) are read by performing reads from the 32-bit data register. the status information can be read by a read of the uart status register. the overrun error bit is set to 1 if data is received and the re ceive fifo is already full. this is cleared to 0 once there is an empty space in the fifo and a new charac- ter can be written to it. the break error bit is set to 1 if a break condition was detected, indicating that the received data input was held low for longer than a full- word transmission time (defined as start, da ta, parity and stop bits). in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. when the parity error bit is set to 1, it indicates that the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the lcr_h register. in fifo mode, this error is associated with the charac- ter at the top of the fifo. when the framing er ror bit is set to 1, it indicates that the received character did not have a valid stop bit (a valid st op bit is 1). in fifo mode, this error is associated with the character at the top of the fifo. example: empty example. 22.4.7. uart status register description the uart status register contains the va rious flags and receive status. if the sta- tus is read from this register, then the st atus information for break, framing and par- ity corresponds to the data character read from the uart data register prior to reading the uart status register. the status information for overrun is set immedi- ately when an overrun condition occurs. hw_uartapp_stat 0x8006c060 table 792. hw_uartapp_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 present hispeed busy cts txfe rxff txff rxfe rxbyte_invalid oerr berr perr ferr rxcount free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 22: application uart 585 table 793. hw_uartapp_stat bit field descriptions bits label rw reset definition 31 present ro 0x1 this read-only bit indicates that the application uart function is present when it reads back a one. this application uart function is not available on a device that returns a zero for this bit field. unavailable = 0x0 uartapp is not present in this product. available = 0x1 uartapp is present in this product. 30 hispeed ro 0x1 this read-only bit indicates that the high-speed function is present when it reads back a one. this high speed function is not available on a device that returns a zero for this bit field. unavailable = 0x0 hispeed is not present in this product. available = 0x1 hispeed is present in this product. 29 busy ro 0x0 uart busy. 28 cts ro 0x0 clear to send. 27 txfe ro 0x1 transmit fifo empty. the meaning of this bit depends on the state of the fen bit in the uart line control register. if the fifo is disabled, this bit is set when the transmit holding register is empty. if the fifo is enabled, the txfe bit is set when the transmit fifo is empty. 26 rxff ro 0x0 receive fifo full. 25 txff ro 0x0 transmit fifo full. 24 rxfe ro 0x1 receive fifo empty. 23:20 rxbyte_invalid rw 0xf the invalid state of the last read of receive data. each bit corresponds to one byte of the rx data. (1 = invalid.) 19 oerr ro 0x0 overrun error. this bit is set to 1 if data is received and the fifo is already full. this bit is cleared to 0 by any write to the status register. the fifo contents remain valid since no further data is written when the fifo is full; only the contents of the shift register are overwritten. the cpu must now read the data in order to empty the fifo. 18 berr rw 0x0 break error. for pio mode, this is for the last character read from the data register. for dma mode, it will be set to 1 if any received character for a particular rxdma command had a break error. to clear this bit, write a zero to it. note that clearing this bit does not affect the interrupt status, which must be cleared by writing the interrupt register. 17 perr rw 0x0 parity error. for pio mode, this is for the last character read from the data register. for dma mode, it will be set to 1 if any received character for a particular rxdma command had a parity error. to clear this bit, write a zero to it. note that clearing this bit does not affect the interrupt status, which must be cleared by writing the interrupt register. free datasheet http:/// STMP36XX official product documentation 5/3/06 586 chapter 22: application uart 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 22.4.8. uart debug register description the uart debug register contains the state of the dma signals. hw_uartapp_debug 0x8006c070 16 ferr rw 0x0 framing error. for pio mode, this is for the last character read from the data register. for dma mode, it will be set to 1 if any received character for a particular rxdma command had a framing error. to clear this bit, write a zero to it. note that clearing this bit does not affect the interrupt status, which must be cleared by writing the interrupt register. 15:0 rxcount ro 0x0 number of bytes received during a receive dma command. table 794. hw_uartapp_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 txdmarun rxdmarun txcmdend rxcmdend txdmarq rxdmarq table 795. hw_uartapp_de bug bit field descriptions bits label rw reset definition 31:6 rsvd1 ro 0x0 reserved, read as zero, do not modify. 5 txdmarun ro 0x0 dma command run status: this bit reflects the state of the toggle signal for txdmarun. 4 rxdmarun ro 0x0 dma command run status: this bit reflects the state of the toggle signal for rxdmarun. 3 txcmdend ro 0x0 dma command end status: this bit reflects the state of the toggle signal for uart_txcmdend. 2 rxcmdend ro 0x0 dma command end status: this bit reflects the state of the toggle signal for uart_rxcmdend. 1 txdmarq ro 0x0 dma request status: this bit reflects the state of the toggle signal for uart_txdmareq. note that tx burst request is not supported. 0 rxdmarq ro 0x0 dma request status: this bit reflects the state of the toggle signal for uart_rxdmareq. note that rx burst request is not supported. table 793. hw_uartapp_stat bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 22: application uart 587 description: empty description. example: empty example. uartapp xml revision: 1.42 free datasheet http:/// STMP36XX official product documentation 5/3/06 588 chapter 22: application uart 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 23: debug uart 589 23. debug uart this chapter describes the debug uart included on the STMP36XX, how to oper- ate it, and how to disable the fifos. programmable registers are described in section 23.4 . 23.1. overview the debug uart performs: ? serial-to-parallel conversion on data received from a peripheral device ? parallel-to-serial conversion on data transmitted to the peripheral device the cpu reads and writes data and cont rol/status informat ion through the apbx interface. the transmit and receive paths are buffered with internal fifo memories, enabling up to 16 bytes to be stored independently in both transmit and receive modes. the debug uart includes a programmable baud rate generator that creates a common transmit and receive internal clock from the 24-mhz uart internal refer- ence clock input uartclk, which is tied internally to xclk. it offers similar functionality to the industry-standard 16c550 uart device and sup- ports baud rates of up to 1mbits/s (in high-speed configuration). figure 108 shows a block diagram of the debug uart. the debug uart operation and baud rate val- ues are controlled by the line control register (hw_uartapp_linectrl). the debug uart can generate a single combined interrupt, so output is asserted if any individual interrupt is asserted and unmasked. interrupt sources include the receive (including timeout), transmit, modem status, and error conditions. if a framing, parity, or break error occurs during reception, the appropriate error bit is set, and is stored in the fifo. if an overru n condition occurs, the overrun register bit is set immediately, and fifo data is prevented from being overwritten. you can pro- gram the fifos to be one-byte deep, providing a conventional double-buffered uart interface. unlike the application uart, the debug ua rt does not support dma or flow con- trol (cts/rts). free datasheet http:/// STMP36XX official product documentation 5/3/06 590 chapter 23: debug uart 5-36xx-d1-1.02-050306 23.2. operation control data is written to the debug uart line control register. this register defines: ? transmission parameters ? word length ? buffer mode ? number of transmitted stop bits ?parity mode ? break generation ? baud rate divisor 23.2.1. fractional baud rate divider the baud rate divisor is calculated from the frequency of xclk and the desired baud rate by using the following formula: divisor = (xclk * 4) / baud rate, rounded to the nearest integer the divisor must be between 0x00000040 an d 0x003fffc0, inclusive. program the lowest 6 bits of the divisor into baud_divf rac, and the next 16 bits of the divisor into baud_divint. in the debug uart, hw_uartdbglcr_h, hw_uartdbgibrd, and hw_uartdbgfbrd form a single 30-bit wi de register (uartlcr) that is updated on a single write strobe generated by an hw_uartdbglcr_h write. so, in order 24-mhz xtal osc. divide by n uart uart programmable registers and fifos arm core ahb slave ahb apbx master apbx ahb-to-apbx bridge sram uart1rx baudrate rx fsm uart1tx tx fsm xclk uartclk figure 107. debug uart block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 23: debug uart 591 to internally update the contents of hw_uartdbgibrd or hw_uartdbgfbrd, a write to hw_uartdbglcr_h must always be performed at the end. 23.2.2. uart character frame figure 108 illustrates the uart character frame. 23.2.3. data transmission or reception data received or transmitted is stored in two 16-byte fifos, though the receive fifo has an extra four bits per character for status information. for transmission, data is written into the transmit fifo. if the debug uart is enabled, it causes a data frame to start transmitting with the parameters indicated in uartlcr_h. data continues to be transmitted until there is no data left in the transmit fifo. the busy signal goes high as soon as data is written to the transmit fifo (that is, the fifo is non-empty) and remains asserted high while data is being transmitted. busy is negated only when the transmit fi fo is empty and the last character has been transmitted from the shift register, including the stop bits. busy can be asserted high even though the debug uart might no longer be enabled. for each sample of data, three readings are taken and the majority value is kept. in the following paragraphs, the middle sampling point is defined and one sample is taken either side of it. ? when the receiver is idle (uartrxd continuously 1, in the marking state) and a low is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by baud16, begins running and data is sampled on the eighth cycle of that counter in normal uart mode to allow for the shorter logic 0 pulses (half way through a bit period). ? the start bit is valid if uartrxd is still low on the eighth cycle of baud16, otherwise a false start bit is detected and it is ignored. if the start bit was valid, successive data bits are sampled on every 16th cycle of baud16 (that is, one bit period later) according to the programmed length of the data characters. the parity bit is then checked, if parity mode was enabled. ? lastly, a valid stop bit is confirmed if uartrxd is high, otherwise a framing error has occurred. when a full word is received, the data is stored in the receive fifo, with any error bits associated with that word (see table 796 ). figure 108. debug uart character frame free datasheet http:/// STMP36XX official product documentation 5/3/06 592 chapter 23: debug uart 5-36xx-d1-1.02-050306 23.2.4. error bits three error bits are stored in bits [10:8] of the receive fifo and are associated with a particular character. an additional error indicating an overrun error is stored in bit 11 of the receive fifo. 23.2.5. overrun bit the overrun bit is not associated with the character in the receive fifo. the over- run error is set when the fifo is full, a nd the next character is completely received in the shift register. the data in the shift register is overwritten, but it is not written into the fifo. when an empty location is available in the receive fifo, and another character is received, the state of the overrun bit is copied into the receive fifo along with the received character. the overrun state is then cleared. table 796 shows the bit functions of the receive fifo. 23.3. disabling the fifos fifos can be disabled. in this case, the transmit and receive sides of the primecell uart have one-byte holding registers (the bottom entry of the fifos). the overrun bit is set when a word has been received and the previous one was not yet read. in this implementation, the fifos are not physically disabled, but the flags are manipulated to give the illusi on of a one-byte register. 23.4. programmable registers this section describes the debug uart?s programable registers. 23.4.1. uart data register description for words to be transmitted: 1) if the fi fos are enabled, data written to this loca- tion is pushed onto the transmit fifo 2) if the fifos are not enabled, data is stored in the transmitter holding register (the bo ttom word of the transmit fifo). the write operation initiates transmission from the primecell uart. the data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. the resultant word is then transmitted. for received words: 1) if the fifos are enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive fifo 2) if the fifos are not enabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive fifo). the received data byte is read by performing reads from the dr reg- ister along with the corresponding status information. the status information can also be read by a read of the hw_uartdbgrsr_ecr register. hw_uartdbgdr 0x80070000 table 796. receive fifo bit functions fifo bit function 11 overrun indicator 10 break error 9 parity error 8 framing error 7:0 received data free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 23: debug uart 593 description: empty description. example: empty example. table 797. hw_uartdbgdr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved oe be pe fe data table 798. hw_uartdbgdr bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:12 reserved ro 0x0 reserved. 11 oe ro 0x0 overrun error. this bit is set to 1 if data is received and the receive fifo is already full. this is cleared to 0 once there is an empty space in the fifo and a new character can be written to it. 10 be ro 0x0 break error. this bit is set to 1 if a break condition was detected, indicating that the received data input was held low for longer than a full-word transmission time (defined as start, data, parity and stop bits). in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. 9 pe ro 0x0 parity error. when this bit is set to 1, it indicates that the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the lcr_h register. in fifo mode, this error is associated with the character at the top of the fifo. 8 fe ro 0x0 framing error. when this bit is set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). in fifo mode, this error is associated with the character at the top of the fifo. 7:0 data rw 0x0 receive (read) data character. transmit (write) data character. free datasheet http:/// STMP36XX official product documentation 5/3/06 594 chapter 23: debug uart 5-36xx-d1-1.02-050306 23.4.2. uart receive status register (read) and error clear register (write) description the rsr_ecr register is the receive status and error clear register. if the status is read from this register, then the status information for break, framing, and parity cor- responds to the data character read from dr prior to reading rsr_ecr. the status information for overrun is set immediately when an overrun condition occurs. a write to rsr_ecr clears the framing, parity, break, and overrun errors. hw_uartdbgrsr_ecr 0x80070004 description: empty description. example: empty example. 23.4.3. uart flag register description the fr register is the flag register. hw_uartdbgfr 0x80070018 table 799. hw_uartdbgrsr_ecr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable ec oe be pe fe table 800. hw_uartdbgrsr_ ecr bit field descriptions bits label rw reset definition 31:8 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 7:4 ec rw 0x0 error clear. any write to this bitfield clears the framing, parity, break, and overrun errors. the value is unpredictable when read. 3 oe rw 0x0 overrun error. this bit is set to 1 if data is received and the fifo is already full. this bit is cleared to 0 by any write to rsr_ecr. the fifo contents remain valid, since no further data is written when the fifo is full, only the contents of the shift register are overwritten. the cpu must now read the data in order to empty the fifo. 2 be rw 0x0 break error. 1 pe rw 0x0 parity error. 0 fe rw 0x0 framing error. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 23: debug uart 595 description: empty description. example: empty example. 23.4.4. uart irda low-power counter register description the uart irda low-power counter register is an 8-bit read/write register that stores a low-power counter divisor value used to divide down the uartclk to gen- erate the irlpbaud16 signal. hw_uartdbgilpr 0x80070020 table 801. hw_uartdbgfr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved ri txfe rxff txff rxfe busy dcd dsr cts table 802. hw_uartdbgfr bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:9 reserved ro 0x0 reserved, do not modify, read as zero. 8 ri ro 0x0 ring indicator. this bit is the complement of the uart ring indicator (nuartri) modem status input. that is, the bit is 1 when the modem status input is 0. 7 txfe ro 0x1 transmit fifo empty. the meaning of this bit depends on the state of the fen bit in the lcr_h register. if the fifo is disabled, this bit is set when the transmit holding register is empty. if the fifo is enabled, the txfe bit is set when the transmit fifo is empty. 6 rxff ro 0x0 receive fifo full. 5 txff ro 0x0 transmit fifo full. 4 rxfe ro 0x1 receive fifo empty. 3 busy ro 0x0 uart busy. 2 dcd ro 0x0 data carrier detect. 1 dsr ro 0x0 data set ready. 0 cts ro 0x0 clear to send. free datasheet http:/// STMP36XX official product documentation 5/3/06 596 chapter 23: debug uart 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 23.4.5. uart integer baud rate divisor register description the ibrd register is the integer part of the baud rate divisor value. hw_uartdbgibrd 0x80070024 table 803. hw_uartdbgilpr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable ilpdvsr table 804. hw_uartdbgilpr bit field descriptions bits label rw reset definition 31:8 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 7:0 ilpdvsr rw 0x0 irda low power divisor [7:0]. 8-bit low-power divisor value. table 805. hw_uartdbgibrd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable baud_divint table 806. hw_uartdbgibrd bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:0 baud_divint rw 0x0 baud rate integer [15:0]. the integer baud rate divisor. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 23: debug uart 597 description: empty description. example: empty example. 23.4.6. uart fractional baud rate divisor register description the fbrd register is the fractional part of the baud rate divisor value. hw_uartdbgfbrd 0x80070028 description: empty description. example: empty example. 23.4.7. uart line control register, high byte description the lcr_h is the line control register. hw_uartdbglcr_h 0x8007002c table 807. hw_uartdbgfbrd 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved baud_divfrac table 808. hw_uartdbgfbrd bit field descriptions bits label rw reset definition 31:8 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 7:6 reserved ro 0x0 not documented. 5:0 baud_divfrac rw 0x0 baud rate fraction [5:0]. the fractional baud rate divisor. free datasheet http:/// STMP36XX official product documentation 5/3/06 598 chapter 23: debug uart 5-36xx-d1-1.02-050306 table 809. hw_uartdbglcr_h 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved sps wlen fen stp2 eps pen brk table 810. hw_uartdbglcr_h bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:8 reserved ro 0x0 reserved, do not modify, read as zero. 7 sps rw 0x0 stick parity select. when bits 1, 2, and 7 of this register are set, the parity bit is transmitted and checked as a 0. when bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. when this bit is cleared, stick parity is disabled. 6:5 wlen rw 0x0 word length [1:0]. the select bits indicate the number of data bits transmitted or received in a frame as follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits. 4 fen rw 0x0 enable fifos. if this bit is set to 1, transmit and receive fifo buffers are enabled (fifo mode). when cleared to 0, the fifos are disabled (character mode); that is, the fifos become 1-byte-deep holding registers. 3 stp2 rw 0x0 two stop bits select. if this bit is set to 1, two stop bits are transmitted at the end of the frame. the receive logic does not check for two stop bits being received. 2 eps rw 0x0 even parity select. if this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. when cleared to 0, then odd parity is performed which checks for an odd number of 1s. this bit has no effect when parity is disabled by parity enable (pen, bit 1) being cleared to 0. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 23: debug uart 599 description: empty description. example: empty example. 23.4.8. uart control register description the cr is the control register. hw_uartdbgcr 0x80070030 1 pen rw 0x0 parity enable. if this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no parity bit added to the data frame. 0 brk rw 0x0 send break. if this bit is set to 1, a low-level is continually output on the uarttxd output, after completing transmission of the current character. for the proper execution of the break command, the software must set this bit for at least two complete frames. for normal use, this bit must be cleared to 0. table 811. hw_uartdbgcr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable ctsen rtsen out2 out1 rts dtr rxe txe lbe reserved sirlp siren uarten table 812. hw_uartdbgcr bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15 ctsen rw 0x0 cts hardware flow control enable. not implemented. 14 rtsen rw 0x0 rts hardware flow control enable. not implemented. 13 out2 rw 0x0 this bit is the complement of the uart out2 (nuartout2) modem status output. not implemented. 12 out1 rw 0x0 this bit is the complement of the uart out1 (nuartout1) modem status output. not implemented. 11 rts rw 0x0 request to send. not implemented. 10 dtr rw 0x0 data transmit ready. not implemented. table 810. hw_uartdbglcr_h bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 600 chapter 23: debug uart 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 23.4.9. uart interrupt fifo level select register description the ifls register is the interrupt fifo lev el select register. use the ifls register to define the fifo level at which the uarttxintr and uartrxintr are trig- gered. the interrupts are generated based on a transition through a level rather 9 rxe rw 0x1 receive enable. if this bit is set to 1, the receive section of the uart is enabled. data reception occurs for either uart signals or sir signals according to the setting of sir enable (siren, bit 1). when the uart is disabled in the middle of reception, it completes the current character before stopping. 8 txe rw 0x1 transmit enable. if this bit is set to 1, the transmit section of the uart is enabled. data transmission occurs for either uart signals or sir signals according to the setting of sir enable (siren, bit 1). when the uart is disabled in the middle of transmission, it completes the current character before stopping. 7 lbe rw 0x0 loop back enable. if this bit is set to 1 and the sir enable bit is set to 1 and the test register tcr bit 2 (sirtest) is set to 1, then the nsirout path is inverted and fed through to the sirin path. the sirtest bit in the test register must be set to 1 to override the normal half-duplex sir operation. this must be the requirement for accessing the test registers during normal operation, and sirtest must be cleared to 0 when loopback testing is finished. this feature reduces the amount of external coupling required during system test. if this bit is set to 1 and the sirtest bit is set to 0, the uarttxd path is fed through to the uartrxd path. in either sir mode or normal mode, when this bit is set, the modem outputs are also fed through to the modem inputs. 6:3 reserved ro 0x0 reserved, do not modify, read as zero. 2 sirlp rw 0x0 irda sir low-power mode. not supported. 1 siren rw 0x0 sir enable. if this bit is set to 1, the irda sir endec is enabled. not supported. 0 uarten rw 0x0 uart enable. if this bit is set to 1, the uart is enabled. data transmission and reception occurs for either uart signals or sir signals, according to the setting of sir enable (siren, bit 1). when the uart is disabled in the middle of transmission or reception, it completes the current character before stopping. table 812. hw_uartdbgcr bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 23: debug uart 601 than being based on the level. that is, the design is such that the interrupts are gen- erated when the fill level pr ogresses through th e trigger level. th e bits are reset so that the trigger level is when t he fifos are at the half-way mark. hw_uartdbgifls 0x80070034 description: empty description. example: empty example. 23.4.10. uart interrupt mask set/clear register description the imsc register is the interrupt mask se t/clear register. on a read, this register gives the current value of the mask on the relevant interrupt. on a write of 1 to the table 813. hw_uartdbgifls 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved rxiflsel txiflsel table 814. hw_uartdbgifl s bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:6 reserved ro 0x0 reserved, do not modify, read as zero. 5:3 rxiflsel rw 0x2 receive interrupt fifo level select. the trigger points for the receive interrupt are as follows: not_empty = 0x0 trigger on fifo not empty, i.e., at least 1 of 8 entries. one_quarter = 0x1 trigger on fifo full to at least 2 of 8 entries. one_half = 0x2 trigger on fifo full to at least 4 of 8 entries. three_quarters = 0x3 trigger on fifo full to at least 6 of 8 entries. seven_eighths = 0x4 trigger on fifo full to at least 7 of 8 entries. invalid5 = 0x5 reserved. invalid6 = 0x6 reserved. invalid7 = 0x7 reserved. 2:0 txiflsel rw 0x2 transmit interrupt fifo level select. the trigger points for the transmit interrupt are as follows: empty = 0x0 trigger on fifo empty, i.e., no entries. one_quarter = 0x1 trigger on fifo less than 2 of 8 entries. one_half = 0x2 trigger on fifo less than 4 of 8 entries. three_quarters = 0x3 trigger on fifo less than 6 of 8 entries. seven_eighths = 0x4 trigger on fifo less than 7 of 8 entries. invalid5 = 0x5 reserved. invalid6 = 0x6 reserved. invalid7 = 0x7 reserved. free datasheet http:/// STMP36XX official product documentation 5/3/06 602 chapter 23: debug uart 5-36xx-d1-1.02-050306 particular bit, it sets the corresponding mask of that interrupt. a write of 0 clears the corresponding mask. hw_uartdbgimsc 0x80070038 description: empty description. example: empty example. 23.4.11. uart raw interrupt status register description the uart raw interrupt status register is a read-only register. on a read, this reg- ister gives the current raw status value of the corresponding interrupt. a write has no effect. all the bits, except for the modem status interrupt bits (bits 3 to 0), are cleared to 0 when reset. the modem status interrupt bits are undefined after reset. table 815. hw_uartdbgimsc 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved oeim beim peim feim rtim txim rxim dsrmim dcdmim ctsmim rimim table 816. hw_uartdbgimsc bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:11 reserved ro 0x0 reserved, do not modify, read as zero. 10 oeim rw 0x0 overrun error interrupt mask. on a read, the current mask for the oeim interrupt is returned. on a write of 1, the mask of the oeim interrupt is set. a write of 0 clears the mask. 9 beim rw 0x0 break error interrupt mask. 8 peim rw 0x0 parity error interrupt mask. 7 feim rw 0x0 framing error interrupt mask. 6 rtim rw 0x0 receive timeout interrupt mask. 5 txim rw 0x0 transmit interrupt mask. 4 rxim rw 0x0 receive interrupt mask. 3 dsrmim rw 0x0 nuartdsr modem interrupt mask. 2 dcdmim rw 0x0 nuartdcd modem interrupt mask. 1 ctsmim rw 0x0 nuartcts modem interrupt mask. 0 rimim rw 0x0 nuartri modem interrupt mask. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 23: debug uart 603 hw_uartdbgris 0x8007003c description: empty description. example: empty example. 23.4.12. uart masked interrupt status register description the uart masked interrupt status register is a read-only register. on a read, this register gives the current masked status value of the corresponding interrupt. a write has no effect. all the bits except for the modem status interrupt bits (bits 3 to 0) are cleared to 0 when reset. the modem status interrupt bits are undefined after reset. hw_uartdbgmis 0x80070040 table 817. hw_uartdbgris 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved oeris beris peris feris rtris txris rxris dsrrmis dcdrmis ctsrmis rirmis table 818. hw_uartdbgri s bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:11 reserved ro 0x0 reserved, read as zero, do not modify. 10 oeris ro 0x0 overrun error interrupt status. 9 beris ro 0x0 break error interrupt status. 8 peris ro 0x0 parity error interrupt status. 7 feris ro 0x0 framing error interrupt status. 6 rtris ro 0x0 receive timeout interrupt status. 5 txris ro 0x0 transmit interrupt status. 4 rxris ro 0x0 receive interrupt status. 3 dsrrmis ro 0x0 nuartdsr modem interrupt status. 2 dcdrmis ro 0x0 nuartdcd modem interrupt status. 1 ctsrmis ro 0x0 nuartcts modem interrupt status. 0 rirmis ro 0x0 nuartri modem interrupt status. free datasheet http:/// STMP36XX official product documentation 5/3/06 604 chapter 23: debug uart 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 23.4.13. uart interrupt clear register description the uart interrupt clear register is writ e-only. on a write of 1, the corresponding interrupt is cleared. a wr ite of 0 has no effect. hw_uartdbgicr 0x80070044 table 819. hw_uartdbgmis 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved oemis bemis pemis femis rtmis txmis rxmis dsrmmis dcdmmis ctsmmis rimmis table 820. hw_uartdbgmis bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:11 reserved ro 0x0 reserved, read as zero, do not modify. 10 oemis ro 0x0 overrun error masked interrupt status. 9 bemis ro 0x0 break error masked interrupt status. 8 pemis ro 0x0 parity error masked interrupt status. 7 femis ro 0x0 framing error masked interrupt status. 6 rtmis ro 0x0 receive timeout masked interrupt status. 5 txmis ro 0x0 transmit masked interrupt status. 4 rxmis ro 0x0 receive masked interrupt status. 3 dsrmmis ro 0x0 nuartdsr modem masked interrupt status. 2 dcdmmis ro 0x0 nuartdcd modem masked interrupt status. 1 ctsmmis ro 0x0 nuartcts modem masked interrupt status. 0 rimmis ro 0x0 nuartri modem masked interrupt status. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 23: debug uart 605 description: empty description. example: empty example. table 821. hw_uartdbgicr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved oeic beic peic feic rtic txic rxic dsrmic dcdmic ctsmic rimic table 822. hw_uartdbgic r bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:11 reserved ro 0x0 reserved, read as zero, do not modify. 10 oeic w o 0x0 overrun error interrupt clear. 9 beic w o 0x0 break error interrupt clear. 8 peic w o 0x0 parity error interrupt clear. 7 feic w o 0x0 framing error interrupt clear. 6 rtic w o 0x0 receive timeout interrupt clear. 5 txic w o 0x0 transmit interrupt clear. 4 rxic w o 0x0 receive interrupt clear. 3 dsrmic w o 0x0 nuartdsr modem interrupt clear. 2 dcdmic w o 0x0 nuartdcd modem interrupt clear. 1 ctsmic w o 0x0 nuartcts modem interrupt clear. 0 rimic w o 0x0 nuartri modem interrupt clear. free datasheet http:/// STMP36XX official product documentation 5/3/06 606 chapter 23: debug uart 5-36xx-d1-1.02-050306 23.4.14. uart dma control register description the uart dma control register is a read/write register. all the bits are cleared to 0 on reset. hw_uartdbgdmacr 0x80070048 description: empty description. example: empty example. uartdbg xml revision: 1.22 table 823. hw_uartdbgdmacr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unavailable reserved dmaonerr txdmae rxdmae table 824. hw_uartdbgdmacr bit field descriptions bits label rw reset definition 31:16 unavailable ro 0x0 the uart ip only implements 16- and 8-bit registers, so the top two or three bytes of every 32-bit register are always unavailable. 15:3 reserved ro 0x0 reserved, read as zero, do not modify. 2 dmaonerr rw 0x0 dma on error. 1 txdmae rw 0x0 transmit dma enable. not implemented. 0 rxdmae rw 0x0 receive dma enable. not implemented. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 24: irda controller 607 24. irda controller this chapter describes the irda controller included on the STMP36XX. programma- ble registers are described in section 24.4 . 24.1. overview the STMP36XX provides a complete solution for implementing ir communications in embedded applications, including the following features: ? irda protocol controller ? high-performance irda protocol controller ? compatible with irda serial infrared physical layer specification (irphy), version 1.4 ? supports vfir, fir, mir, and sir rates. ? two independent dma channels a block diagram of the irda controller is shown in figure 109 . the STMP36XX uses a low-cost, low-power, irda very fast infrared (vfir) control- ler integrated circuit for enabling irda communicatio n capabilities in embedded designs. an ir communication subsystem can be implemented simply by adding an irda compatible transceiver. 24-mhz xtal osc. divide by n programmable registers and fifos arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram dma interface fsm ir_rx ir_tx ir serial integrated facg ir sclk figure 109. irda cont roller block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 608 chapter 24: irda controller 5-36xx-d1-1.02-050306 the irda controller on the STMP36XX is compatible with the irda serial infrared physical layer specification (irphy) version 1. 4. it supports a host interface, an ir protocol controller, and memory for buffer ing. the irda controller on the STMP36XX supports data rates up to 16 mbits per second (vfir), including all slower data rates (fir, mir, and sir). the ir protocol controller supports the various irda encode and decode operations required by the various data rates. this allows the STMP36XX to interface to a wide range of ir capable devices at the highest performance. the irda-compatible controller is programmed and controlled by software operating on the embedded host processor. the irda controller is software-configurable via the apbx bus through a set of accessible r egisters. details about the register set and a simple spi protocol are defined in section 24.4 . typically, an irda software stack, application software, and STMP36XX driver provides irda-compatible opera- tion. the STMP36XX is ideal for mobile applications where size and power consumption are important. when combined with a vfir transceiver, highly portable devices such as digital media players, mobile ph one handsets, and digi tal still cameras can provide a private, high- performance, wireless da ta transfer capability. 24.2. operation the ir controller is designed to meet the ir da physical layer sp ecification, version 1.4. for more information and detailed specif ications, refer to http://www.irda.org. all data rates that are called for in the specification are supported, including: ? sir: 2400 bps, 9600 bps, 19.2 kbps, 38.4 kbps, 57.6 kbps and 115.2 kbps ? mir: 576 kbps and 1.152 mbps ? fir: 4 mbps ?vfir: 16 mbps 24.2.1. dma operation the ir controller resides on the apbx bus as a dma slave. there are two indepen- dent dma channels for ir , one for transmission and on e for receiving. for apbx dma channel 6, which is the irda rx channel, the first pio word in the dma com- mand is ctrl1. however, for apbx dma cha nnel 7, which is the irda tx, the first pio word in a dma command is ctrl1. for a detailed description of how the dma works, refer to chapter 11 . the ir controller en codes data from th e apbx tx dma channel and sends it out over ir_tx to the transceiver. the incoming ir_rx is sampled and decoded, then transferred via the abpx dma rx channel. data is processed one byte (8 bits) at a time. the module also supports the serial interface using ir_sclk and communi- cates with the tr ansceiver device. 24.2.2. ir transmit processing the maximum size allowed is 2050 bytes pe r ir specifications. the size field on transmits can be 0; this is meaningful only if a speed change is requested. the ir block receives packets for transmission through an asynchronous fifo. when the tx block first detects the fifo is non-empty, it checks to see if rx or the serial interface is currently active. if no t, transmission begins immediately. other- wise, it waits until there is no othe r activity before starting transmission. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 24: irda controller 609 the ir tx block stalls the dma request if it is disabled or if its fifo is full. if the tx block is processing data faster than th e apbx dma is sending them, then an under- flow condition in the tx fifo can occur. th is is a catastrophic failure for the current frame because gaps in ir are not allowed. in such cases, the underflow flag pulses, and the error interrupt is generated, if it is enabled. a tx_irq is asserted for every completion of a frame, if enabled. 24.2.3. ir receive processing ir block starts a dma request once data is available in the rx fifo. the length of the received frame is unknown until the end-of -frame stop flag is detected, when the length of a rx dma transaction has to be determined. the rx dma interface issues a 32-bit status word for each dma block (the total dma length is the pro- grammed length + 4 bytes). if the status word is 0xffffffff, the current frame is not finished yet, and more data is available for retrieval. if the rx dma block size is larger than the remaining ir rx data, zeros are stuffed for the required dma trans- fer size, and the status word indicates the end of the frame. table 825 describes the rx status bit field definitions. the ir rx block stalls the dma request if it is disabled or if its fifo is empty. if the rx block is receiving data faster than the apbx dma readin g from it, then an over- flow condition in the rx fifo can occur. in such cases, the overflow flag pulses and the error interrupt is generated if it is enabled. an rx_irq is generated for every completion of a frame, if enabled. 24.2.4. ir serial interface ir can send serial command to the ir transceiver through the ir serial command interface. at power up, it is required that the ir transceiver be reset before access- ing it. this can be done by writing a 1 to the init bit in the hw_ir_tcctrl register. the host should then wait until the busy bit is low in the same register before attempting to access th e ir transceiver again. once reset, commands can be sent to the ir transceivers to put the transceiver into the desired operation speed and power mo de. as an example, a 1-byte register table 825. rx status bit field definitions bits label definition 23 rxtoobig the frame was discarded because it was too big for the available buffer. 22 rxbofinframe a 0xc0 (bof) was detected in the body of an incoming ir frame. the frame reception was consequently restarted after the bof and the previous data was discarded 21 rsvd1 20 rxmissedeof no 0xc1 (eof) was detected in the incoming ir frame. 19 rxmissedbof no 0xc0 (bof) was detected in the incoming frame. can only occur in sir when framing is active and rxbofover is set. 18 rxframeabort the frame was aborted due to error or transmitter abort. 17 rxcrcerror the frame had an invalid crc. 16 rxsuccess 1 if rx packet was successf ul. (no error bits set). 15:0 rxsize length of the rx frame in byte. free datasheet http:/// STMP36XX official product documentation 5/3/06 610 chapter 24: irda controller 5-36xx-d1-1.02-050306 write command looks like figure 110 (from the vishay semiconductors vfir trans- ceiver tfdu8108 specification). the bits indicated are driven out on ir_t x, and data is clocked using ir_sclk. after the data, addr, indx and c fields in the hw_ir_tcctrl register are pro- grammed, the ir issues the read/write co mmand to transceiver through the serial interface. 24.2.5. ir clock configuration there are two clocks in the ir controller. one is the ir_clk, which varies according the operation mode and speed. the ot her clock is the oversampling clock irov_clk, which runs at a multiple of the ir_clk frequency. the appropriate clock frequency (as listed in ta b l e 8 2 6 ) could be generated by programming the hw_clkctrl_irclkctrl register manually . however, the preferred way to get the desired ir clock frequency is to assert the auto_div bit in the hw_clkctrl_irclkctrl register. the cl ock controller then automatically pro- grams the ir_div and irov_div based on the speed and mode information from ir. 24.3. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. table 826. ir clock divider mode/speed ir_div irov_div sir 2400 bps 768 260 sir 9600 bps 192 260 sir 19.2 kps 96 260 sir 38.4 kps 48 260 sir 57.6 kps 32 260 sir 115.2 kbps 16 260 mir 0.576 mbps 16 52 mir 1.152 mbps 16 26 fir 4.0 mbps 5 12 vfir 16.0 mbps 5 4 0 1 1 r0 r1 r2 r3 a0 a1 a2 sync bits register address transceiver address write 0 0 stop bits 1 d0..d7 8-data bits figure 110. example of 1-byte serial interface write command free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 24: irda controller 611 24.4. programmable registers this section describes the irda controller?s programable registers. 24.4.1. ir control register description the ir control register contains gl obal ir configuration and enables. hw_ir_ctrl 0x80078000 hw_ir_ctrl_set 0x80078004 hw_ir_ctrl_clr 0x80078008 hw_ir_ctrl_tog 0x8007800c table 827. hw_ir_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsvd2 mta mode speed rsvd1 tc_time_div tc_type sir_gap sipen tcen txen rxen table 828. hw_ir_ctrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 set to zero for normal operation. when this bit is set to one (default), then the entire block is held in its reset state. also used as a clock gate. run = 0x0 allow ir to operate normally. reset = 0x1 hold ir in reset. 30 clkgate rw 0x1 set this bit zero for normal operation. setting this bit to one (default) gates all of the block level clocks off to miniminize ac energy consumption. 29:27 rsvd2 ro 0x0 reserved 26:24 mta rw 0x0 minimum turnaround time. the least delay from the last receive to when a transmission can begin. mta_10ms = 0x0 turnaround time > 10 ms mta_5ms = 0x1 turnaround time > 5 ms mta_1ms = 0x2 turnaround time > 1 ms mta_500us = 0x3 turnaround time > 0.5 ms mta_100us = 0x4 turnaround time > 0.1 ms mta_50us = 0x5 turnaround time > 0.05 ms mta_10us = 0x6 turnaround time > 0.01 ms mta_0 = 0x7 disabled 23:22 mode rw 0x0 irda mode. sir = 0x0 mir = 0x1 fir = 0x2 vfir = 0x3 21:19 speed rw 0x0 speed select. select speed in sir/mir mode. spd000 = 0x0 sir 9600bps mir 1.152 mbps spd001 = 0x1 sir 19.2kbps mir 0.576 mbps spd010 = 0x2 sir 38.4 kbps spd011 = 0x3 sir 57.6 kbps spd100 = 0x4 sir 115.2 kbps spd101 = 0x5 sir 2400 bps 18:14 rsvd1 ro 0x0 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 612 chapter 24: irda controller 5-36xx-d1-1.02-050306 description: empty description. example: empty example 24.4.2. ir transmit dma control register description the ir transmit dma control register configures the transmit dma. hw_ir_txdma 0x80078010 hw_ir_txdma_set 0x80078014 hw_ir_txdma_clr 0x80078018 hw_ir_txdma_tog 0x8007801c 13:8 tc_time_div rw 0x0 divider from apbx clock period for transceiver control timing 7 tc_type rw 0x0 transceiver control type. 0=serial interface 1=temic 6:4 sir_gap rw 0x0 gap between bytes in sir. number of bit-times to wait before deciding transmission has been blocked. gap_10k = 0x0 10,000 ir_clk cycles gap_5k = 0x1 5,000 ir_clk cycles gap_1k = 0x2 1,000 ir_clk cycles gap_500 = 0x3 500 ir_clk cycles gap_100 = 0x4 100 ir_clk cycles gap_50 = 0x5 50 ir_clk cycles gap_10 = 0x6 10 ir_clk cycles gap_0 = 0x7 disabled 3 sipen rw 0x0 sip enable. set to 1 to enable generation of sip in modes faster than sir. 2 tcen rw 0x0 transceiver enable. set to 1 to enable the serial interface or temic pulse generator. 1 txen rw 0x0 transmit enable. set to 1 to enable the transmit generator. 0 rxen rw 0x0 receive enable. set to 1 to enable the receive parser. table 829. hw_ir_txdma 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 run rsvd2 empty int change new_mta new_mode new_speed bof_type xbofs xfer_count table 828. hw_ir_ctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 24: irda controller 613 description: empty description. example: empty example. 24.4.3. ir receive dma register description the ir receive dma control regist er configures the receive dma. hw_ir_rxdma 0x80078020 hw_ir_rxdma_set 0x80078024 hw_ir_rxdma_clr 0x80078028 hw_ir_rxdma_tog 0x8007802c table 830. hw_ir_txdma bit field descriptions bits label rw reset definition 31 run rw 0x0 tells the ir to execute the transmit dma command. the ir will clear this bit at the end of transmit execution. 30 rsvd2 ro 0x0 reserved 29 empty rw 0x0 indicates there is no data associated with this descriptor. this is a speed-change only transaction. if this bit is set, xfer_count must be set to 0. 28 int rw 0x0 if set, will generate a speed-change interrupt at end of frame. note this interrupt will occur regardless of whether change is set. if software wants to change speeds at end of the frame, change must be set. 27 change rw 0x0 if set, an update to mode, speed, and mta register fields will occur at end of frame. 26:24 new_mta rw 0x0 new mta setting to take effect at the end of this frame. see mta field in ctrl register for encoding. 23:22 new_mode rw 0x0 new mode to change to at end of this frame. see mode field in ctrl register for encoding. 21:19 new_speed rw 0x0 new speed to change to at end of this frame. see speed field in ctrl register for encoding. 18 bof_type rw 0x0 select which version of xbof to use. 17:12 xbofs rw 0x0 number of extra bofs to transmit in sir. 11:0 xfer_count rw 0x0 number of bytes in the frame to transmit. data may be in multiple dma descriptors. if this register is written to, it is assumed a new frame is starting. free datasheet http:/// STMP36XX official product documentation 5/3/06 614 chapter 24: irda controller 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 24.4.4. ir debug control register description the ir debug control register includes c onfiguration bits normally used for debug- ging only. hw_ir_dbgctrl 0x80078030 hw_ir_dbgctrl_set 0x80078034 hw_ir_dbgctrl_clr 0x80078038 hw_ir_dbgctrl_tog 0x8007803c table 831. hw_ir_rxdma 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 run rsvd xfer_count table 832. hw_ir_rxdma bit field descriptions bits label rw reset definition 31 run rw 0x0 tell the ir to execute the rx dma command. the ir will clear this bit at the end of receive execution. 30:10 rsvd ro 0x0 reserved 9:0 xfer_count rw 0x0 number of words to receive in a data chunk. table 833. hw_ir_dbgctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 vfirswz rxfrmoff rxcrcoff rxinvert txfrmoff txcrcoff txinvert intloopback duplex mio_rx mio_tx mio_sclk mio_en free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 24: irda controller 615 description: empty description. example: empty example. 24.4.5. ir interrupt register description the ir interrupt register contains the inte rrupt enables and the interrupt status. the interrupt status bits report the unmasked stat e of the interrupts. to clear a particular interrupt status bit, write the bit-clear address with the particular bit set to 1. the enable bits control t he interrupt output: a 1 will enable a particular interrupt to assert the uart interrupt output, while a 0 will dis able the particular in terrupt from affect- ing the interrupt output. hw_ir_intr 0x80078040 hw_ir_intr_set 0x80078044 hw_ir_intr_clr 0x80078048 hw_ir_intr_tog 0x8007804c table 834. hw_ir_dbgctrl bit field descriptions bits label rw reset definition 31:13 rsvd2 ro 0x0 reserved 12 vfirswz rw 0x0 if set, swaps order of vfir data bit pairs. normal = 0 {d1,d2} = lsb, msb swap = 1 {d1,d2} = msb, lsb 11 rxfrmoff rw 0x0 if set, tries to capture sir frames without bof or eof. 10 rxcrcoff rw 0x0 if set, turns off crc checking on received frames. crc bytes are still sent to the host. 9 rxinvert rw 0x0 if set, inverts ir_rx before processing. 8 txfrmoff rw 0x0 if set, prevents ir from doing irda framing on transmits. 7 txcrcoff rw 0x0 if set, prevents ir from calculating and inserting crc into the transmit frame. 6 txinvert rw 0x0 if set, inverts ir_tx before outputting. 5 intloopback rw 0x0 if set, internally routes ir_tx to ir_rx. use in conjunction with duplex for loopback testing 4 duplex rw 0x0 put ir in duplex mode for testing. 3 mio_rx ro 0x0 read value on ir_rx. 2 mio_tx rw 0x0 value to drive out on ir_tx if mio_en=1. 1 mio_sclk rw 0x0 value to drive out on ir_sclk if mio_en=1. 0 mio_en rw 0x0 mio enable. if set, the values written into this register get output on ir_tx and ir_sclk. free datasheet http:/// STMP36XX official product documentation 5/3/06 616 chapter 24: irda controller 5-36xx-d1-1.02-050306 table 835. hw_ir_intr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 rxabort_irq_en speed_irq_en rxof_irq_en txuf_irq_en tc_irq_en rx_irq_en tx_irq_en rsvd1 rxabort_irq speed_irq rxof_irq txuf_irq tc_irq rx_irq tx_irq table 836. hw_ir_intr bit field descriptions bits label rw reset definition 31:23 rsvd2 ro 0x0 reserved 22 rxabort_irq_en rw 0x0 receive abort interrupt enable. disabled = 0x0 no interrupt request enabled. enabled = 0x1 interrupt request enabled. 21 speed_irq_en rw 0x0 speed change interrupt enable. disabled = 0x0 no interrupt request enabled. enabled = 0x1 interrupt request enabled. 20 rxof_irq_en rw 0x0 receive overflow interrupt enable. disabled = 0x0 no interrupt request enabled. enabled = 0x1 interrupt request enabled. 19 txuf_irq_en rw 0x0 transmit underflow interrupt enable. disabled = 0x0 no interrupt request enabled. enabled = 0x1 interrupt request enabled. 18 tc_irq_en rw 0x0 transceiver control interrupt enable. disabled = 0x0 no interrupt request enabled. enabled = 0x1 interrupt request enabled. 17 rx_irq_en rw 0x0 ir receive interrupt enable. disabled = 0x0 no interrupt request enabled. enabled = 0x1 interrupt request enabled. 16 tx_irq_en rw 0x0 transmit interrupt enable. disabled = 0x0 no interrupt request enabled. enabled = 0x1 interrupt request enabled. 15:7 rsvd1 ro 0x0 reserved 6 rxabort_irq rw 0x0 recieve abort interrupt status. indicates rxen was turned off while a valid frame was being received. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 5 speed_irq rw 0x0 speed change interrupt status. indicates the completion of a speed change. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 4 rxof_irq rw 0x0 receive overflow interrupt status. indicates a fifo overflow condition while receiving a frame. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 24: irda controller 617 description: empty description. example: empty example. 24.4.6. ir rx data register description the ir rx data register is the dma data register. it transmits (writes) or receives (reads) up to four data characters per apbx cycle. hw_ir_data 0x80078050 description: this register is shared by the transm it and receive dma channels. since transmit is always a write and receive is always a re ad, this does not create any conflicts. a pio write to this register pushes up to fo ur bytes into the ir txfifo. a pio read of this register reads up to fo ur bytes from the ir rxfifo. example: empty example. 3 txuf_irq rw 0x0 transmit underflow interrupt status. indicates a fifo underflow condition while attempting to transmit a frame. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 2 tc_irq rw 0x0 transceiver control interrupt status. indicates a transceiver control cycle has completed. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 1 rx_irq rw 0x0 receive interrupt status. indicates a complete frame has been received and buffered. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 0 tx_irq rw 0x0 transmit interrupt status. indicates a complete frame has been transmitted. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. table 837. hw_ir_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 data table 838. hw_ir_data bit field descriptions bits label rw reset definition 31:0 data rw 0x0 4 bytes of data. table 836. hw_ir_intr bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 618 chapter 24: irda controller 5-36xx-d1-1.02-050306 24.4.7. ir status register description the ir status register contains flags and status of the ir block. hw_ir_stat 0x80078060 table 839. hw_ir_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 present mode_allowed any_irq rsvd2 rxabort_summary speed_summary rxof_summary txuf_summary tc_summary rx_summary tx_summary rsvd1 media_busy rx_active tx_active table 840. hw_ir_stat bit field descriptions bits label rw reset definition 31 present ro 0x1 this read-only bit indicates that the application ir function is present when it reads back a one. this application ir function is not available on a device that returns a zero for this bit field. unavailable = 0x0 ir is no t present in this product. available = 0x1 ir is present in this product. 30:29 mode_allowed ro 0x0 this read-only field indicates the maximum mode ir that is allowed. vfir = 0x0 vfir speeds and below are allowed. fir = 0x1 fir speeds and below are allowed. mir = 0x2 sir and mir are allowed. sir = 0x3 only sir is allowed. 28 any_irq ro 0x0 any enabled interrupt requesting service. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 27:23 rsvd2 ro 0x0 reserved 22 rxabort_summary ro 0x0 receive abort interrupt enabled and requesting. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 21 speed_summary ro 0x0 speed change interrupt enabled and requesting. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 20 rxof_summary ro 0x0 receive overflow interrupt enabled and requesting. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 19 txuf_summary ro 0x0 transmit underflow interrupt enabled and requesting. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 18 tc_summary ro 0x0 transceiver control interrupt enabled and requesting. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 17 rx_summary ro 0x0 ir receive interrupt enabled and requesting. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 24: irda controller 619 description: empty description. example: empty example. 24.4.8. ir transceiver control register description the ir transceiver control register controls both temic style and serial interface transceivers. hw_ir_tcctrl 0x80078070 hw_ir_tcctrl_set 0x80078074 hw_ir_tcctrl_clr 0x80078078 hw_ir_tcctrl_tog 0x8007807c 16 tx_summary ro 0x0 transmit interrupt enabled and requesting. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 15:3 rsvd1 ro 0x0 reserved 2 media_busy ro 0x0 media busy indicates ir is currently sending or has detected an active transmitter in the medium. 1 rx_active ro 0x0 ir receive is currently receiving a valid irda frame. 0 tx_active ro 0x0 ir transmit is currently busy transmitting a frame. table 841. hw_ir_tcctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 init go busy rsvd temic ext_data data addr indx c table 842. hw_ir_tcctrl bit field descriptions bits label rw reset definition 31 init w o 0x0 a write to this register will start a reset cycle for serial interface transceivers. ignored for temic. 30 go w o 0x0 a write to this register will start a control cycle. for temic, it starts a speed change pulse. for serial interface, it starts to send out the command in fields 23:0 29 busy ro 0x0 while a serial interface command or temic pulse is still being processed, this bit will read 1. 28:25 rsvd ro 0x0 reserved 24 temic rw 0x0 temic pulse value to send. only us ed if tc_type=1. low = 0x0 low speed pulse high = 0x1 high speed pulse table 840. hw_ir_stat bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 620 chapter 24: irda controller 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 24.4.9. ir serial interface read data register description the ir serial interface read data register contains the return data on a serial inter- face read command. hw_ir_si_read 0x80078080 description: empty description. example: empty example. 24.4.10. ir debug register description this is the ir debug register. 23:16 ext_data rw 0x0 extended data. only valid for serial interface writes with an extended index. 15:8 data rw 0x0 data or extended index. if indx=1111, this is an extended index field. if indx!=special command(1111), this is the data field. 7:5 addr rw 0x0 trasceiver address for serial interface command. 4:1 indx rw 0x0 index field for serial interface command. 0 c rw 0x0 c bit for serial interface command. indicates transfer direction. 0=read, 1=write table 843. hw_ir_si_read 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 abort data table 844. hw_ir_si_read bit field descriptions bits label rw reset definition 31:9 rsvd1 ro 0x0 reserved 8 abort ro 0x0 when high, indicates the last serial transceiver read was not completed. this oc curs when the transceiver fails to drive a start bit to the 4230 within four ir_sclk cycles 7:0 data ro 0x0 data returned by the transceiver on a read command. table 842. hw_ir_tcctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 24: irda controller 621 hw_ir_debug 0x80078090 description: empty description. example: empty example. ir xml revision: 1.29 table 845. hw_ir_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 txdmakick rxdmakick txdmaend rxdmaend txdmareq rxdmareq table 846. hw_ir_debug bit field descriptions bits label rw reset definition 31:6 rsvd1 ro 0x0 reserved 5 txdmakick ro 0x0 dma kick toggle line for transmitter. 4 rxdmakick ro 0x0 dma kick toggle line for receiver. 3 txdmaend ro 0x0 transmit dma command end signal value. 2 rxdmaend ro 0x0 receive dma command end signal value. 1 txdmareq ro 0x0 transmit dma request signal value. 0 rxdmareq ro 0x0 receive dma request signal value. free datasheet http:/// STMP36XX official product documentation 5/3/06 622 chapter 24: irda controller 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 623 25. audioin/adc this chapter describes the audioin/adc module implemented on the STMP36XX, including dma, sample rate conversion, and internal operation. programmable reg- isters are described in section 25.6 . 25.1. overview the STMP36XX features an audio record path that consists of a sigma-delta analog- to-digital converter (adc), followed by the audioin digital multi-stage finite impulse response (fir) filter. the microphone or line input is oversamp led by the adc, and the 1-bit digital stream is input to a cascaded-integrator co mb filter, where the si gnal is parallelized, sent through a high-pass filter to remove dc offset, and the sample rate is con- verted to the audioin?s internal rate. next, the signal is filtered using a three-stage fir filter. the resultant parallel pcm samples are then transferred to a buffer in memory using the apbx bridge dma, where it can be read by system software. the analog audio source can be selected from one of three possible inputs: ? mono microphone input ? stereo line inputs ? looped back from the stereo headphone amplifier the audioin module implements the following functions: ? serial to parallel bit-stream integrator/averager ? sample rate converting (src) cascaded-integrator comb (cic) filter ? high-pass filter (hpf) ? three-stage downsampling fir filter: 7-tap (8:4), 11-tap (4:2), 33-tap (2:1) supporting conversion from quarter, half, full, double, and quad sample rates that are multiples of the standard 32 khz, 44.1 khz, and 48 khz rates ? 16- or 32-bit pcm sample widths ? apbx bridge dma interface ? independent control of each channel?s volume (including mute) ? dac-to-adc internal loopback for product development ? control bit fields used for analog adc settings figure 111 shows the audio path and control options, and figure 112 is a high-level block diagram of the audioin module. free datasheet http:/// STMP36XX official product documentation 5/3/06 624 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 line 1 adc l fifo to adc dma adc gain adc left input mux mic bias micin line 2 speaker headphone right headphone left dac r fifo from dac dma line 1 r dac l from dac dma line 1 l controlled by speaker pwd select=00 select=01 select=10 select=00 or 10 select=01 audioout_hpvol_select note: select=11 is invalid output speaker output r output l fifo adc r fifo to adc dma adc gain adc right input mux 1 1 2 2 7 7 4 4 5 5 6 3 1. audioout_dacvolume: digital volume control. 2. audioout_hpvol: analog volume control. 3. audioout_spkrvol: analog volume contro l that works on the speaker amp output. 4. audioin_adcvolume: digital volume control. 5. audioin_adcvol: analog volume control that controls the adc gain block. 6. audioin_micline_micgain: analog volume control that controls the mic amp. 7. atten_line bit notes: figure 111. mixed signal audio elements free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 625 25.2. operation the first step in receiving audio to th e audioin module requires the analog-to- digital converter (adc). the STMP36XX includes a high-performance analog stereo sigma-delta adc. it converts analog audio to two (left and right channel) single-bit digital streams that are input to the audioin module, along with a clock that runs at the sigma-delta oversampling clock rate. the audioin module includes hardware for oversampling, decimation, and arbitr ary sample rate conversion. the 1-bit stream is input to a cascaded-integrator comb filter where serial-to-parallel data conversion, as well as sample rate conver sion, takes place, along with a high-pass filter to eliminate dc offset. serial audio is first input to an av erager that initially converts samples to 8-bit values. the cic then interpolates/decimates as well as sign-extends the parallel data, converting the samples from the programmed standard external sample rate to the audioin module?s internal rate. the resultant 24-bit pcm samples are then stored to the module?s ram. 24-mhz xtal osc. divide by n adc programmable registers arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram adc digital filtering, decimation, sample rate conversion dma request analog to 1-bit conversion line or mic in clock control figure 112. audioin/adc block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 626 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 these 24-bit samples are then filtered using a three-stage fir filter, consisting of 7, 11, and 33 taps, respectively. the audi oin contains a sequencer, multiply- accumulate hardware, and a set of filter coefficients that performs successive iterations on the data stored in ram. inte rmediate data that is calculated along the taps/stages of the fir are also stored in the audioin?s ram. the resultant filtered pcm data is then stored in a fifo that ca n either be directly accessed by the host cpu or read by the STMP36XX?s ahb-apbx bridge dma engine to store the data in on- or off-chip memory to al low access to system software. in most cases, a ccess to the audioin?s data is made by the ahb-apbx bridge dma. dma channel 0 is dedicated to the audioin module. the dma moves data from the audioin?s memory-mapped data register to a ram buffer every time a request is made. the buffer may be in on- or off-chip ram. it is also possible for the cpu to manually move data from the audioin data register while monitoring either the fifo or dma request status bits in the audioin debug register (hw_audioin_adcdebug). also present on the STMP36XX is an a udio playback path called audioout/dac. although each functions independently of one another, both the audioin and audioout blocks share their fir filter (sequencer/ram/coefficients) and dma controller. this combined modu le is titled the ?digital f ilter? or digfilt. the register descriptions that follow both refer to each path independently (audioin and audioout) as well as a whole (digfilt), due to the fact that clocks and resets affect either the shared resources or the design as a whole. in order to configure the audioin/adc for operation, the user must first clear the clock gate (clkgate) and soft reset (s ftrst) bits within the audioin control register (hw_audioin_ctrl). the run bit should remain off (zero), while all other control bits are initialized. it is important to note that there are also a number of con- trol bits within the audioout?s address sp ace that control functions within the ana- log adc. the user must clear the clock gate and soft reset of the audioout block in order to program these bits. next, the bridge dma controller channel 0 should be programmed and enabled to collect input audio samples to one or more ram buff- ers. finally, the run bit should be set to start audioin/adc operation. each 32-bit register within the audioin?s address space is aliased to four adjacent words. the first word is used for normal read-write access while the subsequent three words are contained within the register?s set-clear-toggle (sct) address space. only bits that are written to with a one in this space are affected. for exam- ple, writing a one to bit using the register?s set address sets that particular bit, while maintaining the state of all other bits. this convention allows easy bit manipulation without requiring the standard read-modify- write procedure. bits that are written with a one to the register?s clear address clea r the bit, while the toggle address causes bits to invert their current state. 25.2.1. audioin dma the dma is typically controlled by a linked list of descriptors. the descriptors are usually circularly linked, causing the dma to cycle through the set of dma buffers. the dma can be programmed to assert an irq when some or all of the buffers have been filled. for example, audioin dma descriptor 0 ma y program the dma to fill a buffer, set the done irq, and fetch descriptor 1. de scriptor 1 programs th e dma to fill the next buffer. the dma continues to operate normally while the irq is asserted. the cpu free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 627 needs to respond to the irq before the dma has filled a ll of the buffers. the dma isr clears the irq fl ag and informs the op erating system that th e buffers are filled. in general, software copies data out of the buffers or adjusts the descriptors to point to other empty buffers. software should also take advantage of the dma?s counting semaphore feature to synchronize the add ition of new descriptors to the chain. the dma can put the audioin?s pcm data into any memory-mapped location. for 32-bit pcm data, the left-cha nnel sample is stor ed first in the lowest address, fol- lowed by the corresponding right-channel sample in the next word address (+4 bytes). for 16-bit mode, sample pairs are stored in each word. right samples are stored in the upper half-word while left samples are stored in the lower half-word. because the audioin always operates on stereo data, the pcm buffer should always have an integer number of words. the audio data values are in two?s com- plement format, where full-scale values range from 0x7fffffff to 0x80000000 for 32-bit data or 0x7fff to 0x8000 for 16-bit data. in addition to the dma irq used to indica te a filled audioin bu ffer, the module also has an overflow and underflow irq. under flows should never occur, because (by design) the dma should never attempt to read more data than is present within the audioin?s fifo. however, if the audioin ev er attempts to write data into a full fifo, an overflow occurs. this causes the overflow flag to be set in the audioin control register (hw_audioin_ctrl). if the overflow/underflow irq enable bit is set, then this condition also asserts an interrupt. the interrupt is cleared by writing a one to the overflow flag in the hw_audioin_ctrl?s sct clear address space. an audioin underflow is typically caused by the dma running out of new buffers, or if the ahb or apbx is stalled or are otherw ise unable to meet the bandwidth require- ments at the current operating frequency. if the counting semaphore reaches 0, the dma stops processing new descriptors and stops moving data from the audioin?s data register (hw_audioin_data). 25.3. adc sample rate conver ter and internal operation table 847 contains the required value of the hw_audioout_adcssr register for various common sample rates. to make small sample rate adjustments (for exam- ple to track fs fluctuations during a mi x with an fm output to the dac), the user may change the last few lsbs of the src_frac bit field to speed or slow the rate of sample consumption unt il equilibrium between the ad c?s sample rate and the rate of another audio stream is met. note that, unlike the dac, only small deviations to src_frac can be made . the only valid values for basemult, src_hold, and src_int are listed in table 847 . table 847. bit field values for standard sample rates sample rate hw_audioout_adcssr fsample adc basemult src_hold src_int src_frac 192,000 hz 0x4 0x0 0x0f 0x13ff 176,400 hz 0x4 0x0 0x11 0x0037 128,000 hz 0x4 0x0 0x17 0x0e00 96,000 hz 0x2 0x0 0x0f 0x13ff 88,200 hz 0x2 0x0 0x11 0x0037 64,000 hz 0x2 0x0 0x17 0x0e00 48,000 hz 0x1 0x0 0x0f 0x13ff free datasheet http:/// STMP36XX official product documentation 5/3/06 628 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 note : sample rates greater than 48 khz can only be used when the audioout is disabled, and 44.1 khz is the maximum sample rate at which both the audioin and audioout can operate simultaneously. for any of the desired sample rates, the inte rnal sample-rate conver sion factor is calcu- lated according to the following formula: srconv adc = 65536 * [ fanalog adc )/ (8 * fsample adc )] the 1-bit sigma delta a/d converter is always sampled on a submultiple of the 24.0-mhz crystal oscillator frequency, as spec ified in the hw_ccr_adcdiv regis- ter (see figure 113 ). this divider generates sample strobes at fanalog adc where the divisors available come from the set {4,6,8,12,16,2 4}. it is recommended that adcdiv always be set to 000 so that a 6.0-mhz 1-bit a/d sample rate is used. the sample strobe is used to integrate the 1-bit a/d values. as shown in figure 113 , these integrated values are filtered and then delivered to the adc dma to write into on-chip ram. notice that the integrators run continuously while the filters produce samples at the decimated rate. depending on the decimation or over-sample ratio of the cic filter engine, the integrators will pr oduce samples of various pr ecisions and scale factors. the filtered values written to the adc fifo are signed 16-bit or 24-bit numbers with the conversion data lsb-justified, i.e., downscaled in the lower end of the word. the scale factor column of the 48-khz family of sample rates satisfies the property: 24.576 mhz = q*fsample adc where q comes from the set of integers these sample rates include 48 khz, 32 khz, 24 khz, 16 khz, 12 khz, and 8 khz. there are also the members of the 44.1-khz family, whose members satisfy the property: 16.9344 mhz = q*fsample adc where q comes from the set of integers these sample rates include 44.1 khz, 22.05 khz, and 11.025 khz. since 24.576 khz and 16.9344 mhz are relatively prime to 24.0 mhz, members of the 48-khz family and 44.1-khz family are related to the 24.0-mhz source clock by the relationship: 44,100 hz 0x1 0x0 0x11 0x0037 32,000 hz 0x1 0x0 0x17 0x0e00 24,000 hz 0x1 0x1 0x0f 0x13ff 22,050 hz 0x1 0x1 0x11 0x0037 16,000 hz 0x1 0x1 0x17 0x0e00 12,000 hz 0x1 0x3 0x0f 0x13ff 11,025 hz 0x1 0x3 0x11 0x0037 8,000 hz 0x1 0x3 0x17 0x0e00 table 847. bit field values for standard sample rates (continued) sample rate hw_audioout_adcssr fsample adc basemult src_hold src_int src_frac free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 629 24.0 mhz=p*fsample adc , where p is a rational number the a/d block includes a variable rate or rational decimator as shown in figure 113 to accommodate these sample rates. rational numbers in the adc are approxi- mated with a scaled fixed-point 24-bit value. in this case, the decimal point falls between bit 15 and bit 16. therefore, th e lower two bytes hold the fractional part, while the upper byte holds the whole number portion of the scaled fixed point. the position register uses this scaled fixed-point representation to hold the number of 1-bit samples to be dropped (decimated) to find the next sample at which to produce a filtered multibit sigma delta a/d value to send to the dma. whenever the whole number part (bits 23:16) is zero, then a sample is produced. the range of values of the samples stored into the on-chip ram is proportional to the square of the over-sample rate (osr) used in the capture process. the larger the osr, the longer period the integrators run in the adc. as a result, the range of values seen for the same signal wave fo rm captured at the same sample rate but with two different osr will be different. for example: ? an 8-khz microphone captured at f adc = 6.0 mhz will be 36 times smaller than the values resulting from capturing the same source signal at f adc = 1.0 mhz. 1-bit a/d xtal osc analog_l lsamp_in ad_div 24.0 mhz hw_ccr_adc_div xtal_clk cic filter and interpolators ad_div table cic state matchine 6.0-mhz sample strobe +/- 1 integrator variable rate decimator 31 position reg 16 15 1 1 samp_strobe pos_zero= (position_reg[31:16] == 16'h0000) position_reg[31:0] + hw_adcsrr_sr 24'hff0000 whole # fraction variable rate decimator pos_zero frac[15:0] lsamp_out[23:0] dma_request 1-bit a/d analog_r rsamp_in cic filter and interpolators +/- 1 integrator rsamp_out[23:0] high-pass filter high-pass filter figure 113. variable-rate a/d converter free datasheet http:/// STMP36XX official product documentation 5/3/06 630 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 ? the peak range of values seen in a capture of a signal at 44.1 khz with fanalog adc = 6.0 mhz is 3200 decimal. ? the oversample ratio in this case is osr= 136.054. ? calculate a magnitude constant, k filter for adc?s filter from this as k filter = osr 2 /peak value = (136.054) 2 /3200 = 5.7846. ? for any osr in any sample rate, the peak value can be approximated by value peak = osr 2 /k filter . in signal processing, one frequently norma lizes the range of values to 1.0, as seen in a fixed-point scaled integer 1 . for a 24-bit dsp, the fixed point is placed between bit 23 and the sign bit (bit 24) (bit 1 = 2 0 ). so the desired maximum excursion is then 2 23 or 8388608, decimal. one can calculate a normalization constant to multiply all in coming samples for each sampling condition from the following equation (note that osr is fixed at 6 mhz for the STMP36XX): scalefactor = 2 23 * k filter / osr 2 if the incoming sample stream is multiplied, sample by sample, by scalefactor, then normalized 1.0 samples result. all data output from the digfilt adc are scaled according to this equation. 25.4. microphone the external microphone needs a bias voltage to enable it to operate. this bias volt- age can be generated externally using discrete components as shown in figure 114 . or, if either the lradc0 or lradc1 pin is available, it can be used to supply a bias voltage from an on-chip generator, as shown in figure 115 . to enable the generation of the microphone bias voltage on pin lradc0 or lradc1, the two mic_resistor bits in the hw_audioin_micline register need to be written with required values for desired internal re sistor selection. to select either pin lradc1 or lradc0 as the microphone bi as source, write the mic_select bit in the hw_audioin_micline r egister as follows: 0 for pin lradc0, 1 for pin lradc1. 1.a normalized two?s complement 24-bit number cannot ac tually express a value of +1.0 without overflowing. mic vddio 0.1f microphone 2.2k 2.2k 0.1f 10f figure 114. external microphone bias generation free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 631 25.5. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 25.6. programmable registers the following registers provide control for programmable elements of the audioin/acd block. 25.6.1. audioin control register description the audioin control register provides overall control of the digital portion of the analog-to-digital converter. hw_audioin_ctrl 0x8004c000 hw_audioin_ctrl_set 0x8004c004 hw_audioin_ctrl_clr 0x8004c008 hw_audioin_ctrl_tog 0x8004c00c table 848. hw_audioin_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsrvd3 dmawait_count rsrvd1 lr_swap edge_sync invert_1bit offset_enable hpf_enable word_length loopback fifo_underflow_irq fifo_overflow_irq fifo_error_irq_en run lradc0 (opt.) 0.1f microphone hw_audioin_micline _mic_resistor 2.5k 4.5k 8.5k adjustable voltage from 1.25 to 3 v with hw_audioin_micline_mic_bias lradc1 (opt.) hw_audioin_micline_mic_select 10f mic 2.2k figure 115. internal microphone bias generation free datasheet http:/// STMP36XX official product documentation 5/3/06 632 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 table 849. hw_audioin_ct rl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 audioin module soft reset. setting this bit to one forces a reset to portions of digfilt that control audio input and then gates th e clocks off because the clkgate bit's reset state is to disable clocks. this bit must be cleared to zero for normal operation. note that the clkgate bit does not affect sftrst, because it must remain writeable during clock gating. 30 clkgate rw 0x1 audioin clock gate enable. when this bit is set to 1, it gates off the clocks to the portions of the digfilt block that control only input audio functions. it does not affect portions of the block that control audioout. clear the bit to zero for normal audioin operation. note that when this bit is set, it remains writeable during clock gating so that it may be disabled by the user. 29:21 rsrvd3 ro 0x0 reserved 20:16 dmawait_count rw 0x0 dma request delay count. this bit field specifies the number of apbx clock cycles (0 to 31) to delay before each dma request. this field acts as a throttle on the bandwidth consumed by the digfilt block. this field can be loaded by the dma. 15:11 rsrvd1 ro 0x0 reserved 10 lr_swap rw 0x0 left/right input channel swap enable. setting this bit to one swaps the left and right serial audio inputs from the adc before being parallelized and having the sample rate converted by the audioin's cic block. 9 edge_sync rw 0x0 serial input clock edge sync select. this bit selects the edge of the adc's serial input clock upon which the cic-filter synchronizes fo r data receive. 0=rising edge. 1=falling edge 8 invert_1bit rw 0x0 invert serial audio input enable. when set, this bit inverts the 1-bit serial input of both left and right channels from the adc's sigma-delta modulator. 0=normal operation. 1=invert l/r serial audio input to the cic block. 7 offset_enable rw 0x1 adc analog high-pass filter offset calculation enable. when this bit is set, the adc's high pass filter actively adjusts the serial audio input, removing dc offset present within the signal. active dc offset only takes place when the hpf_enable bit is set. once dc offset has been achieved, this bit can be cleared to maintain a constant level of offset. after clearing this bit, the hpf_enable bit should remain set to maintain a constant dc offset. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 633 6 hpf_enable rw 0x1 adc high-pass filter enable. when this bit is set, the adc's analog high pass filter is enabled. once enabled, the offset_enable bit can be set to cause the filter to begin removing dc offset from the incoming serial analog data. once dc offset has been removed, the offset_enable bit should be cleared while the hpf_enabl e bit remains set. 5 word_length rw 0x0 pcm audio bit size select . this bit selects the size of the parallel pcm data collected by the audioin's input fifo. 0=32-bit pcm samples. 1=16 bit samples. note that the pcm audio data output from the fir filter stages is 24 bits. for 16-bit operation, the resultant data is normalized by dropping the least significant 8 bits. for 32-bit mode, the two's complement pcm data is sign extended to 32 bits. 4 loopback rw 0x0 audioout-to-audioin loopback enable. setting this bit to one connects the audioout's digital serial data from the sdm module to the audioin's serial digital input to the cic module, bypassing the analog dac and adc. this test mode provides a digital-only loopback which ties the output filter chain back to the input filter chain. this bit should be cleared to zero for normal operation. 3 fifo_underflow_irq rw 0x0 fifo underflow interrupt status bit. this bit is set by hardware if the audioin's fifo underflows any time during operation. it is reset by software by writing a one to the sct clear address space. an interrupt is issued to the host processor if this bit is set and fifo_error_irq_en=1. note that underflows should not occur by design because requests to the dma are not made unless there is data present within the fifo, and would indicate a serious dma error. 2 fifo_overflow_irq rw 0x0 fifo overflow interrupt status bit. this bit is set by hardware if the audioin's fifo overflows due to a dma request that is not serviced in time. it is reset by software writing a one to the sct clear address space. an interrupt is issued to the host processor if this bit is set and fifo_error_irq_en=1. 1 fifo_error_irq_en rw 0x0 fifo error interrupt enable. set this bit to one to enable an audioin interrupt request to the host processor when either the fifo overflow or underflow status bits are set. note that this bit does not affect the state of the underflow/overflow status bits, but rather their ability to signal an interrupt to the cpu. 0 run rw 0x0 audioin enable. setting this bit to one causes the audioin to begin converting data. once 8 words of audio input samples are collected in its fifo, it makes a dma service request. clearing this bit to zero stops data conversion and also causes the clkgate bit to be set. table 849. hw_audioin_ct rl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 634 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 description: the audioin control register contains bit fields used to control and monitor audioin operation including: reset, clocks, dma transfers, analog adc signal interface, high-pass filter operation, pc m data size, test, and interrupt control. example: hw_audioin_ctrl.run = 1; // start audioin conversion 25.6.2. audioin status register description the audioin status register is used to det ermine if the digital-to-analog converter is operational. hw_audioin_stat 0x8004c010 hw_audioin_stat_set 0x8004c014 hw_audioin_stat_clr 0x8004c018 hw_audioin_stat_tog 0x8004c01c description: the audioin status register provides an indication of the presence of the adc functionality. example: unsigned testvalue= hw_audioin_stat.adc_present; 25.6.3. audioin sample rate register description the audioin sample rate register is used to specify the sample rate from which the incoming serial audio data is converted as it is received by the cic module from the analog adc. hw_audioin_adcsrr 0x8004c020 hw_audioin_adcsrr_set 0x8004c024 hw_audioin_adcsrr_clr 0x8004c028 hw_audioin_adcsrr_tog 0x8004c02c table 850. hw_audioin_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 adc_present rsrvd3 table 851. hw_audioin_st at bit field descriptions bits label rw reset definition 31 adc_present ro 0x1 audioin functionality present. this status bit is set to one in products that include the audioin/adc. if this bit is zero, the audioin/adc is permanently disabled and cannot be operated by the user. 30:0 rsrvd3 ro 0x0 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 635 table 852. hw_audioin_adcsrr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 osr basemult rsrvd2 src_hold rsrvd1 src_int rsrvd0 src_frac table 853. hw_audioin_adcs rr bit field descriptions bits label rw reset definition 31 osr ro 0x0 audioin oversample rate. note that for the STMP36XX, the oversample rate is fixed at 6 mhz. osr6 = 0x0 audioin oversample rate at 6 mhz. osr12 = 0x1 audioin oversample rate at 12 mhz. 30:28 basemult rw 0x1 base sample rate multiplier. this bit field is used to configure the adc's sample rate to one of three ranges: single, double, or quad. this multiply factor is used to achieve sample rates greater than the standard rates of 32/44.1/48 khz. a value of 0x1 should be used when selecting half and quarter sample rates. note that sample rates greater than 48 khz may only be used when the audioout is disabled, and 44.1 khz is the maximum sample rate at which both the audioin and audioout can operate simultaneously. single_rate = 0x1 single-rate multiplier (for 48/44.1/32 khz as well as half and quarter rates). double_rate = 0x2 double-rate multiplier (for 96/88.2/64 khz). quad_rate = 0x4 quad-rate multiplier (for 192/176.4/128 khz). 27 rsrvd2 ro 0x0 reserved. always write a zero to this bit field. 26:24 src_hold rw 0x0 sample rate conversion hold factor. this bit is used to hold a sample of a variable number of clock cycles in order to generate half and quarter sample rates when dividing down the audioin's internal rate using the equation: output_sample_rate = (6x10^6 * basemult) / (src_int.src_frac * 8 * (src_hold + 1)). refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. 23:21 rsrvd1 ro 0x0 reserved. always write zeros to this bit field. 20:16 src_int rw 0x11 sample rate conversion integer factor. this bit field is the integer portion of a divide term used to sample- rate-convert the audioin's internal rate using the equation; output_sample_rate = (6x10^6 * basemult) / (src_int.src_frac * 8 * (src_hold + 1)). refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. free datasheet http:/// STMP36XX official product documentation 5/3/06 636 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 description: the audioin sample rate register contai ns bit fields used to specify the rate at which the adc samples incoming analog audio. example: // program the adc for a sample rate of 48 khz: hw_audioout_dacsrr.basemult = 0x1; // quad-rate hw_audioout_dacsrr.src_hold = 0x0; // 0 for full- double- quad-rates hw_audioout_dacsrr.src_int = 0xf; // 15 for the integer portion hw_audioout_dacsrr.src_frac = 0x13ff; // the fractional portion 25.6.4. audioin volume register description the audioin volume register is used to adjust the signal level of the recorded audio input from the adc. hw_audioin_adcvolume 0x8004c030 hw_audioin_adcvolume_set 0x8004c034 hw_audioin_adcvolume_clr 0x8004c038 hw_audioin_adcvolume_tog 0x8004c03c 15:13 rsrvd0 ro 0x0 reserved. always write zeros to this bit field. 12:0 src_frac rw 0x37 sample rate conversion fraction factor. this bit field is the fractional portion of a divide term used to sample-rate-convert the audioin's internal rate using the equation; output_sample_rate = (6x10^6 * basemult) / (src_int.src_frac * 8 * (src_hold + 1)). refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. table 854. hw_audioin_adcvolume 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd6 volume_update_left rsrvd5 en_zcd rsrvd4 volume_left rsrvd3 volume_update_right rsrvd2 rsrvd1 volume_right table 853. hw_audioin_adcs rr bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 637 table 855. hw_audioin_adcv olume bit field descriptions bits label rw reset definition 31:29 rsrvd6 ro 0x00 reserved 28 volume_update_left ro 0x1 left channel volume update pending. this bit is set to one by the hardware when an audioin volume update is pending, i.e., waiting on a zero crossing on the left channel. the bit is set following a write to the volume_left bit field and is cleared when the attenuation value is applied to the pcm input stream (at a zero-crossing). this status bit is not used when en_zcd=0. 27:26 rsrvd5 ro 0x00 reserved 25 en_zcd rw 0x0 enable zero cross detect. this bit enables/disables use of the zero cross detect circuit in the adc (rather than enabling the circuit itself). when enabled, changes to the volume bit fields are not applied until it is detected that the input signal's sign bit toggles (crosses zero amplitude). when disabled, changes to the volume bit fields take effect immediately when written. 24 rsrvd4 ro 0x0 reserved 23:16 volume_left rw 0xff left channel volume setting. this bit field is used to establish the incoming pcm audio signal strength during record. volume ranges from full scale -0.5db (0xfe) to -100db (0x37). each increment of this bit field causes a half db increase in volume. note that values 0x00-0x37 all produce the same attenuation level of -100db, and a value of 0xff is reserved. also note that the several bit fields exist for the analog adc that should be used to adjust the realitive gain of the input signal to the audioin block.volume_left and volume_right must be set to identical values whenever attenuation is changed. 15:13 rsrvd3 ro 0x00 reserved 12 volume_update_right ro 0x1 right channel volume update pending. this bit is set to one by the hardware when an audioin volume update is pending, i.e., waiting on a zero crossing on the right channel. the bit is set following a write to the volume_right bit field and is cleared when the attenuation value is applied to the pcm input stream (at a zero-crossing). this status bit is not used when en_zcd=0. 11:9 rsrvd2 ro 0x00 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 638 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 description: the audioin volume register allows volume control of the left and right channels. always program the volume_left and volu me_right bit fields to identical values whenever attenuation is changed . input audio can be attenuated in 0.5-db steps, from full scale down to a minimum of -100 db. this register is also used to enable/control volume updates such that they are only applied when pcm values cross zero to prevent unwanted audio artifacts. example: hw_audioin_adcvolume.u = 0x00ff00ff; maximum volume for left and right channels. 25.6.5. audioin debug register description the audioin debug register is used for testing and debugging the audioin block. hw_audioin_adcdebug 0x8004c040 hw_audioin_adcdebug_set 0x8004c044 hw_audioin_adcdebug_clr 0x8004c048 hw_audioin_adcdebug_tog 0x8004c04c 8 rsrvd1 ro 0x0 reserved 7:0 volume_right rw 0xff right channel volume setting. this bit field is used to establish the incoming pcm audio signal strength during record. volume ranges from full scale -0.5db (0xfe) to -100db (0x37). each increment of this bit field causes a half db increase in volume. note that values 0x00-0x37 all produce the same attenuation level of -100db, and a value of 0xff is reserved. also note that the several bit fields exist for the analog adc that should be used to adjust the realitive gain of the input signal to the audioin block. volume_right and volume_left must be set to identical values whenever attenuation is changed. table 855. hw_audioin_adcv olume bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 639 table 856. hw_audioin_adcdebug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 enable_adcdma rsrvd1 adc_dma_req_hand_shake_clk_cross set_interrupt3_hand_shake dma_preq fifo_status table 857. hw_audioin_adcde bug bit field descriptions bits label rw reset definition 31 enable_adcdma rw 0x0 audioin digital path test enable. this bit is used solely for development and debug and is not functional on production parts. when enabled, it causes the audioin's serial audio data input to bypass the cic block, to be assembled into 32-bit words and transferred out to memory using the audioout's dma channel 1. unlike lo opback, this test mode provides a means of verifying the digital portion of the audioin/adc logic without causing the audio data to pass through the audioout's fir filter stages. 30:4 rsrvd1 ro 0x00 reserved 3 adc_dma_req_hand_sha ke_clk_cross ro 0x0 dma request sync status. this bit reflects the current state of the second flop on the chain of three flip-flops used to synchronize the audioin's dma request signal from the module's internal 24-mhz clock to the apbx's memory clock domain. this bit is only intended for test. 2 set_interrupt3_hand_s hake ro 0x0 interrupt[3] status. this bit reflects the current state of the apbx interface state machi ne's internal interrupt[3] signal used to prioritize channels 0 and 1 dma requests from the digfilt. this bit is only intended for test. free datasheet http:/// STMP36XX official product documentation 5/3/06 640 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 description: the audioin debug register provides read-only access of various internal audioin module signals to assist in de bug and validation, as well as control of adcdma test mode. example: unsigned tempstatus = hw_audioin_adcdebug.fifo_status; 25.6.6. adc mux volume and select control register description this register controls operation of the analog adc input mux. hw_audioin_adcvol 0x8004c050 hw_audioin_adcvol_set 0x8004c054 hw_audioin_adcvol_clr 0x8004c058 hw_audioin_adcvol_tog 0x8004c05c 1 dma_preq ro 0x0 dma request status. this bit reflects the current state of the audioin's dma request signal. dma requests are issued any time the request signal toggles. this bit can be polled by software, in order to manually move samples from the audioin's fifo to a memory buffer when the audioin's dma channel is not used. 0 fifo_status ro 0x0 fifo status. this bit is set when the audioin's fifo contains any amount of valid data and is cleared when the fifo is empty. table 858. hw_audioin_adcvol 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 select_left rsrvd1 select_right rsrvd0 mute gain_left gain_right table 859. hw_audioin_adcv ol bit field descriptions bits label rw reset definition 31:30 rsrvd2 ro 0x0 reserved 29:28 select_left rw 0x0 adc left channel input source select. this bit field is used to select the analog input source of the adc's left channel. 00=microphone. 01=line1. 10=headphone. 11=line2 (169-bga only). line2 left input is lradc2. 27:26 rsrvd1 ro 0x0 reserved table 857. hw_audioin_adcde bug bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 641 description: this register supplies the volume, mute, and input select controls for the analog adc mux/gain amplifier. example: hw_audioin_adcvol.mute = 0; 25.6.7. microphone and line control register description this register provides the microphone and line control bits. hw_audioin_micline 0x8004c060 hw_audioin_micline_set 0x8004c064 hw_audioin_micline_clr 0x8004c068 hw_audioin_micline_tog 0x8004c06c 25:24 select_right rw 0x0 adc right channel input source select. this bit field is used to select the analog input source of the adc's right channel. 00=microphone. 01=line1. 10=headphone. 11=line2 (169-bga only). 23:9 rsrvd0 ro 0x0 reserved 8 mute rw 0x1 adc mute. when set, this bit mutes both the left and right channel analog inputs. 1=mute. 0=unmute. note that mute is always applied immediately when written (unlike volume when en_zcd=1), therefore the user should always ramp down the channel's volume to the minimum level (-100 db) before setting the mute bit. 7:4 gain_left rw 0x0 left channel adc gain. this bit selects the level of gain applied to the left channel analog input. each increment of this field represents a 1.5db gain. programming a value of 0x0, applies a 0db gain, 0x1 applies a 1.5db gain, and so on up to a maximum gain of 22.5db when a value of 0xf is used. 3:0 gain_right rw 0x0 right channel adc gain. this bit selects the level of gain applied to the right channel analog input. each increment of this field represents a 1.5-db gain. programming a value of 0x0, applies a 0-db gain, 0x1 applies a 1.5-db gain, and so on up to a maximum gain of 22.5 db when a value of 0xf is used. table 859. hw_audioin_adcv ol bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 642 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 table 860. hw_audioin_micline 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd6 atten_line divide_line1 divide_line2 rsrvd5 mic_select rsrvd4 mic_resistor rsrvd3 mic_bias rsrvd2 force_micamp_pwrup rsrvd1 mic_gain table 861. hw_audioin_micli ne bit field descriptions bits label rw reset definition 31 rsrvd6 ro 0x0 reserved 30 atten_line rw 0x0 attenuate line1 input. this bit is used to attenuate the line1 volume range down by >= 20 db. additionally, when this bit is set, the headphone volume intervals that are controlled by the vol_left and vol_right bit fields in the hw_audioout_hpvol register are increased (<= 3 db). this bit affects both the left and right channels. 29 divide_line1 rw 0x0 attenuate line1 input. when used in conjunction with a 10k series input resistor on the line1 pin, this bit causes the line1 input signal to be attenuated by 6db (+/-1.5 db) t o allow a 1-vrms input signal. this bit affects the left and right channels of both the adc and dac. 28 divide_line2 rw 0x0 attenuate line2 input. when used in conjunction with a 10k series input resistor on the line2 pin, this bit causes the line2 input signal to be attenuated by 6 db (+/-1.5 db) to allow a 1-vrms input signal. this bit affects the left and right channels of both the adc and dac. 27:25 rsrvd5 ro 0x0 reserved 24 mic_select rw 0x0 microphone bias pin select. when mic_resistor is enabled (non-zero), this bit is used to select the pin source for the micbias input voltage reference. 0=lradc0. 1=lradc1. note that the lradc pin that is selected for micbias cannot also be used as an lradc input. 23:22 rsrvd4 ro 0x0 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 643 description: this register provides the microphone and line control bits. example: hw_audioin_micline.mic_gain = 0x2; // 30 db 25.6.8. analog clock control register description this register provides analog clock control. hw_audioin_anaclkctrl 0x8004c070 hw_audioin_anaclkctrl_set 0x8004c074 hw_audioin_anaclkctrl_clr 0x8004c078 hw_audioin_anaclkctrl_tog 0x8004c07c 21:20 mic_resistor rw 0x0 microphone bias resistor select. note that the analog adc block must be powered on before turning on the micbias circuit (adc bit within the hw_audioout_pwrdn register must be cleared to zero) 00=off. 01=2.5 kohm. 10=4.5 kohm. 11=8.5 kohm. 19 rsrvd3 ro 0x0 reserved 18:16 mic_bias rw 0x0 microphone bias voltage select. 0=1.25 v, 1=1.50 v, up to 7=3.00 v (0.25-v increments) 15:9 rsrvd2 ro 0x00 reserved 8 force_micamp_pwrup rw 0x1 force adc microphone amplifier powerup. if the adc is powered down or is not set to the mic for its input, then clearing this bit forces the microphone amplifier to powerup. 7:2 rsrvd1 ro 0x00 reserved 1:0 mic_gain rw 0x0 microphone gain. 00=0 db, 01=20 db, 10=30 db, 11=40 db. table 862. hw_audioin_anaclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 clkgate rsrvd3 dither_enable slow_dither invert_adcclk rsrvd2 adcdiv table 861. hw_audioin_micli ne bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 644 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 description: this register provides analog clock control. example: hw_audioin_anaclkctrl.adcdiv = 0x2; // 3 mhz 25.6.9. audioin read data register description the audioin read data register provides access to incoming pcm audio sam- ples. hw_audioin_data 0x8004c080 hw_audioin_data_set 0x8004c084 hw_audioin_data_clr 0x8004c088 hw_audioin_data_tog 0x8004c08c table 863. hw_audioin_anaclkc trl bit field descriptions bits label rw reset definition 31 clkgate rw 0x1 analog clock gate. set th is bit to gate the clocks for the adc converter and associated digital filter. 30:7 rsrvd3 ro 0x0 reserved 6 dither_enable rw 0x0 adc dither enable. when this bit is set, dither is enabled within the adc. 5 slow_dither rw 0x0 slow dither. when dither is enabled (dither_enable=1), and this bit is set, adc input signal dithering is slowed to half its normal rate. 4 invert_adcclk rw 0x0 adc clock invert. set th is bit to invert the adc_clk for the adc sigma-delta converter and associated digital filters. 3 rsrvd2 ro 0x0 reserved 2:0 adcdiv rw 0x0 adc analog clock divider. this bit field is used to select the oversampling clock rate used by the adc. this bit field should only be changed per sigmatel. 000=6 mhz. 001=4 mhz. 010/100=3 mhz. 011/101=2 mhz. 110=1.5 mhz. 111=1 mhz. table 864. hw_audioin_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 high low free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 25: audioin/adc 645 description: the audioin read data register provides 32-bit data transfers for the dma, or, alternatively, can be directly read by the cpu. each data value read from the regis- ter is transferred from the audioin's fifo that contains the resultant audio data that has passed through it's digital fir f ilter stages. these 32-bit values contain either one 32-bit sample or two 16-bit samples, depending on how the data size is programmed. note that the pcm audio data output from the fir filter stages is 24- bit. for 16-bit operation, the resultant data is normalized by dropping the least signif- icant 8 bits. for 32-bit mode, the two's co mplement pcm data is sign extended to 32 bits. example: unsigned long testvalue= hw_audioin_data.u; // read a 32 bit value from the read data reg- ister in cpu diagnostic (non-dma) mode audioin xml revision: 1.54 table 865. hw_audioin_data bit field descriptions bits label rw reset definition 31:16 high ro 0x0000 right sample or sample high half-word. for 16-bit sample mode, this field contains the right channel sample. for 32-bit sample mode, this field contains the most significant 16 bits of the 32-bit sample (either left or right). 15:0 low ro 0x0000 left sample or sample low half-word. for 16-bit sample mode, this field contains the left channel sample. for 32-bit per sample mode, this field contains the least significant 16 bits of the 32-bit sample (either left or right). free datasheet http:/// STMP36XX official product documentation 5/3/06 646 chapter 25: audioin/adc 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 647 26. audioout/dac this chapter describes the audioout/dac module implemented on the STMP36XX, including dma, sample rate conversion, internal operation, reference control settings, and headphone amplifier operation. programmable registers are described in section 26.7 . 26.1. overview the STMP36XX features an audio playback path that consists of the audioout digital multi-stage fir filter, followed by a sigma-delta digital-to-analog converter (dac). pcm audio samples ar e transferred from a buffer in memory using the apbx bridge dma to the audioout?s fifo. sample pairs are processed by a three-stage finite impulse response filter. the resultant pcm samples are input to the sigma-delta modulation (sdm) block, where they are serialized, sample rate converted to the desired output rate, and output to the analog dac. the analog audio destination can be selected from one of three possible outputs: ? stereo headphone amplifier output ? stereo speaker amplifier output ? stereo line output the audioout module provides the following functions: ? 1-bit sigma-delta dac ? three stage upsampling fir filter: 33-tap (1:2), 11-tap (2:4), 7-tap (4:8), supporting conversion from quarter, half, full, double and quad sample rates that are multiples of the standard 32k, 44.1k, and 48k hz rates ? parallel-to-serial bi t-stream decimator ? sample rate converter (src) ? 16- or 32-bit pcm sample widths ? apbx bridge dma interface ? independent control of each channel?s volume (including mute) ? sigmatel 3d virtualization ? adc-to-dac internal loopback for product development ? control bit fields used for analog dac settings figure 116 shows a high-level diagram of the audioout module. see figure 111 on page 624 for a diagram of the audio path and control options. free datasheet http:/// STMP36XX official product documentation 5/3/06 648 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 26.2. operation audio data conversion begins by ei ther using the STMP36XX?s ahb-apbx bridge dma engine to write two?s complement pcm data to the audioout?s input fifo, or by writing the data directly to the audioout?s data register via the host cpu. the data is then normalized to 24-bit sample s and then filtered using a 3-stage fir filter, consisting of 33, 11, and 7 taps, respectively. the audioout contains a sequencer, multiply-accumulate hardware, and a set of filter coefficients that performs successive iterations on the da ta stored in ram. intermediate data calculated along the taps/stages of the fir are also stored in the audioout?s ram. the audioout module includes hardware for interpolation, sample and hold, and sigma-delta modulation that is applied to the filtered parallel pcm data. the resultant oversampled 1-bit serial stream is then output to the high-performance analog stereo sigma-delta dac. 24-mhz xtal osc. divide by n arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram dma request clock control dac digital filtering, interpolation, sample rate conversion, digital volume, zero cross detect to headphone, line or speaker out 1-bit digital-to-analog conversion dac programmable registers figure 116. audioout /dac block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 649 in most cases, the audioout?s pcm da ta is transferred by the ahb-apbx bridge dma. dma channel 1 is dedicated to the audioout module. the dma moves data to the audioout?s memory-mapped data register from a ram buffer every time a request is made. the buffer may be in on-chip or off-chip ram. it is also possible for the cpu to manually move data to the audioout data register while monitoring either the fifo or dma request status bits in the audioout debug register (hw_audioout_dacdebug). also present on the STMP36XX is an audio record path called audioin/adc. although each functions independently of one another, both the audioout and audioin blocks share their fir filter (sequencer/ram/coefficients) and dma con- troller. this combined module is titled the ?digital filter? or digfilt. the register descriptions that follow refer both to each path independently (audioout and audioin) as well as a whole (digfilt), due to the fact that clocks and resets affect either the shared resources or the design as a whole. in order to configure the audioout/dac for operation, the user must first clear the clock gate (clkgate) and soft reset (sftr st) bits within the audioout control register (hw_audioout_ctrl). the run bit should remain off (zero), while all other control bits are initialized. it is important to note that there are also a number of control bits within the audioout?s address space that control functions within the analog dac. next, the bridge dma contro ller channel 1 should be programmed and enabled to supply output audio samples from one or more ram buffers. finally, the run bit should be set to start audioout/dac operation. after the 8-word audioout fifo is fille d, conversion begins. each 32-bit register within the audioout?s address space is aliased to four adja- cent words. the first word is used for normal read-write access, while the subse- quent three words are contained within the register?s set-clear-toggle (sct) address space. only bits that are written to with a one in this space are affected. for exam- ple, writing a one to a bit using the regist er?s set address, sets that particular bit while maintaining the state of all other bits. this convention allows easy bit manipu- lation without requiring the standard read-m odify-write procedure. bits that are writ- ten with a one to the register?s clear address clear the bit, while the toggle address causes bits to invert their current state. 26.2.1. audioout dma the dma is typically controlled by a lin ked list of descripto rs. generally, the descriptors are circularly linked to cause the dma to cycle through the set of dma buffers. the dma can be programmed to assert an irq when some or all of the buffers have been transmitted. for example, audioout dma descriptor 0 may program the dma to transmit a buffer, set the done irq, and fetch descriptor 1. descriptor 1 programs the dma to transmit the next buffer. the dma continues to operate normally while the irq is assert ed. the cpu needs to respond to the irq before the dma has transmitted all of the buffers with new data. the dma isr clears the irq flag and prepares buffers and/or descriptors with new data. in general, software copies new data into the buffers or adjust the descriptors to point to existing buffers. software should also take advantage of the dma?s counting semaphore feature to synchronize the add ition of new descriptors to the chain. the dma can take pcm data from any memory-mapped location. for 32-bit pcm data, the left channel sample is stored fi rst in the lowest address, followed by the corresponding right channel sample in the next word address (+4 bytes). for 16-bit mode, sample pairs are stored in each word. right samples are stored in the upper free datasheet http:/// STMP36XX official product documentation 5/3/06 650 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 half word, while left samp les are stored in the lower half word. because the audioout always operates on stereo data, the pcm buffer should always have an integer number of words. it is not possible to play mono data unless the mono samples are each repeated twice in memory, once for the left channel and once for the right channel. the audio data values are in two?s complement format, where full scale values range from 0x7fffffff to 0x80000000 for 32-bit data or 0x7fff to 0x8000 for 16-bit data. in addition to the dma irq used for a udioout buffer refill, the audioout also has an underflow and overflow irq. over flows should never occur, because (by design) the dma should never attempt to write more data than there is space available within the audioout?s fifo. ho wever, if the dma does not keep up with requests and the fifo is emptied by th e audioout?s filter stages, an underflow occurs. this causes the underflow flag to be set in the audioout control register (hw_audioout_ctrl). if the overflow/underflow irq enabl e bit is set, then this condition also asserts an interrupt. the interrupt is cleared by writing a one to the underflow flag in the hw_audioout_ctrl?s sct clear address space. an audioout underflow is typically caused by the dma running out of new buffers, or if the ahb or apbx is stalled or is ot herwise unable to meet the bandwidth requirements at the current operating frequency. if the counting semaphore reaches 0, the dma stops processing new descriptors and stops moving data to the audioout?s data register (hw_audioout_data). in some cases, it may be desirable to synchronize the dac clock speed with some other reference. examples include a system playing from a network stream or digital fm receiver. in these cases, the audioout sample rate register can be adjusted to speed up or slow down the data rate. software needs to periodically monitor the buffer positions to make corrections as necessary. 26.3. dac sample rate conver ter and internal operation table 866 contains the required value of the hw_audioout_dacssr register for various common sample rates. although these are the standard rates, any sample rate from 8k to 192 khz can be programmed. table 866. bit field values for standard sample rates sample rate hw_audioout_dacssr fsample dac basemult src_hold src_int src_frac 192,000 hz 0x4 0x0 0x0f 0x13ff 176,400 hz 0x4 0x0 0x11 0x0037 128,000 hz 0x4 0x0 0x17 0x0e00 96,000 hz 0x2 0x0 0x0f 0x13ff 88,200 hz 0x2 0x0 0x11 0x0037 64,000 hz 0x2 0x0 0x17 0x0e00 48,000 hz 0x1 0x0 0x0f 0x13ff 44,100 hz 0x1 0x0 0x11 0x0037 32,000 hz 0x1 0x0 0x17 0x0e00 24,000 hz 0x1 0x1 0x0f 0x13ff 22,050 hz 0x1 0x1 0x11 0x0037 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 651 note: sample-rates greater than 48 khz can only be used when the audioin is disabled, and 44.1 khz is the maximum sample rate at which both the audioout and audioin can operate simultaneously. for any of the desired sample rates, a fractional sample-rate conversion factor is calculated within the digfilt according to the following equation srconv dac = 65536 * [ (fanalog dac )/ (8 * hold dac * fsample dac )] if computed with the above explicit operator precedence, the resulting sample-rate con- version factor (srconv dac ) will be a 24-bit scaled fixed-point representation of the desired decimation factor. the 1-bit sigma delta d/a converter is always sampled on a submultiple of the 24.0-mhz crystal oscilla tor frequency, as specif ied in the hw_ccr_dacdiv register (see figure 117 ). this divider generates sample strobes at fanalog dac where the divisors available come from the set {4,6,8,12,16,24}. with hw_ccr_dacdiv set to zero, to divide by 4, fanalog dac becomes 6.0 mhz for a 24.0-mhz crystal. the sample strobe derived fr om this divider is used to interpolate the 1-bit d/a values. the 1-bit sigma delta modulator is effectively running at fanalog dac . as shown in figure 117 , the 16-bit or 32-bit d/a values are extracted from on-chip ram via the dma. they are filtered to band-limit the audio stream. this filter runs on xtal_clk , but filters samples at the source sample rate, which is slower than the output d/a sample rate. in the process, this filter performs a fixed 1:8 interpolation or up-sample input stream. a single 24-bit sample at the output of the fixed filter is further interpolated up to the 1-bit d/a rate. the variable rate sample, hold and interpolate block performs this function. it stalls the filter pipeline and dma source , using the handshake lines that connect with the previous filter stage to supply sa mples at the correct over-sample ratio. the 1-bit dac runs at the fixed sample rate of fanalog dac while the dma fetches sam- ples in burst at irregular intervals to ma intain the required in put to the modulator. in this case, the 1-bit d/a is running at 6 mhz. the sample hold and interpolate block accepts a new sample from the filter at a (44.1 khz * 8) = 352.8 khz. it passes interpolated samples to the modulator at a 6.0-mhz rate. the sample, hold and interpolate block passes a source sample from the fixed 1:8 interpolation filter to the sigma delta modulator corresponding to every 8.503 fanalog dac samples. recall that this is a variable ra te interpolation stage that changes for every over sample rate (osr) setting in use. if the desired sample rate fsample dac = 44.1 khz, for example, the sample hold and interpolate block will accept samples from fixe d interpolation filter at 352.8 khz, i.e., 8x the desired sample rate. there is a handshake pair (request/ack) between the variable rate sample hold and interpolate block and the fixed interpolating filter block. this handshake is used to pace the samples from the fifo to 44.1 khz. 16,000 hz 0x1 0x1 0x17 0x0e00 12,000 hz 0x1 0x3 0x0f 0x13ff 11,025 hz 0x1 0x3 0x11 0x0037 8,000 hz 0x1 0x3 0x17 0x0e00 table 866. bit field values for standard sample rates (continued) free datasheet http:/// STMP36XX official product documentation 5/3/06 652 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 there are also members of the 48-khz family whose members satisfy the property: 24.576 mhz = q*fsample dac these sample rates include 48 khz, 32 khz, 24 khz, 16 khz, and 12 khz. there are also the members of the 44.1-khz family whose members satisfy the property: 16.9344 mhz = q*fsample adc where q comes from the set of integers. these sample rates include 44.1 khz, 22.05 khz, and 11.025 khz. the d/a converter block includes a variable rate or rational interpolator to accom- modate these sample rates, as shown in figure 117 . rational numbers in the dac are approximated with a scaled fixed-point 24-bit value. in this case, the decimal point falls between bit 15 and bit 16. ther efore, the lower two bytes hold the frac- tional part, while the upper byte holds the whole number portion of the scaled fixed point. the position register uses this scaled fixed-point representation for the num- ber of 1-bit samples to be interpolated (generated) to find the next sample to be sent to the sigma delta modulator. whenever the whole number part (bits 23:16) is zero, then the next dma sample is consumed. for playback at 44.1 khz, set the interpola- tor to generate 67.027 new interpolated samples between every dma sample. hw_dacsrr_sr 1-bit analog d/a xtal osc dac_lsamp da_div 24.0 mhz hw_ccr_dacdiv xtal_clk sigma delta modulator samp_strobe 31 position reg 16 15 1 1 samp_strobe pos_zero= (position_reg[23:16] == 8'h00) position_reg[31:0] + 24'hff0000 whole # fraction variable rate interpolator pos_zero frac[15:0] sample hold & interpolate l 1:8 fixed interp. filter handshake left channel from dma handshake 1-bit analog d/a dac_rsamp sigma delta modulator sample hold & interpolate r 1:8 fixed interp. filter handshake right channel from dma fanalog dac 8 x fsample dac 1 x fsample dac 3d effect 3d effect figure 117. stereo sigma delta d/a converter free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 653 26.4. reference control settings the reference control register allows adju stment of reference voltages and currents. vbg is the internal bandgap voltage (no external pin). this is a stable voltage refer- ence used to establish all other voltage and current references for the chip, includ- ing vag, vrefp, the li-ion charge termination voltage, etc. all the voltage and current references on the chip are proportional to vbg. vag is the analog ground voltage. it sets t he dc bias on the input and output of all of the audio pins. this is typically set near vdda/2. vag also affects the peak out- put swing of the dac. as vag is lowered, the output swing of the dac scales with it. however, at low vdda levels, the analog performance can be improved by set- ting vag somewhat below vdda/2. the dac is particularly susceptible to power supply noise if vdda-vag is not large enough. table 867 shows the simulated psrr at different vag settings when vdda=1.35v. the table includes typical and worst case results. table 867. simulated psrr for dac at 1.35 vdda vag code vag value tt 25c ss ?20c 1010 0.684 ?62 1001 0.664 ?77 1000 0.645 ?85 0111 0.625 ?85 ?36 0110 0.605 ?53 0101 0.586 ?60 free datasheet http:/// STMP36XX official product documentation 5/3/06 654 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 26.5. headphone the stm35xx supports a conventional stereo headphone drive, as shown in figure 118 . in addition, as shown in figure 119 ? figure 121 , the chip can generate an optional headphone common node circuit for the headphones that eliminates the need for the large and expensive dc blocking capa citors. it also improves the anti-pop per- formance. these benefits are obtained at a slight increase in power consumption, i.e., at 30 mv rms output, the resultant increase in power consumption is approxi- mately 2.7 mw. .01f 16 ? 220 f 61 hpr 16 ? 16 ? 220 f 65 hpl 16 ? headphones .01f 100 ? 100 ? figure 118. conventional stereo headphone application circuit .01f 16 ? 61 hpr 16 ? 65 hpl headphones 16 ? 16 ? .01f hp_vgnd 63 hp_sense 60 tie at headphone jack 100 ? 16 ? .01f 100 ? figure 119. stereo headphone application circuit with common node free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 655 headphone common hp amp short detect latch r s hw_audioout_anactrl_short_cm_sts irqa hw_audioout_anactrl_shortmode_cm == `01' hw_audioout_anactrl_shortmode_cm != `00' 1 0 1 0 hw_audioout_anactrl_shortmode_cm == `01' hw_audioout_anactrl_shortmode_cm != `11' hw_audioout_anactrl_shortmode_cm == `00' powerdown headphone amp figure 120. stereo headphone common short detection and powerdown circuit headphone common hp amp short detect latch r s hw_audioout_anac trl_short_lr_sts irqa hw_audioout_anactrl_shortmode_lr == `01' || hw_audioout_anactrl_shortmode_lr == `10' hw_audioout_anactrl_shortmode_lr != `00' 1 0 hw_audioout_anactrl_shortmode_lr != `01' hw_audioout_anactrl_shortmode_lr == `00' powerdown headphone amp figure 121. stereo headphone l/r/ short detection and powerdown circuit free datasheet http:/// STMP36XX official product documentation 5/3/06 656 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 26.5.1. board components the headphone amplifier output requires a few external resistors and capacitors. there is a series rc compensation network that helps to guara ntee the stability of the amplifier under all loading co nditions. there is also a 100 ? resistor to the head- phone ground, which has multiple functions: ? in cap mode operation (a dc blocking cap is present), the 100 ? resistor improves startup pop suppression. ? in capless mode operation (no dc blocking cap), the resistor avoids 60-hz hum into a powered speaker when the player is turned off. ? in capless and cap mode players, the 100 ? resistor minimizes the power-off signal feedthrough from line-in to headphone out. ? in powerdown mode, there is a 100k ? resistor between line-in and headphone out. the 100 ? load resistor keeps the powerdown feedthrough level at ?60 db. when the part is powered up, there is no signal path between line-in and headphone out, thus no bleedthrough. 26.5.2. capless mode operation the headphone amplifier is designed to work with or without a dc blocking cap. in capless mode, an amplifier is used to bias the headphone ground at the analog ground level (vag), which is typically near vdda/2. this avoids any dc signal across the output load. capless operation provides slight improv ement to psrr and low frequency perfor- mance. it slightly degrades snr and thd (approximately 1 db). the biggest advan- tage is the savings in cost and area by eliminating the large dc blocking caps. the biggest disadvantage is ex tra power consumption. the capless mode of operation doubles the power consumed in the headphone amps. at normal listening levels, this has a fairly small effect on battery life. but with a full scale sine wave, it can significantly reduce the battery life. with a sinusoidal signal, the headphone power consumption per channel with a 16 ? load is roughly: power=1mw + vpeak*vdda/ (16ohm * pi) (per channel) this number is doubled in capless mode. however, normal music files have a much higher peak-to-average ratio than a sinu- soid. a par of 10 is typical in a music file, compared to a par of 1.414 for a sinu- soid. so headphone power for a normal music file is: power=1mw + vpeak*vdda*2.8mw (per channel) again, this number is doubled in capless mode. 26.6. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 657 26.7. programmable registers the following registers provide control for programmable elements of the audioout/dac block. 26.7.1. audioout control register description the audioout control register provides over all control of the digital portion of the digital-to-analog converter. hw_audioout_ctrl 0x80048000 hw_audioout_ctrl_set 0x80048004 hw_audioout_ctrl_clr 0x80048008 hw_audioout_ctrl_tog 0x8004800c table 868. hw_audioout_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsrvd4 dmawait_count rsrvd3 lr_swap edge_sync invert_1bit rsrvd2 ss3d_effect rsrvd1 word_length dac_zero_enable loopback fifo_underflow_irq fifo_overflow_irq fifo_error_irq_en run table 869. hw_audioout_ctrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 audioout module soft reset. setting this bit to one forces a reset to portions of digfilt that control audio output and then gates the clocks off since the clkgate bit's reset state is to disable clocks. this bit must be cleared to zero for normal operation. note that the clkgate bit does not affect sftrst since it must remain writeable during clock gating. a note is included in the bit field descriptions below for those bits that are not affected by the audioout's soft reset bit. these bits either control audioin or both audioin and audioout functions. 30 clkgate rw 0x1 audioout clock gate enable. when this bit is set to 1, it gates off the clocks to the portions of the digfilt block that control only output audio functions. it does not affect portions of the block that control audioin. clear this bit to zero for normal audioout operation. note that when this bit is set, it remains writeable during clock gating so that it may be disabled by the user. 29:21 rsrvd4 ro 0x0 reserved. always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 658 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 20:16 dmawait_count rw 0x0 dma request delay count. this bit field specifies the number of apbx clock cycles (0 to 31) to delay before each dma request. this field acts as a throttle on the bandwidth consumed by the digfilt block. this field can be loaded by the dma. 15 rsrvd3 ro 0x0 reserved. always write zeroes to this bit field. 14 lr_swap rw 0x0 left/right output channel swap enable. setting this bit to one swaps the left and right serial audio outputs from the sdm block to the analog dac . 13 edge_sync rw 0x0 serial output clock edge sync select. this bit selects the edge of the dac's serial output clock upon which the sdm synchronize s for data transmit. 0=rising edge. 1=falling edge. 12 invert_1bit rw 0x0 invert serial audio output enable. when set, this bit inverts the 1-bit serial output of both the left and right channels to the dac's sigma-delta modulator. 0=normal operation. 1=invert l/r serial audio output from the sdm block. 11:10 rsrvd2 ro 0x0 reserved. always write zeroes to this bit field. 9:8 ss3d_effect rw 0x0 virtual 3d effect enable. this bit field provides a virtual 3d effect for a two channel system by subtracting a portion of the opposite channel's content for each channel. three reduction ratios are available (db value represents amount of opposite channel content subtracted). 00=off 01=low (3 db) 10=medium (4.5 db) 11=high (6 db) 7 rsrvd1 ro 0x0 reserved. always write zeroes to this bit field. 6 word_length rw 0x0 pcm audio bit size select . this bit selects the size of the parallel pcm data that is input to the audioout's fifo. 0=32-bit pcm samples. 1=16-bit samples. note that the pcm audio data input to the fir filter stages is 24 bit. for 16-bit operation, the data is first sign- extended to 24 bits. for 32-bit operation, the data is first normalized by dropping the least significant 8 bits. 5 dac_zero_enable rw 0x0 quiet output enable. when enabled, this bit causes the audioout's sdm block to transmit alternating ones and zeros (...010101...). this function is used for pop-suppression while the audioout is reconfigured and during periods when the modulator would othewise transmit zeros. note that this function continues to operate when audioout is clock-gated. also note that the user must enable/disable this function while the audioout is not clock-gated. this bit is reset by a power-on reset only. table 869. hw_audioout_ctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 659 description: the audioout control register contains bit fields used to control and monitor audioout operation including: reset, cl ocks, dma transfers, data to the analog dac module, pcm data size, test, and inte rrupt control. example: hw_audioout_ctrl.run = 1; // start dac conversion 26.7.2. audioout status register description the audioout status register is used to determine if the digital-to-analog con- verter is operational. hw_audioout_stat 0x80048010 hw_audioout_stat_set 0x80048014 hw_audioout_stat_clr 0x80048018 4 loopback rw 0x0 audioin-to-audioout loopback enable. setting this bit to one routes the audio data received by the audioin's fifo to the audioout's fifo. this test mode provides a loopback that does not use the digfilt's dma memory inteface. this bit should be cleared to zero for normal operation. 3 fifo_underflow_irq rw 0x0 fifo underflow interrupt status bit. this bit is set by hardware if the audioout's fifo underflows any time during operation due to a dma request that is not serviced in time. it is reset by software by writing a one to the corresponding bit in the hw_audioout_ctrl_clr register. an interrupt is issued to the host processor if this bit is set and fifo_error_irq_en=1. 2 fifo_overflow_irq rw 0x0 fifo overflow interrupt status bit. this bit is set by hardware if the audioout's fifo overflows. it is reset by software by writing a one to the corresponding bit in the hw_audioout_ctrl_clr register. an interrupt is issued to the host processor if this bit is set, and fifo_error_irq_en=1. note that overflows should not occur by design since requests to the dma are not made unless there is adequate space present within the fifo. therefore, this condition would indicate a serious dma error. 1 fifo_error_irq_en rw 0x0 fifo error interrupt enable. set this bit to one to enable an audioout interrupt request to the host processor when either the fifo overflow or underflow status bits are set. note that this bit does not affect the state of the underflow/overflow status bits, but rather their ability to signal an interrupt to the cpu. 0 run rw 0x0 audioout enable. setting this bit to one causes audioout operation to start, beginning with a dma request to fill its 8-word fifo. clearing this bit to zero stops data conversion and also causes the clkgate bit to be set. table 869. hw_audioout_ctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 660 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 hw_audioout_stat_tog 0x8004801c description: the audioout status register provides an indication of the presence of the dac functionality. example: unsigned statusvalue = hw_audioout_stat.dac_present; 26.7.3. audioout sample rate register description the audioout sample rate register is us ed to specify the sample rate that the parallel pcm audio data is converted to within the sdm module before being output to the analog dac. hw_audioout_dacsrr 0x80048020 hw_audioout_dacsrr_set 0x80048024 hw_audioout_dacsrr_clr 0x80048028 hw_audioout_dacsrr_tog 0x8004802c table 870. hw_audioout_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dac_present rsrvd1 table 871. hw_audioout_stat bit field descriptions bits label rw reset definition 31 dac_present ro 0x1 audioout functionality present. this status bit is set to one in products that include the audioout/dac. if this bit is zero, the audioout/dac is permanently disabled and cannot be operated by the user. 30:0 rsrvd1 ro 0x0 reserved. always write zeroes to this bit field. table 872. hw_audioout_dacsrr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 osr basemult rsrvd2 src_hold rsrvd1 src_int rsrvd0 src_frac free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 661 description: the audioout sample rate register provides a number of bit fields to direct the sdm module's hardware to sample-rate-conv ert the audio stream output to one of a table 873. hw_audioout_dacsrr bit field descriptions bits label rw reset definition 31 osr ro 0x0 audioout oversample rate. note that for the STMP36XX, the oversample rate is fixed at 6 mhz. osr6 = 0x0 audioout oversample rate at 6 mhz. osr12 = 0x1 audioout oversample rate at 12 mhz. 30:28 basemult rw 0x1 base sample rate multiplier. this bit field is used to configure the dac's sample rate to one of three ranges: single, double, or quad. this multiply factor is used to achieve sample rates greater than the standard rates of 32/44.1/48 khz. a value of 0x1 should be used when selecting half and quarter sample rates. note that sample rates greater than 48 khz may only be used when the audioin is disabled, and 44.1 khz is the maximum sample rate at which both the audioin and audioout can operate simultaneously. single_rate = 0x1 single rate multiplier (for 48/44.1/32 khz as well as half and quarter rates). double_rate = 0x2 double rate multiplier (for 96/88.2/64 khz). quad_rate = 0x4 quad rate multiplier (for 192/176.4/128 khz). 27 rsrvd2 ro 0x0 reserved. always write a zero to this bit field. 26:24 src_hold rw 0x0 sample rate conversion hold factor. this bit is used to hold a sample of a vari able number of clock cycles in order to generate half and quarter sample rates when dividing down the audioout's internal rate using the equation: output_sample_rate = (6x10^6 * basemult) / (src_int.src_frac * 8 * (src_hold + 1)). refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. 23:21 rsrvd1 ro 0x0 reserved. always write zeros to this bit field. 20:16 src_int rw 0x11 sample rate conversion integer factor. this bit field is the integer portion of a divide term used to sample rate convert the audioout's internal rate using the equation: output_sample_rate = (6x10^6 * basemult) / (src_int.src_frac * 8 * (src_hold + 1)). refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. 15:13 rsrvd0 ro 0x0 reserved. always write zeros to this bit field. 12:0 src_frac rw 0x37 sample rate conversion fraction factor. this bit field is the fractional portion of a divide term used to sample rate convert the audioout's internal rate using the equation: output_sample_rate = (6x10^6 * basemult) / (src_int.src_frac * 8 * (src_hold + 1)). refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. free datasheet http:/// STMP36XX official product documentation 5/3/06 662 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 number of common sample rates. note that these values can also be dynamically altered in small amounts in order to track variations in the outgoing audio stream from sources such as fm digital radio. example: // program the dac to output a sample rate of 48 khz: hw_audioout_dacsrr.basemult = 0x1; // quad-rate hw_audioout_dacsrr.src_hold = 0x0; // 0 for full- double- quad-rates hw_audioout_dacsrr.src_int = 0xf; // 15 for the integer portion hw_audioout_dacsrr.src_frac = 0x13ff; // the fractional portion 26.7.4. audioout volume register description the audioout volume register is used to adjust the signal level of the playback audio output to the dac. hw_audioout_dacvolume 0x80048030 hw_audioout_dacvolume_set 0x80048034 hw_audioout_dacvolume_clr 0x80048038 hw_audioout_dacvolume_tog 0x8004803c table 874. hw_audioout_dacvolume 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 volume_update_left rsrvd3 en_zcd mute_left volume_left rsrvd2 volume_update_right rsrvd1 mute_right volume_right table 875. hw_audioout_dacvo lume bit field descriptions bits label rw reset definition 31:29 rsrvd4 ro 0x00 reserved. always write zeroes to this bit field. 28 volume_update_left ro 0x0 left channel volume update pending. this bit is set to one by the hardware when an audioout volume update is pending, i.e., waiting on a zero crossing on the left channel. the bit is set following a write to the volume_left bit field and is cleared when the attenuation value is applied to the pcm output stream (at a zero-crossing). this status bit is not used when en_zcd=0. 27:26 rsrvd3 ro 0x00 reserved. always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 663 description: 25 en_zcd rw 0x0 enable zero cross detect. this bit enables/disables use of the zero cross detect circuit in the dac (rather than enabling the circuit itself). when enabled, changes to the volume bit fields are not applied until it is detected that the output signal's sign bit toggles (crosses zero amplitude). when disabled, changes to the volume bit fields take effect immediately when written. 24 mute_left rw 0x1 mute left channel. 0=unmute, 1=mute. note that mute is always applied immediately when written (unlike volume when en_zcd=1). the channel volume should always be ramped down to the minimum level (-100db) before setting the mute bit. 23:16 volume_left rw 0xff left channel volume setting. this bit field is used to establish the outgoing pcm audio signal strength during playback. volume ranges from full scale -0.5db (0xfe) to -100db (0x37). each increment of this bit field causes a half-db increase in volume. note that values 0x00-0x37 all produce the same attenuation level of -100db, and a value of 0xff is reserved. also note that the several bit fields exist for the analog dac that should be used to adjust the realitive gain of the output signal from the audioout block. 15:13 rsrvd2 ro 0x00 reserved. always write zeroes to this bit field. 12 volume_update_right ro 0x0 right channel volume update pending. this bit is set to one by the hardware when an audioout volume update is pending, i.e., waiting on a zero crossing on the right channel. the bit is set following a write to the volume_right bit field and is cleared when the attenuation value is applied to the pcm output stream (at a zero-crossing). this status bit is not used when en_zcd=0. 11:9 rsrvd1 ro 0x00 reserved. always write zeroes to this bit field. 8 mute_right rw 0x1 mute right channel. 0=unmute, 1=mute. note that mute is always applied immediately when written (unlike volume when en_zcd=1), therefore the user should always ramp down the channel's volume to the minimum level (-100 db) before setting the mute bit. 7:0 volume_right rw 0xff right channel volume setting. this bit field is used to establish the outgoing pcm audio signal strength during playback. volume ranges from full scale -0.5db (0xfe) to -100db (0x37). each increment of this bit field causes a half-db increase in volume. note that values 0x00-0x37 all produce the same attenuation level of -100db, and a value of 0xff is reserved. also note that the several bit fields exist for the analog dac that should be used to adjust the realitive gain of the output signal from the audioout block. table 875. hw_audioout_dacvo lume bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 664 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 the audioout volume register allows independent volume and mute control of the left and right channels. output audio can be attenuated in 0.5-db steps, from full-scale down to a minimum of -100 db. this register is also used to enable/control volume updates such that they are only applied when pcm values cross zero to pre- vent unwanted audio artifacts. example: hw_audioout_dacvolume.u = 0x01ff01ff; // mute both left and right channels hw_audioout_dacvolume.u = 0x00ff00ff; // maximum volume for left and right channels. 26.7.5. audioout debug register description the audioout debug register is used for test and debug of the audioout block. hw_audioout_dacdebug 0x80048040 hw_audioout_dacdebug_set 0x80048044 hw_audioout_dacdebug_clr 0x80048048 hw_audioout_dacdebug_tog 0x8004804c table 876. hw_audioout_dacdebug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 enable_dacdma rsrvd1 set_interrupt1_clk_cross set_interrupt0_clk_cross set_interrupt1_hand_shake set_interrupt0_hand_shake dma_preq fifo_status table 877. hw_audioout_dac debug bit field descriptions bits label rw reset definition 31 enable_dacdma rw 0x0 audioout digital path test enable. this bit is used solely for development and debugging, and is not functional on production parts. when enabled, it causes the audioiout's serial audio data output to bypass the dac analog block, to be assembled into 32-bit words and transferred out to memory using the audioin's dma channel 0. unlike loopback, this test mode provides a means of verifying the digital portion of the audiooout logic without causing the audio data to pass through the audioin's fir filter stages. 30:6 rsrvd1 ro 0x00 reserved. always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 665 description: the audioout debug register provides read-only access of various internal audioout module signals to assist in de bug and validation, as well as control of dacdma test mode. example: unsigned tempstatus = hw_audioout_dacdebug.fifo_status; 26.7.6. headphone volume and select control register description the headphone volume and select control register provides volume, mute, and input select controls for the headphone. hw_audioout_hpvol 0x80048050 hw_audioout_hpvol_set 0x80048054 hw_audioout_hpvol_clr 0x80048058 hw_audioout_hpvol_tog 0x8004805c 5 set_interrupt1_clk_cr oss ro 0x0 interrupt[1] sync status. this bit reflects the current state of the second flop on the chain of three flip-flops used to synchronize the audioout's interrupt[1] signal used to prioritize channels 0 and 1 dma requests from the digfilt. this signal is synchronized from the module's internal 24-mhz clock to the apbx's memory clock domain. this bit is intended for test only. 4 set_interrupt0_clk_cr oss ro 0x0 interrupt[0] sync status. this bit reflects the current state of the second flop on the chain of three flip-flops used to synchronize the audioout's interrupt[0] signal used to prioritize channel 0 and 1 dma requests from the digfilt. this signal is synchronized from the module's internal 24-mhz clock to the apbx's memory clock domain. this bit is intended for test only. 3 set_interrupt1_hand_s hake ro 0x0 interrupt[1] status. this bit reflects the current state of the apbx interface state machine's internal interrupt[1] signal used to prioritize channel 0 and 1 dma requests from the digfilt. this bit is intended for test only. 2 set_interrupt0_hand_s hake ro 0x0 interrupt[0] status. this bit reflects the current state of the apbx interface state machine's internal interrupt[0] signal used to prioritize channel 0 and 1 dma requests from the digfilt. this bit is intended for test only. 1 dma_preq ro 0x0 dma request status. this bit reflects the current state of the audioout's dma request signal. dma requests are issued any time the request signal toggles. this bit can be polled by software, in order to manually move samples to the audioout's fifo from a memory buffer when the audioout's dma channel is not used. 0 fifo_status ro 0x1 fifo status. this bit is set by hardware when the audioout's fifo contains any empty entries and is cleared when the fifo is full. table 877. hw_audioout_dac debug bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 666 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 description: this register provides volume, mute, and input select controls for the headphone. example: hw_audioout_hpvol.mute = 0; 26.7.7. speaker volume control register description this register provides volume and mute controls for the speaker. hw_audioout_spkrvol 0x80048060 hw_audioout_spkrvol_set 0x80048064 hw_audioout_spkrvol_clr 0x80048068 hw_audioout_spkrvol_tog 0x8004806c table 878. hw_audioout_hpvol 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 select rsrvd3 mute rsrvd2 vol_left rsrvd1 vol_right table 879. hw_audioout_hpvol bit field descriptions bits label rw reset definition 31:26 rsrvd4 ro 0x00 reserved. always write zeroes to this bit field. 25:24 select rw 0x0 master output select. 00=stereo dac. 01=stereo line1. 10=mono dac (from left dac). 11=invalid. it is reset by a power-on reset only. 23:17 rsrvd3 ro 0x00 reserved. always write zeroes to this bit field. 16 mute rw 0x1 headphone mute. it is reset by a power-on reset only. 15:13 rsrvd2 ro 0x00 reserved. always write zeroes to this bit field. 12:8 vol_left rw 0x03 left headphone gain control. this bit field controls headphone gain. each decrement represents a 2-db step. +6 db max volume in dac mode. +12 db max volume in linein mode. it is reset by a power-on reset only. 7:5 rsrvd1 ro 0x00 reserved. always write zeroes to this bit field. 4:0 vol_right rw 0x03 headphone right volume control. 2-db volume steps. +6 db max volume in dac mode. +12 db max volume in linein mode. it is reset by a power-on reset only. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 667 description: this register provides the volume and mute controls for the speaker. example: hw_audioout_spkrvol.mute = 0; 26.7.8. audio power-down control register description the audio power-down control register provides all power-down control bits. hw_audioout_pwrdn 0x80048070 hw_audioout_pwrdn_set 0x80048074 hw_audioout_pwrdn_clr 0x80048078 hw_audioout_pwrdn_tog 0x8004807c table 880. hw_audioout_spkrvol 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 mute rsrvd1 vol table 881. hw_audioout_spk rvol bit field descriptions bits label rw reset definition 31:17 rsrvd2 ro 0x00 reserved. always write zeroes to this bit field. 16 mute rw 0x1 speaker mute. it is reset by a power-on reset only. 15:4 rsrvd1 ro 0x00 reserved. always write zeroes to this bit field. 3:0 vol rw 0x3 speaker volume control. 2-db volume steps. +12 db max volume. default = +6 db. speaker input is always right dac. it is reset by a power-on reset only. table 882. hw_audioout_pwrdn 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd7 speaker rsrvd6 selfbias rsrvd5 right_adc rsrvd4 dac rsrvd3 adc rsrvd2 capless rsrvd1 headphone table 883. hw_audioout_pwr dn bit field descriptions bits label rw reset definition 31:25 rsrvd7 ro 0x00 reserved. always write zeroes to this bit field. 24 speaker rw 0x1 speaker power-down. it is reset by a power-on reset only. 23:21 rsrvd6 ro 0x00 reserved. always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 668 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 description: the audio power-down register provides control to power-down sections of the audio analog circuit. example: hw_audioout_pwrdn.dac = 0; 26.7.9. audioout reference c ontrol register description this register provides the voltage and current reference control bits. hw_audioout_refctrl 0x80048080 hw_audioout_refctrl_set 0x80048084 hw_audioout_refctrl_clr 0x80048088 hw_audioout_refctrl_tog 0x8004808c 20 selfbias rw 0x0 powers down the self -bias circuit. the reference uses a self-bias circuit during power-up that can be turned off with this bit. it is reset by a power-on reset only. 19:17 rsrvd5 ro 0x00 reserved. always write zeroes to this bit field. 16 right_adc rw 0x0 right adc power down. when enabled, powers down the adc's right channel while allowing the left to function normally (mono). note that, although this bit is located in the dac address space, it is an adc function and is reset by the adc sftrst bit. 15:13 rsrvd4 ro 0x00 reserved. always write zeroes to this bit field. 12 dac rw 0x1 power down dac analog circuitry. it is reset by a power-on reset only. 11:9 rsrvd3 ro 0x00 reserved. always write zeroes to this bit field. 8 adc rw 0x1 power down adc and input mux circuitry. note that, although this bit is located in the dac address space, it is an adc function and is reset by the adc sftrst bit. 7:5 rsrvd2 ro 0x00 reserved. always write zeroes to this bit field. 4 capless rw 0x1 power down headphone common amplifier used in capless headphone. if this bit is high, then the capless circuit is powered down and the device is either off or operating in cap mode ( ac-coupled). if the bit it low, then the device is on and in capless mode (dc- coupled). this bit field is reset by a power-on reset only. 3:1 rsrvd1 ro 0x00 reserved. always write zeroes to this bit field. 0 headphone rw 0x1 master (headphone) power down. it is reset by a power-on reset only. table 883. hw_audioout_pwr dn bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 669 table 884. hw_audioout_refctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 xtal_bgr_bias rsrvd3 vbg_adj low_pwr lw_ref bias_ctrl rsrvd2 adj_adc adj_vag adc_refval vag_val rsrvd1 dac_adj table 885. hw_audioout_refctrl bit field descriptions bits label rw reset definition 31:25 rsrvd4 ro 0x00 reserved. always write zeroes to this bit field. 24 xtal_bgr_bias rw 0x0 switch the xtal bias from self-bias to bandgap- based bias current. also switches the source of the xtal supply in series aa or liion to core supply to save power. note that while this bit is located in the dac address space, since it controls both dac and adc functions, it is not reset by the dac's sftrst bit. it is reset by a power-on reset only. 23 rsrvd3 ro 0x0 reserved. always write zeroes to this bit field. 22:20 vbg_adj rw 0x0 small adjustment for vbg value. will affect all reference voltages. expected to be used to tweak final li-ion charge voltage. 000=nominal. 001=+0.25%. 010=+0.5%. 011=0.75%. 100=-0.25%. 101=-0.5%. 110=-0.75%. 111=-1.0%. note that, while this bit is located in the dac address space, since it controls both dac and adc functions, it is not reset by the audioout's sftrst bit. it is reset by a power-on reset only. 19 low_pwr rw 0x0 lowers power (~100 ua) in the bandgap amplifier. this mode is useful in usb suspend or standby when bandgap accuracy is not critical. note that while this bit is located in the audioout address space, since it controls both dac and adc functions, it is not reset by the audioout's sftrst bit. it is reset by a power-on reset only. 18 lw_ref rw 0x0 lowers adc and vag reference voltages in 11:8 and 7:4 by ~22%. this bit must be set if vdda is <1.7 v. otherwise, vag and adc reference psrr will be poor. note that, while this bit is located in the audioout address space, since it controls both dac and adc functions, it is not reset by the audioout's sftrst bit. it is reset by a power-on reset only. free datasheet http:/// STMP36XX official product documentation 5/3/06 670 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 description: the audioout reference control register provides control over the voltage and power for the audio analog circuits. 17:16 bias_ctrl rw 0x0 bias current contro l for all analog blocks: 00=nominal. 01=-20%. 10=-10%. 11=+10%. note that, while this bit is located in the audioout address space, since it controls both dac and adc functions, it is not reset by the audioout's sftrst bit. it is reset by a power-on reset only. warning: adjusting the bias current also changes the lradc max voltage reference level. these bits should only be used for test/debug, and not in an application. 15:14 rsrvd2 ro 0x0 reserved. always write zeroes to this bit field. 13 adj_adc rw 0x0 adc reference voltage adjust. when cleared, analog adc reference is 1.5 v. when set, adc reference is controlled by adcrefval. the adj_adc bit should be cleared when the adc/audioin is not in use (improves dac snr). when the adc and dac are both enabled, the adj_adc bit must be set or the vag and adc references will interfere with each other and degrade snr. note that, although this bit is located in the dac address space, it is an adc function and is reset by the adc sftrst bit. 12 adj_vag rw 0x0 when cleared, vag is vdd/2 (resistor divider). when set, vag is controlled by vagval 7:4. note that, while this bit is located in the audioout address space, since it controls both dac and adc functions, it is not reset by the audioout sftrst bit. it is reset by a power-on reset only. 11:8 adc_refval rw 0x0 adc reference value (when adjadc set): f=1.60 v. 0=1.225 v, 25-mv steps, also affected by lwref. note that, although this bit is located in the dac address space, it is an adc function and is reset by the adc sftrst bit. 7:4 vag_val rw 0x0 vag reference value (when adjvag set): f=1.00 v, 0=0.625 v, 25-mv steps, also affected by lwref. see section on selecting the vag level earlier in this chapter. note that, while this bit is located in the audioout address space, since it controls both dac and adc functions, it is not reset by the audioout's sftrst bit. it is reset by a power-on reset only. 3 rsrvd1 ro 0x0 reserved. always write zeroes to this bit field. 2:0 dac_adj rw 0x0 adjusts the reference current (signal swing) in the dac : 000=nominal. 001=+0.25 db. 010=+0.5 db. 011=+0.75 db. 100==-0.25 db. 101=-0.5 db. 110=- 0.75 db. 111=-1.0 db. it is reset by a power-on reset only. table 885. hw_audioout_refctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 671 example: hw_audioout_refctrl.adj_vag = 1; 26.7.10. miscellaneous audio controls register description this register provides miscellenous audio control bits. hw_audioout_anactrl 0x80048090 hw_audioout_anactrl_set 0x80048094 hw_audioout_anactrl_clr 0x80048098 hw_audioout_anactrl_tog 0x8004809c table 886. hw_audioout_anactrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd8 short_cm_sts rsrvd7 short_lr_sts rsrvd6 shortmode_cm rsrvd5 shortmode_lr rsrvd4 short_lvladjl rsrvd3 short_lvladjr rsrvd2 hp_hold_gnd hp_classab rsrvd1 en_spkr_zcd zcd_selectadc en_zcd table 887. hw_audioout_anact rl bit field descriptions bits label rw reset definition 31:29 rsrvd8 ro 0x00 reserved. always write zeroes to this bit field. it is reset by a power-on reset only. 28 short_cm_sts rw 0x0 status of common mode amplifier short detection: 0=no short. to clear this interrupt and then rearm it: (1) set hw_audioout_anactrl_shortmode_cm to 00. (2) clear this bit. (3) set hw_audioout_anactr l_shortmode_cm to 01. there are two sets of edge-triggered latches in this path. all three steps must be executed to rearm the short detect. note that this interrupt is non-maskable within the audioout block. 27:25 rsrvd7 ro 0x0 reserved. always write zeroes to this bit field. 24 short_lr_sts rw 0x0 status of headphone amplifier short detection: 0=no short. to clear this interrupt and then rearm it: (1) set hw_audioout_anactr l_shortmode_lr to 00. (2) clear this bit. (3) set hw_audioout_anactr l_shortmode_lr to 01. there are two sets of edge-triggered latches in this path. all three steps must be executed to rearm the short detect. note that this interrupt is non-maskable within the audioout block. 23:22 rsrvd6 ro 0x0 reserved. always write zeroes to this bit field. free datasheet http:/// STMP36XX official product documentation 5/3/06 672 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 21:20 shortmode_cm rw 0x0 headphone common mode amplifier short control mode. 00=reset analog latch, hw power down on unlatched short signal. 01=latch short signal. hw power down on latched signal. 10=do not use. 11=do not use. 19 rsrvd5 ro 0x00 reserved. always write zeroes to this bit field. 18:17 shortmode_lr rw 0x0 headphone left and right channel short control mode. 00=reset analog latch, hw power-down disabled. 01=latch short signal, hw power-down enabled. 10=do not use. 11=do not use. 16:15 rsrvd4 ro 0x0 reserved. always write zeroes to this bit field. 14:12 short_lvladjl rw 0x0 adjust the left headphone current short detect trip point: 000=nominal. 001=-25%. 010=-50%. 011=-75%. 100=+25%. 101=+50%. 110=+75%. 111=+100%. it is reset by a power-on reset only. 11 rsrvd3 ro 0x0 reserved. always write zeroes to this bit field. 10:8 short_lvladjr rw 0x0 adjust the right headphone current short detect trip point: 000=nominal. 001=-25%. 010=-50%. 011=-75%. 100=+25%. 101=+50%. 110=+75%. 111=+100%. it is reset by a power-on reset only. 7:6 rsrvd2 ro 0x0 reserved. always write zeroes to this bit field. 5 hp_hold_gnd rw 0x0 hold headphone output to ground (used for power- up/power-down procedures). it is reset by a power-on reset only. 4 hp_classab rw 0x0 default is 0 (classa mode). classa mode can be useful for power-up/power-down and short handling. this bit should be set (classab mode) before starting audio signal. it is reset by a power-on reset only. 3 rsrvd1 ro 0x0 reserved. always write zeroes to this bit field. 2 en_spkr_zcd rw 0x0 enable zero cross detect for speaker amplifier. this is a separate circuit from the headphone and adc zcd. it is reset by a power-on reset only. 1 zcd_selectadc rw 0x0 set to one to enable zcd on adcmux amplifier (and disable zcd on headphone amplifier). set to zero for zcd on headphone amplifier. note that, while this bit is located in the audioout address space, since it controls both dac and adc functions, it is not reset by the audioout's sftrst bit. it is reset by a power-on reset only. 0 en_zcd rw 0x0 enable zero cross detect for headphone amplifier and/or adc mux amplifier. selectadc bit 21 chooses between headphone and adc amplifier select (they share a zcd circuit). note that, while this bit is located in the audioout address space, since it controls both dac and adc functions, it is not reset by the audioout's sftrst bit. it is reset by a power-on reset only. table 887. hw_audioout_anact rl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 673 description: this register provides miscellaneous audio control bits. example: hw_audioout_anactrl.en_zcd = 1; // enable zero cross detect. 26.7.11. miscellaneous test audio controls register description this register provides miscellaneous audio test bits. hw_audioout_test 0x800480a0 hw_audioout_test_set 0x800480a4 hw_audioout_test_clr 0x800480a8 hw_audioout_test_tog 0x800480ac table 888. hw_audioout_test 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd6 hp_antipop rsrvd5 tm_adcin_tohp tm_speaker tm_hpcommon hp_i1_adj hp_iall_adj spkr_i1_adj spkr_iall_adj rsrvd4 vag_classa vag_double_i rsrvd3 hp_chopclk rsrvd2 dac_chopclk rsrvd1 dac_classa dac_double_i dac_dis_rtz table 889. hw_audioout_test bit field descriptions bits label rw reset definition 31 rsrvd6 ro 0x0 reserved. always write zeroes to this bit field. 30:28 hp_antipop rw 0x0 reserved 27 rsrvd5 ro 0x0 reserved. always write zeroes to this bit field. 26 tm_adcin_tohp rw 0x0 testmode to pipe adc mux out (adc in) to headphone output pins. no longer have adc filter pins, this allows visibility to adc mux amp performance. to use this mode, the headphone load and the headphone board compensation must be removed (the adc amp cannot drive it). note that, although this bit is located in the dac address space, it is an adc function and is reset by the adc sftrst bit. 25 tm_speaker rw 0x0 testmode to pipe speaker pos to microphone input. this is used for analog loopback dac-speaker-mic- adc mode. there should be no load on the mic input pin during this mode. 24 tm_hpcommon rw 0x0 uses headphone common vag, instead of vaggate in adc mux. this is used for analog loopback dac-hp- adc mode to include common amp in path. 23:22 hp_i1_adj rw 0x0 adjusts bias current in first stage of headphone amplifier : 00=nominal. 01=-50%. 10=+100%. 11=+50%. it is reset by a power-on reset only. free datasheet http:/// STMP36XX official product documentation 5/3/06 674 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 description: this register provides miscellaneous audio test bits.. example: hw_audioout_test.tm_hpcommon = 1; // use headphone common vag. 26.7.12. bist control and status register description the bist control and status register pr ovides overall control of the integrated bist engine. 21:20 hp_iall_adj rw 0x0 adjusts all bias current in headphone amplifier : 00=nom, 01=-50%, 10=+50%, 11=-40%. it is reset by a power-on reset only. 19:18 spkr_i1_adj rw 0x0 adjusts bias current in 1st stage of speaker amplifier : 00=nom, 01=-50%, 10=+100%, 11=+50%. it is reset by a power-on reset only. 17:16 spkr_iall_adj rw 0x0 adjusts all bias current in speaker amplifier : 00=nominal. 01=-50%. 10=+50%. 11=-40%. it is reset by a power-on reset only. 15:14 rsrvd4 ro 0x0 reserved. always write zeroes to this bit field. 13 vag_classa rw 0x0 set to one to disable classab mode in vag amp. will increase current by ~200 ua. note that, while this bit is located in the audioout address space, since it controls both dac and adc functions, it is not reset by the audioout's sftrst bit. it is reset by a power-on reset only. 12 vag_double_i rw 0x0 set to one to double classa current in vag amplifier (+240ua). note that, while this bit is located in the audioout address space, since it controls both dac and adc functions, it is not reset by the audioout's sftrst bit. it is reset by a power-on reset only. 11:10 rsrvd3 ro 0x00 reserved. always write zeroes to this bit field. 9:8 hp_chopclk rw 0x0 enable chopping in the headphone and microphone amplifiers: 00=disabled. 01=48 khz. 10=96 khz. 11=192 khz. 7:6 rsrvd2 ro 0x0 reserved. always write zeroes to this bit field. 5:4 dac_chopclk rw 0x0 enable chopping in the dac amplifier: 00=disabled. 01=384 khz. 10=192 khz. 11=96 khz. 3 rsrvd1 ro 0x0 reserved. always write zeroes to this bit field. 2 dac_classa rw 0x0 set to one to disable classab mode in dac. will increase power by ~600 ua. 1 dac_double_i rw 0x0 set to one to double classa current in dac amplifier (+360 ua in each dac). 0 dac_dis_rtz rw 0x0 set to one to disable dac rtz mode. test-only bit that disables the return-to-zero function. this bit should remain cleared. table 889. hw_audioout_test bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 675 hw_audioout_bistctrl 0x800480b0 hw_audioout_bistctrl_set 0x800480b4 hw_audioout_bistctrl_clr 0x800480b8 hw_audioout_bistctrl_tog 0x800480bc description: the bistctrl register provides overall control of the integrated bist engine. example: hw_audiout_bistctrl.u = 0x00000000; 26.7.13. hardware bist status 0 register description this register provides visibility into memory failures detected by the bist engine. hw_audioout_biststat0 0x800480c0 hw_audioout_biststat0_set 0x800480c4 hw_audioout_biststat0_clr 0x800480c8 hw_audioout_biststat0_tog 0x800480cc table 890. hw_audioout_bistctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 fail pass done start table 891. hw_audioout_bistctrl bit field descriptions bits label rw reset definition 31:4 rsvd0 ro 0x0 reserved 3 fail ro 0x0 bist has failed. 2 pass ro 0x0 bist has passed 1 done ro 0x0 bist has completed. 0 start rw 0x0 reserved. always write a 0 to this bit field. table 892. hw_audioout_biststat0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd0 data table 893. hw_audioout_biststat0 bit field descriptions bits label rw reset definition 31:24 rsvd0 ro 0x0 reserved 23:0 data ro 0x0 failing data at the failing address. free datasheet http:/// STMP36XX official product documentation 5/3/06 676 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 description: the audioout biststat0 provides visi bility into memory failures detected by the bist engine. example: hw_audiout_biststat0.u = 0x00000000; 26.7.14. hardware audiout bist status 1 register description the audioout bistatts 1 provides visibility into memo ry failures dete cted by the bist engine. hw_audioout_biststat1 0x800480d0 hw_audioout_biststat1_set 0x800480d4 hw_audioout_biststat1_clr 0x800480d8 hw_audioout_biststat1_tog 0x800480dc description: the audioout bistatts1 provides visi bility into memory failures detected by the bist engine. example: hw_audiout_bistatts1.u = 0x00000000; 26.7.15. analog clock control register description this register provides analog clock control. hw_audioout_anaclkctrl 0x800480e0 hw_audioout_anaclkctrl_set 0x800480e4 hw_audioout_anaclkctrl_clr 0x800480e8 hw_audioout_anaclkctrl_tog 0x800480ec table 894. hw_audioout_biststat1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd1 state rsvd0 addr table 895. hw_audioout_biststat1 bit field descriptions bits label rw reset definition 31:29 rsvd1 ro 0x0 reserved 28:24 state ro 0x0 fail state of the bist engine. 23:8 rsvd0 ro 0x0 failing data at the failing address. 7:0 addr ro 0x0 failing data at the failing address. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 26: audioout/dac 677 description: this register provides analog clock control. example: hw_audioout_anaclkctrl.invert_dacclk = 1; // invert dac clock. 26.7.16. audioout write da ta register description the audioout write data register prov ides a means to output pcm audio sam- ples. hw_audioout_data 0x800480f0 hw_audioout_data_set 0x800480f4 hw_audioout_data_clr 0x800480f8 hw_audioout_data_tog 0x800480fc table 896. hw_audioout_anaclkctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 clkgate rsrvd3 invert_dacclk rsrvd2 dacdiv table 897. hw_audioout_anacl kctrl bit fiel d descriptions bits label rw reset definition 31 clkgate rw 0x1 analog clock gate. set this bit to gate the clocks for the dac converter and associated digital filter. it is reset by a power-on reset only. 30:5 rsrvd3 ro 0x0 reserved 4 invert_dacclk rw 0x0 dac clock invert. set this bit to invert the dac_clk for the dac sigma-delta converter and associated digital filters. 3 rsrvd2 ro 0x0 reserved 2:0 dacdiv rw 0x0 dac analog clock divider. this bit field is used to select the oversampling clock rate used by the adc. this bit field should only be changed per sigmatel. 000=6 mhz. 001=4 mhz. 010/100=3 mhz. 011/101=2 mhz. 110=1.5 mhz. 111=1 mhz. table 898. hw_audioout_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 high low free datasheet http:/// STMP36XX official product documentation 5/3/06 678 chapter 26: audioout/dac 5-36xx-d1-1.02-050306 description: the audioout write data register provides 32-bit data transfers for the dma or alternatively can be directly written by the cpu. each data value written to the regis- ter is placed in the audioout's fifo, whic h in turn is used by the digital fir filter stages. these 32-bit values contain either one 32-bit sample or two 16-bit samples, depending on how the data size is progra mmed. note that the pcm audio data input to the fir filter stages is 24 bit. for 16-b it operation, the input data is sign extended to 24 bits. for 32-bit mode, it is normalized by dropping the least significant 8 bits. example: hw_audioout_data.u = 0x12345678; // write 0x1234 to the right channel and 0x5678 to the left channel in 16 bit per sample mode hw_audioout_data.u = 0x12345678; // write 0x12345678 to either the left or right channel in 32 bit per sample mode. audioout xml revision: 1.67 table 899. hw_audioout_d ata bit field descriptions bits label rw reset definition 31:16 high rw 0x0000 right sample or sample high half-word. for 16-bit sample mode, this field contains the right channel sample. for 32-bit sample mode, this field contains the most significant 16 bits of th e 32-bit sample (either left or right). 15:0 low rw 0x0000 left sample or sample low half-word. for 16-bit sample mode, this field contains the left channel sample. for 32-bit per sample mode, this field contains the least significant 16 bits of the 32-bit sample (either left or right). free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 27: spdif transmitter 679 27. spdif transmitter this chapter describes the spdif transmitter provided on the STMP36XX. it includes sections on interrupts, clocking, dma operation, and pio debug mode. programmable registers are described in section 27.6 . 27.1. overview the sony-philips digital interface format (spdif) transmitte r module transmits data according to the spdif digital audio interface standard (iec-60958). figure 122 shows a block diagram of the spdif transmitter module. data samples are transmitted as blocks of 192 frames, each frame consisting of two 32-bit sub-frames. a 32-bit sub-frame is composed of a 4-bit preamble, a 24-bit data payload (e.g., a left- or right-channel pcm sample), and a 4- bit status field. the status fields are encoded according to the iec-60958 consumer specification, reflecting the contents of the hw_spdif_framctrl and hw_ spdif_ctrl registers. see the iec- 60958 specification for proper programming of these fields. the sub-frame is transmitted serially, l sb-first, using a biphase-mark channel-cod- ing scheme. this encoding allows an spdif receiver to recover the embedded clock signal. note: sub-frame information can be changed ?on-the-fly? but is not reflected in the serial stream until the current frame is transmitted. this ensures consistency of the frame and the generated parity appended to that frame. the spdif transmitter operates at one of three register-selectable base sample rates: 32 khz, 44.1 khz, or 48 khz. do uble-rate output (64 khz, 88.2 khz, and 96 khz) can also be selected using the hw_spdif_srr_basemult register. the data-clock required to transmit an spdif frame at these sample-rates is generated using a fractional clock-divider. this divi der uses both edges of the 480-mhz clock directly from the output of the pll, divided by 4. this divider is located in the clkc- trl module where all system clocks ar e generated; the resultant clock (pcm_spdif_clk) is output to the spdif mo dule to be used fo r data transmission. note: the spdif module only operates within iec-60958 consumer audio speci- fications when the pll and hw _clkctrl_spdifctrl_freq_div are appropri- ately programmed to provide a 120-mhz clock to the spdif_clkctrl module. lower frequency cloc ks may be used, but will not me et the above specifications. implementation note: the output of the spdif_clk_gen module (the pcm_spdif_clk) must be declared as a generated clock, and any signals crossing between this clock-domain (pcm_spdif) and the apb_clk domain must be appropri- ately clock-crosse d (2-flop, metastability circuit). note: a lut may be implemented in the clkctrl module to allow clock-genera- tion for spdif when pll output frequency is programmed from 360?480 mhz. free datasheet http:/// STMP36XX official product documentation 5/3/06 680 chapter 27: spdif transmitter 5-36xx-d1-1.02-050306 the spdif module receives data by one of two methods: ? software-directed pio writes to the hw_spdif_wdata register ? appropriate programming of the dma-engine. (see chapter 11 , ?ahb-to-apbx bridge with dma? on page 257 , for a detailed description of the dma module and how to perform dma data transfers to/from modules and memory.) once provided by the dma, the received da ta is placed in a 2x24 word fifo for each channel, left and right. at initialization, the fifo is filled before spdif data transfer occurs. after this, data is requested whenever this fifo has an empty entry or at a nominal rate corresponding to the programmed sample-rate in hw_spdif_srr. the behavior of the spdif module during or after a fifo underflow is programma- ble. on detection of an underflow event, the spdif module sends the current sam- 24-mhz xtal osc. divide by n arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram pll 480 mhz divide by 4 pcm_spdif_clk spdif programmable registers dual-edge fractional clock divider hw_spdif_srr hw_spdif_srr_rate divide ratio rom clock divider hw_spdif_ctrl spdif data encoding dma data flow control 2x24 left-channel fifo 2x24 right-channel fifo dma request engine spdif stream control clock crossing pcm_spdif_clk domain fifo control and request generation data formatting (16-bit/24-bit) apbx_clk domain clkctrl module hw_spdif_framectrl spdif_data figure 122. spdif transmitter block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 27: spdif transmitter 681 ple for four frames before muting (sending zeros) the data stream based on the configuration of hw_spdif_framectrl_amute. the final validity unit embed- ded within each frame dictates whether the receiver processes the data within that frame. hw_spdif_framectrl determ ines the behavior of this bit. spdif data can be transmitted in one of two modes: 32-bit mode and 16-bit mode. selection between these modes is done with the hw_spdif_ctrl_data_width register. in either case, data samples must be interleaved in main memory for proper behavior, although in 32-bit mode, 32-bit words are interleaved and in 16-bit mode, 16-bit words are interleaved. ? when hw_spdif_ctrl_data_width=0, 32-bit mode is enabled, and hw_spdif_wdata contains either the left or right data sample. since the spdif frame allows for transmission of only 24 bits, only the 24 msbs stored in the hw_spdif_wdata regist er will be transmitted. ? alternately, when hw_spdif_ctrl_da ta_width=1, 16-bit mode is enabled, and the hw_spdif_wdata register will contain one of each left and right samples. the data transmitted in the spd if frame will be these 16 msbs with 8 zeros appended in the lsb positions. spdif normal operation 0 1 hw_spdif_ctrl_underflow_irq hw_spdif_framectrl_automute underflow asserted after 4-frames consecutive frames w/empty fifo hw_spdif_framectrl_v_config spdif_data = 0 spdif_data = last_value 1 0 hw_spdif_ framectrl_v 0 1 final validity=0 final validity=0 final validity=1 final validity=1 figure 123. spdif flow chart free datasheet http:/// STMP36XX official product documentation 5/3/06 682 chapter 27: spdif transmitter 5-36xx-d1-1.02-050306 note: if the data supplied actually represents a lower resolution analog-to-digital conversion, this information is not captur ed by the spdif transmitter, which always reports a 24-bit sample-size. 27.2. interrupts the spdif module contains a single interrupt source that is asserted on fifo over- flows and/or fifo underflows. this interrupt is enabled by setting hw_spdif_ctrl_fifo_err_irq_en. on interrupt detection, the hw_spdif_ctrl_underflow_irq a nd hw_spdif_ctrl_overflow_irq fields can be polled for the exact cause of the interrupt and appropriate action taken. note: these bits remain valid for polling, regard less of the state of the interrupt enable. 27.3. clocking the iec-60958 specification outlines the requirements for spdif clocking. the spdif module is designed according to the consumer audio requirements. these dictate that: ? average sample-rate error must not exceed 1000 ppm ? maximum instantaneous jitter must not exceed ~4.4 ns. the jitter requirement implies either a single-phase of a >240-mhz clock or both phases of a 120-mhz clock. it also implie s the use of a fractional divider for which the divisors are maintained to sufficient si gnificant digits to yield the required ppm tolerance. the spdif module in the stmp 36xx uses nine-bit fractional coefficients that yield an average frequency error of 52 ppm. these coefficients are determined according to the required clock-rates that are dictated by the sample rates imple- mented. the required clock frequencies provided by the clkctrl module for the implemented sample-rates are: f(48 khz) 6.144 mhz f(44.1 khz) 5.6448 mhz f(32 khz) 4.096 mhz f(96 khz) 12.288 mhz f(88.2 khz) 11.2896 mhz f(64 khz) 8.192 mhz all clocks within the spdif module are gated according to the state of hw_spdif_ctrl_clkgate. when set, all clocks derived from the apb_clk are gated. gating of the pcm_spdi f_clk is accomplished through hw_clkctrl_spdifclkctrl_clkgate. a mo dule-level reset is also provided in hw_spdif_ctrl_sftrst. setting this bit performs a module-wide reset and subsequent assertion of the hw_spdif_ctrl_clkgate. note: a soft reset (sftrst) can take multiple clock periods to complete, so do not set clkgate when setting sftrst. th e reset process gate s the clocks auto- matically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 27: spdif transmitter 683 27.4. dma operation using the spdif module in dma mode involves configuring the appropriate dma channel to provide the interleaved data blocks stored in memory. see chapter 11 , ?ahb-to-apbx bridge with dma? on page 257 for detailed information on dma pro- gramming. once programmed, the dma engine references a set of linked dma descriptors stored by the cpu in main memory. these descriptors point to data blocks stored in system memory and also provide a mechanism for automated pio writes before transfer of a data-block. figure 124 describes a typical set of descrip- tors required to transmit two data-blocks. here, the dma is instructed to perform two pio writes prior to toggling the dma_pcmdkick signal : ? hw_spdif_ctrl_underflow_irq_en is se t to enable interrupts on fifo underflow detect ? hw_spdif_framectrl_amute and hw_spdif_framectrl_v_config are set to mute and tag the data stream as invalid on a fifo underflow. the dma engine is then programmed to transfer 512-bytes to the spdif module. additionally, the spdif module contains a mechanism for ?throttling? dma requests to the dma engine. this circuit is prog rammed using the hw_spdif_ctrl_dmawait 512-byte data block 0 read nextcmd_addr 512 buffer address hw_spdif_ctrl=0x00000001 1 0 2 10 0 read nextcmd_addr 512 buffer address hw_spdif_ctrl=0x00000001 1 0 2 10 0 512-byte data block 1 nextcmd_addr 0 buffer address hw_spdif_ctrl=0xc0000000 1 0 1 10 0 hw_spdif_framectrl= 0x00030000 hw_spdif_framectrl= 0x00030000 figure 124. spdif dma two-block transmit example free datasheet http:/// STMP36XX official product documentation 5/3/06 684 chapter 27: spdif transmitter 5-36xx-d1-1.02-050306 field and corresponds to the number of cycles of the apb_clk to wait before toggling the dma_preq signal to the dma engine. note: considering that the bandwidth requirements of the spdif module are mini- mal (not in excess of 96 khz) and burst re quests occur only in pairs, this field can be ignored for most, if no t all, applications. there is a floor apbx frequency below whic h the spdif cannot wo rk without errors. that frequency can be calculated as follows: ? assume that there are 6 ot her blocks apart from spdif on the apbx bus, and it takes 4 apbx clock cycles to service each bl ock. if the number of clock cycles required to service each block changes, change the equations accordingly. ? assume that hw_spdif_ctrl_dma_wait is less than dma latency. if this is not true, then even dma wait has to be added to the calculation and the floor apbx frequency incr eases further. in 16-bit mode: floor apbx freq = (dma latency + 9) * sample rate. for max dma latency = (6 blocks) x (4 cycles per block) = 24 cycles and max spdif sample rate = 96 khz, min apbx freq = 3.168 mhz. in 32-bit mode: (a) ideal calculation: min freq = [2*(dma latency+4) + 7] * sample rate. for max dma latency = 24 cycles and max spdif sample rate = 96 khz, min apbx freq = 6.048 mhz. (b) simpler calculation: floor apbx freq = 2*(latency + 9) * sample rate = twice that of 16-bit mode. for max latency = 24 cycles and max sample rate = 96 khz, min apbx freq = 6.336 mhz. option a is ideal as it allows a lower floo r frequency; option b can be used to keep it simple and avoid confusion. 27.5. pio debug mode of operation the block is connected only as a pio device to the apbx bus. even though it is designed to work with the dma controller integrated in the apbx bridge, all trans- fers to and from the block are programme d i/o (pio) read or write cycles. when the dma is ready to write to the hw_spdif_data register, it does so with standard apb write cycles. there are four dma related signals that connect the spdif trans- mitter to the dma, but all data transfers are standard pio cycles on the apb. the state of these four signals can be seen in the hw_spdif_debug register. thus, it is possible to comp letely exercise the spdif block for diagnostic purposes, using only load and store instructions from the cpu without ever starting the dma controller. this section describes how to interact with the block using pio opera- tions, and also defines the block?s detailed behavior. whenever the hw_spdif_ctrl register is written to, by either the cpu or the dma, it establishes the basic operation m ode for the block. if the hw_spdif_ctrl register is written with a one in the run bit, then the operation begins and the spdif attempts to read the data block by toggling its pdmareq signal to the dma. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 27: spdif transmitter 685 notice that the pdmareq signal is defined as a ?toggle? signal. this changes state to signify either a request for another dma word or a notification that the current command transfer has been ended by t he spdif. diagnostic software should poll these signals to determine when the spdif is ready for another dma write, and can then supply data by storing a 32-bit word to the hw_spdif_data register, just as the dma would do in normal operation. to perform spdif transfers in pio debug mo de, diagnostic software should perform the following: 1. program the hw_clkctrl_spdifclkctrl register correctly and wait for the pll to lock. 2. turn off the soft reset bit, hw_spdif_ctrl_sftrst , and the clock gate bit, hw_spdif_ctrl_clkgate. 3. properly configure the subcode information by writing the hw_spdif_framectrl register. note: see iec-60958 for proper coding of these fields. 4. enable the spdif transmitter by se tting the hw_spdif_ctrl_run register. 5. wait for hw_spdif_debug_dma_ preq status bit to toggle. 6. write one sample of the left/right data block data to the hw_spdif_data reg- ister. 7. repeat 5 and 6 until all samples have been written to hw_spdif_data. 27.6. programmable registers the following registers provide control for programmable elements of the spdif module. 27.6.1. spdif control register description the spdif control register provides overall control of the spdif converter. hw_spdif_ctrl 0x80054000 hw_spdif_ctrl_set 0x80054004 hw_spdif_ctrl_clr 0x80054008 hw_spdif_ctrl_tog 0x8005400c table 900. hw_spdif_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsrvd1 dmawait_count rsrvd0 wait_end_xfer word_length fifo_underflow_irq fifo_overflow_irq fifo_error_irq_en run free datasheet http:/// STMP36XX official product documentation 5/3/06 686 chapter 27: spdif transmitter 5-36xx-d1-1.02-050306 description: the spdif control register contains t he overall control for spdif sample formats, loopback mode, and interrupt controls. example: table 901. hw_spdif_ctrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 setting this bit to one forces a reset to the entire block and then gates the clocks off. this bit must be set to zero for normal operation. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one it gates off the clocks to the block. warning: first set the clkgate bit in the hw_clkctrl_spdifclkctrl register to 1. only then, set this bit to 1 to prevent any extra samples from being transmitted. when removing clock gating, follow the reverse order: first reset this clkgate bit to 0, and then reset the clkgate bit in the hw_clkctrl_spdifclkctrl register to 0 . 29:21 rsrvd1 ro 0x00 reserved 20:16 dmawait_count rw 0x00 dma request delay count. this bit field specifies the number of apbx clock cycles (0 to 31) to delay before each dma request. this field acts as a throttle on the bandwidth consumed by the spdif block. this field can be loaded by the dma. 15:6 rsrvd0 ro 0x000 reserved 5 wait_end_xfer rw 0x1 set this bit to a one if the spdif transmitter should wait until the internal fifo is empty before halting transmission based on deassertion of run. use in conjuntion with hw_spdif_stat_end_xfer to determine transfer completion 4 word_length rw 0x0 set this bit to one to enable 16-bit mode. set this bit to zero for 32-bit mode. in either case, the spdif frame allows transmission of only 24 bits. in 16-bit mode, eight zeros will be appended to the lsb's of the input sample; in 32-bit mode, the 24 msb's of hw_spdif_wdata will be transmitted. 3 fifo_underflow_irq rw 0x0 this bit is set by hardware if the fifo underflows during spdif transmission. it is reset in software by writing a zero to the bit position or by writing a one to the sct clear address space. 2 fifo_overflow_irq rw 0x0 this bit is set by hardware if the fifo overflows during spdif transmission. it is reset by software by writing a zero to the bit position or by writing a one to the sct clear address space. 1 fifo_error_irq_en rw 0x0 set this bit to one to enable a spdif interrupt request on fifo overflow or under flow status conditions. 0 run rw 0x0 setting this bit to one causes the spdif to begin converting data. the actual conversion will begin when the spdif fifo is filled (4 or 8 words written, depending upon sample word format, i.e., 16 or 32 bits). free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 27: spdif transmitter 687 hw_spdif_ctrl.run = 1; // start spdif conversion 27.6.2. spdif status register description the spdif status register reflects overall status of the spdif converter. hw_spdif_stat 0x80054010 hw_spdif_stat_set 0x80054014 hw_spdif_stat_clr 0x80054018 hw_spdif_stat_tog 0x8005401c description: the spdif status register provides the status of the spdif converter. example: unsigned testbit = hw_spdif_stat.present; 27.6.3. spdif frame control register description the spdif frame control register provides direct control of the control bits trans- mitted over an spdif frame. hw_spdif_framectrl 0x80054020 hw_spdif_framectrl_set 0x80054024 hw_spdif_framectrl_clr 0x80054028 hw_spdif_framectrl_tog 0x8005402c table 902. hw_spdif_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 present rsrvd1 end_xfer table 903. hw_spdif_stat bit field descriptions bits label rw reset definition 31 present ro 0x1 this bit is set to 1 in products in which spdif is present. 30:1 rsrvd1 ro 0x0 reserved 0 end_xfer ro 0x0 when set, indicates that the spdif module has completed transfer of all data, including data stored in internal fifos. used in conjunction with hw_spdif_ctrl_wait_end_xfer. free datasheet http:/// STMP36XX official product documentation 5/3/06 688 chapter 27: spdif transmitter 5-36xx-d1-1.02-050306 description: the spdif frame control register provides direct control of the control bits trans- mitted over an spdif frame. example: hw_spdif_framectrl.copy=1 //spdif frame contains copyrighted material 27.6.4. spdif sample rate register description the spdif sample rate register controls the sample rate of the data stream played back from the circular buffer. hw_spdif_srr 0x80054030 hw_spdif_srr_set 0x80054034 hw_spdif_srr_clr 0x80054038 table 904. hw_spdif_framectrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 v_config auto_mute rsrvd1 user_data v l rsrvd0 cc pre copy audio pro table 905. hw_spdif_framectrl bit field descriptions bits label rw reset definition 31:18 rsrvd2 ro 0x0 reserved 17 v_config rw 0x1 defines spdif behavior when sending invalid frames. 0:do not tag frame as invalid. 1: tag frame as invalid. 16 auto_mute rw 0x0 auto-mute stream on stream-suspend detect. 15 rsrvd1 ro 0x0 reserved 14 user_data rw 0x0 user data transmitted during each sub-frame. consult iec standard for additional details. 13 v rw 0x0 indicates that a sub-frame's samples are invalid. if v=0, the sub-frame is indicated as valid, that is, correctly transmitted and received by the interface. if v=1, the subframe is indicated as invalid. 12 l rw 0x0 generation level is defined by the iec standard, or as appropriate. 11 rsrvd0 ro 0x0 reserved 10:4 cc rw 0x0 category code is defined by the iec standard, or as appropriate. 3 pre rw 0x0 0: no pre-emphasis. 1: pre-emphasis is 50/15 usec. 2 copy rw 0x0 0: copyright bit not asserted. 1: copyright bit asserted. 1 audio rw 0x0 audio=0:pcm data;1. audio=non-pcm data 0 pro rw 0x0 0: consumer use of the channel. 1: professional use of the channel. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 27: spdif transmitter 689 hw_spdif_srr_tog 0x8005403c description: the spdif sample rate register provides a rate field for specifying the sample rate conversion factor to use in outputting the current spdif stream. example: hw_spdif_srr.b.rate = 0x0ac44; // 44.1khz 27.6.5. spdif debug register description the spdif debug register provides read-only access to various internal state infor- mation that may be useful for block debugging and validation. hw_spdif_debug 0x80054040 hw_spdif_debug_set 0x80054044 hw_spdif_debug_clr 0x80054048 hw_spdif_debug_tog 0x8005404c table 906. hw_spdif_srr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 basemult rsrvd0 rate table 907. hw_spdif_srr bit field descriptions bits label rw reset definition 31 rsrvd1 ro 0x0 reserved 30:28 basemult rw 0x1 base-rate multiplier. 1=single-rate( 48 khz). 2=double-rate (96 khz). 27:20 rsrvd0 ro 0x0 reserved 19:0 rate rw 0x00000 sample-rate conversion factor. the only valid entries are: 0x07d00, 0x0ac44, 0x0bb80 // 38k, 44.1k, 48k table 908. hw_spdif_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd1 dma_preq fifo_status free datasheet http:/// STMP36XX official product documentation 5/3/06 690 chapter 27: spdif transmitter 5-36xx-d1-1.02-050306 description: this is a read-only register used for c hecking fifo status and pio mode of opera- tion. example: unsigned testbit = hw_spdif_debug.dma_preq; 27.6.6. spdif write data register description the spdif write data register receives 32-bit data transfers from the dma. it deposits the data into an internal fifo and from there into the spdif stream. these 32-bit writes contain either one 32-bit sample or two 16-bit samples. hw_spdif_data 0x80054050 hw_spdif_data_set 0x80054054 hw_spdif_data_clr 0x80054058 hw_spdif_data_tog 0x8005405c description: writing a 32-bit value to the register corresponds to pushing that 32-bit value into the spdif fifo. the dma writes 32-bit values to this register. in 32-bit-per-sample mode, the dma is writing either one full left sample or one full right sample for each table 909. hw_spdif_debug bit field descriptions bits label rw reset definition 31:2 rsrvd1 ro 0x00 reserved 1 dma_preq ro 0x0 dma request status. this read-only bit reflects the current state of the spdif's dma request signal. dma requests are issued any time the request signal toggles. this bit can be polled by software, in order to manually move samples to the spdif's fifo from a memory buffer when the spdif's dma channel is not used 0 fifo_status ro 0x1 this bit is set when the fifo has empty space. this reflects a dma request being generated. table 910. hw_spdif_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 high low table 911. hw_spdif_data bit field descriptions bits label rw reset definition 31:16 high rw 0x0000 for 16-bit mode, this field contains the entire right channel sample. for 32-bit mode, this field contains the 16 msbs of the 32-bit sample (either left or right). 15:0 low rw 0x0000 for 16-bit mode, this field contains the entire left channel sample. for 32-bit mode, this field contains the 16 lsbs of the 32-bit sample (either left or right). free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 27: spdif transmitter 691 write to this register. for 16-bit mode, the dma is writing a 16-bit left sample and a 16-bit right sample for each 32-bit write to this register. example: hw_spdif_data = 0x12345678; // write 0x1234 to the right channel and 0x5678 to the left channel in 16-bit mode hw_spdif_data = 0x12345678; // write 0x12345678 to either the left or right channel in 32- bit per sample mode. spdif xml revision: 1.26 free datasheet http:/// STMP36XX official product documentation 5/3/06 692 chapter 27: spdif transmitter 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 28: digital radio interface (dri) 693 28. digital radio interface (dri) this chapter describes the digital radio interface included on the STMP36XX. pro- grammable registers are described in section 28.4 . 28.1. overview the STMP36XX implements a digital interface to a digital radio receiver. details of the receiver are described in a separate data sheet. the interface consists of two digital input si gnals that share pins with the analog line inputs. these pins can be used for either their analog functions or their digital func- tions in any given application, but not both. figure 125 shows a block diagram of the digital radio interface, and figure 126 describes dri synchronization and data recovery. 24-mhz xtal osc. divide by n dri dri programmable regs and fifos arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram dma interface and capture state machine dri_clk dri_data frame capture 24 mhz dri_enable figure 125. digital radio interface (dri) block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 694 chapter 28: digital radio interface (dri) 5-36xx-d1-1.02-050306 28.2. frame structure the frame structure used on the di gital radio interface is shown in figure 127 . the 8-clock gap can vary from as short as 8 dr i_clks at 4 mhz (12 cl ocks at 6 mhz) to as long as allowed by the desired bandwidth. dri_clk is expected to run at 4 mhz or 6 mhz on this interface, i.e., it is expected to have a period of 250 ns or 166 ns except for the gap interval. dma interface and state machine 24-mhz xtal osc. divide by n dri programmable registers and fifos dri_clk dri_data 18-bit shift register 24 mhz apbx_clk sync 18-bit parallel register counter compartor dri_clk clock domain 24-mhz clock domain apbx_clk clock domain 24-mhz clock domain figure 126. dri synchronization and data recovery 16-bit pcm sample p 8-clock gap dri_clk dri_data a p a 18x clocks = 4.5 us 2.0 us figure 127. digital radio interface (dri) framing free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 28: digital radio interface (dri) 695 the gap is detected by synchronizing the dri_clk to 24.0 mhz. a counter is incre- mented for each 24-mhz clock. the rising edge of each synchronized dri_clk is used to reset the counter. if the counter ever reaches the threshold established in hw_dri_timing_gap_detection_interval , then the contents of the 18-bit shift register are captured into the 24-mhz domain, and the apbx_clk based state machine is notified. the bits within the 18-bit frame are shown in table 912 and described in table 913 . the pilot_peak bit generally occurs on every eighth pcm sample when pilot syn- chronization has been achieved in the digital radio. the dri hardware monitors this bit to ensure that it occurs on every eighth pcm sample. an interrupt is generated to the cpu if pilot synchronization is lost. in addition, hw_dri_status_phase_offset indicates the phase shift of the last pilot peak received relative to the phase estab- lished immediately after reset. this allows software to make programmatic phase shifts without restarting the dma. the two external inputs, dri_clk and dri_data, are supplied as 1.8-v digital pins that are connected to the analog line inputs. when the dri_enable bit is set, these inputs become digital inputs, as shown in figure 128 . table 912. digital radio interface frame 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 pilot peak attention 16-bit pcm sample table 913. dri frame bit field descriptions bits label definition 17 pilot peak set to one at the pilot peak. set to zero for the following n frames, where n is 7 for 4 mhz and 11 for 6 mhz. this is the first bit shifted in from the frame. 16 attention set to one by receiver to request attention from software. software uses the i 2 c bus to determine the cause of the attention request. when set to one in a frame, this bit causes an attention interrupt to be set in the hw_dri_ctrl register. 15:0 pcm sample the 16 bit pcm sample value is pushed into the dma fifo and from there to a system memory buffer. free datasheet http:/// STMP36XX official product documentation 5/3/06 696 chapter 28: digital radio interface (dri) 5-36xx-d1-1.02-050306 28.3. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 24-mhz xtal osc. divide by n dri programmable regs and fifos dri_clk dri_data 18-bit shift register 24 mhz apbx_clk sync 18-bit parallel register dri_clk clock domain 24-mhz clock domain apbx_clk clock domain 24-mhz clock domain dri_enable analog line in figure 128. digital radio interface (dri) digital signals into analog line-in free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 28: digital radio interface (dri) 697 28.4. programmable registers the following registers describe the programming interface for the digital radio inter- face (dri). 28.4.1. dri control register description the dri control register specifies the reset state and the interrupt controls for the dri controller. hw_dri_ctrl 0x80074000 hw_dri_ctrl_set 0x80074004 hw_dri_ctrl_clr 0x80074008 hw_dri_ctrl_tog 0x8007400c table 914. hw_dri_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate enable_inputs rsvd4 stop_on_oflow_error stop_on_pilot_error rsvd3 dma_delay_count reacquire_phase rsvd2 overflow_irq_en pilot_sync_loss_irq_en attention_irq_en rsvd1 overflow_irq pilot_sync_loss_irq attention_irq run table 915. hw_dri_ctrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 set to zero for normal operation. when this bit is set to one (default), then the entire block is held in its reset state. run = 0x0 allow dri to operate normally. reset = 0x1 hold dri in reset. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one it gates off the clocks to the block. run = 0x0 allow dri to operate normally. no_clks = 0x1 do not clock dri gates in order to minimize power consumption. 29 enable_inputs rw 0x0 set this bit to one to enable the input pads in a digital input mode instead of line-in left/right normal analog mode. analog_line_in = 0x0 use line inputs in their analog mode. dri_digital_in = 0x1 use line inputs in their special dri digital mode. 28:27 rsvd4 ro 0x0 always set this bit field to zero. 26 stop_on_oflow_error rw 0x0 this bit is set to one to cause the run bit to reset and the dma transfers to stop on the detection of an overflow condition. ignore = 0x0 ignore a dma overflow condition and keep transferring samples to the dma. stop = 0x1 stop dma transfers when a dma overflow condition is detected. free datasheet http:/// STMP36XX official product documentation 5/3/06 698 chapter 28: digital radio interface (dri) 5-36xx-d1-1.02-050306 25 stop_on_pilot_error rw 0x0 this bit is set to one to cause the run bit to reset and the dma transfers to stop on the detection of a loss of sync condition. ignore = 0x0 ignore a loss of pilot sync condition and keep transferring samples to the dma. stop = 0x1 stop dma transfers when a loss of pilot sync is detected. 24:21 rsvd3 ro 0x0 always set this bit field to zero. 20:16 dma_delay_count rw 0x01 this bit field used to encode the number of idle cycles that must be placed between successive dma requests. it no longer peforms this function. these bits are now spares. 15 reacquire_phase rw 0x0 this bit is set to one to cause the state machine to reacquire its phase alignment with the pilot peak marker in the eighteenth bit. this bit will be reset to zero by the hardware when the next pilot peak marker is received. normal = 0x0 normal operation with existing phase relationship. new_phase = 0x1 reacquire new phase. 14:12 rsvd2 ro 0x0 always set this bit field to zero. 11 overflow_irq_en rw 0x0 this bit is set to enable an overflow interrupt. disabled = 0x0 interrupt request disabled. enabled = 0x1 interrupt request enabled. 10 pilot_sync_loss_irq_en rw 0x0 this bit is set to enable a pilot sync loss interrupt. disabled = 0x0 interrupt request disabled. enabled = 0x1 interrupt request enabled. 9 attention_irq_en rw 0x0 this bit is set to enable an attention interrupt from the dri. disabled = 0x0 interrupt request disabled. enabled = 0x1 interrupt request enabled. 8:4 rsvd1 ro 0x0 always set this bit field to zero. 3 overflow_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the dri controller. this bit is cleared by software by writing a one to its sct clear address. a dma fifo overrun was detected, pcm samples have been lost. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 2 pilot_sync_loss_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the dri controller. this bit is cleared by software by writing a one to its sct clear address. this bit is set if the expected pilot peak bit is not seen at the expected eight-sample boundary. firmware should consider resynchronizing its data framing in the dma buffers. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. table 915. hw_dri_ctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 28: digital radio interface (dri) 699 description: this register is either written by the dma or the cpu, depending on the state of an dri transaction. example: // turn off soft reset and clock gating hw_dri_ctrl_clr(bm_dri_ctrl_sftrst| bm_dri_ctrl_clkgate); 28.4.2. dri timing register description the dri timing register specifies the de tailed timing used for the dri controller. hw_dri_timing 0x80074010 1 attention_irq rw 0x0 this bit is set to indicate that an interrupt is requested by the dri controller. this bit is cleared by software by writing a one to its sct clear address. this bit is set in response to the detection of an attention bit in a dri frame. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 0 run rw 0x0 set this bit to one to enable the dri controller operation. this bit is automatically set by dma commands that write to ctrl1 after the last pio write of the dma command. for soft dma operation, software can set this bit to enable the controller. see note in hw_dri_debug1 register about when to manually set this bit. there are cases in which the dma should be used to kick off the digtial radio interface. halt = 0x0 no dri command in progress. run = 0x1 process a slave or master dri command. table 916. hw_dri_timing 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 pilot_rep_rate rsvd1 gap_detection_interval table 915. hw_dri_ctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 700 chapter 28: digital radio interface (dri) 5-36xx-d1-1.02-050306 description: this register is either written by the dma or the cpu depending on the state of an dri transaction. example: // set the gap detection interval hw_dri_timing_wr(0x00000022); 28.4.3. dri status register description the dri controller reports status information in this register. hw_dri_stat 0x80074020 table 917. hw_dri_timin g bit field descriptions bits label rw reset definition 31:20 rsvd2 ro 0x0 always set this bit field to zero. 19:16 pilot_rep_rate rw 0xc set this bit field to the number of dri samples between pilot sample centers. set to 8 for 4-mhz. set to 0xc for 6-mhz operation. 15:8 rsvd1 ro 0x0 always set this bit field to zero. 7:0 gap_detection_interval rw 0x10 set this bit field to the number of 24-mhz crystal clocks to count to detect a gap in dri source clocks. table 918. hw_dri_stat 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dri_present rsvd3 pilot_phase rsvd2 overflow_irq_summary pilot_sync_lo ss_irq_summary attention_irq_summary rsvd1 table 919. hw_dri_stat bit field descriptions bits label rw reset definition 31 dri_present ro 0x1 this read-only bit indicates that the dri interface is present when it reads back a one. this dri function is not available on a device that returns a zero for this bit field. unavailable = 0x0 dri is not present in this product. available = 0x1 dri is present in this product. 30:20 rsvd3 ro 0x0 always set this bit field to zero. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 28: digital radio interface (dri) 701 description: the status register provides read-only ac cess to the function presence bits, as well as the pilot phase detector and the interrupt summaries. example: if(hw_dri_stat.dri_present != bv_dri_stat_slave_busy__available)// then wait till it fin- ishes 28.4.4. dri controller dma read data register description the dri dma read data register is the target for both source and destination dma transfers. this register is backed by an eight-deep fifo. hw_dri_data 0x80074030 description: 19:16 pilot_phase ro 0x0 this bit indicates the phase of the last pilot peak marker received from the digital radio relative to a phase established when the dri block was removed from soft reset state and saw its first pilot peak. this value will be zero until the first phase error is noticed. 15:4 rsvd2 ro 0x0 always set this bit field to zero. 3 overflow_irq_summary ro 0x0 this bit is set to indicate that an interrupt is requested by the dri controller. it is the logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 2 pilot_sync_loss_irq_su mmary ro 0x0 this bit is set to indicate that an interrupt is requested by the dri controller. it is the logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 1 attention_irq_summary ro 0x0 this bit is set to indicate that an interrupt is requested by the dri controller. it is the logical and of the corresponding interrupt status bit and interrupt enable bit. no_request = 0x0 no interrupt request pending. request = 0x1 interrupt request pending. 0 rsvd1 ro 0x0 always set this bit field to zero. table 920. hw_dri_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 data table 921. hw_dri_data bit field descriptions bits label rw reset definition 31:0 data rw 0x00000000 the dma channel reads from this address. table 919. hw_dri_stat bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 702 chapter 28: digital radio interface (dri) 5-36xx-d1-1.02-050306 dma reads are directed to this register. example: the dma data register is used by the dma to read or write data from the dri controller as mediated by the dri controller`s dma request signal. 28.4.5. dri device debug register 0 description the dri device debug register 0 provides a diagnostic view into the internal state machine and states of the dri device. hw_dri_debug0 0x80074040 hw_dri_debug0_set 0x80074044 hw_dri_debug0_clr 0x80074048 hw_dri_debug0_tog 0x8007404c table 922. hw_dri_debug0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 dmareq dmacmdkick dri_clk_input dri_data_input test_mode pilot_rep_rate spare frame table 923. hw_dri_debug 0 bit field descriptions bits label rw reset definition 31 dmareq ro 0x0 read-only view of the toggle state of the dma request line. 30 dmacmdkick ro 0x0 read-only view of the toggle state of the dma request line. 29 dri_clk_input ro 0x0 read-only view of the state of the dri clock input signal from the analog logic. 28 dri_data_input ro 0x0 read-only view of the state of the dri data input signal from the analog logic. 27 test_mode rw 0x0 set to one to enable a special internal test mode that supplies pseudo dri frames as dri_clk and dri_data inputs. the integrated test source has been removed for synthesis. this is now a spare bit. 26 pilot_rep_rate rw 0x0 this bit is set to one to select a 12-sample repeat cycle for pilot sync (6-mhz ca se) in the test mode. set to zero for an 8-sample repeat cycle (4-mhz case). note: this bit only affects a built in test generator not the operating mode of the dri. the integrated test source has been removed for synthesis. this is now a spare bit. 8_at_4mhz = 0x0 at 4 mhz, there is 1 pilot per 8 samples. 12_at_6mhz = 0x1 at 6 mhz, there is 1 pilot per 12 samples. 25:18 spare rw 0x00 spares for patching hardware in metal. 17:0 frame ro 0x0000 current state of frame synchronizing register received from the digital radio receiver. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 28: digital radio interface (dri) 703 description: this register provides access to variou s internal states and controls that are used in diagnostic modes of operation. example: while(hw_dri_debug0.dmareq == old_dma_req_value); // wait for next dma request toggle old_dma_req_value = hw_dri_debug0.dmareq; // remember the new state of the dma request tog- gle 28.4.6. dri device debug register 1 description the dri device debug register 1 provid es a diagnostic view into the swizzle frame register of the dri device. hw_dri_debug1 0x80074050 hw_dri_debug1_set 0x80074054 hw_dri_debug1_clr 0x80074058 hw_dri_debug1_tog 0x8007405c table 924. hw_dri_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 invert_pilot invert_attention invert_dri_data invert_dri_clock reverse_frame rsvd1 swizzled_frame table 925. hw_dri_debug 1 bit field descriptions bits label rw reset definition 31 invert_pilot rw 0x0 this bit is set to one to invert the frame register bit used for the pilot peak indicator. normal = 0x0 normal clock polarity. inverted = 0x1 inverted clock polarity. 30 invert_attention rw 0x0 this bit is set to one to invert the frame register bit used for the attention bit. normal = 0x0 normal clock polarity. inverted = 0x1 inverted clock polarity. 29 invert_dri_data rw 0x0 this bit is set to one to invert the dri_data prior to shifting into the shift register. normal = 0x0 normal clock polarity. inverted = 0x1 inverted clock polarity. 28 invert_dri_clock rw 0x0 this bit is set to one to invert the dri_clk edge used to shift data into the shift register. normal = 0x0 normal clock polarity. inverted = 0x1 inverted clock polarity. 27 reverse_frame rw 0x0 this bit is set to one to reverse the bit order of the 18- bit frames received from the digital radio. normal = 0x0 normal clock polarity. reversed = 0x1 inverted clock polarity. free datasheet http:/// STMP36XX official product documentation 5/3/06 704 chapter 28: digital radio interface (dri) 5-36xx-d1-1.02-050306 description: this register provides access to variou s internal states and controls that are used in diagnostic modes of operati on. note: when the invert_pilot, invert_attention, invert_dri_data, invert_dri_clock or reverse_frame bits are set to one, the dma should not be used to kick off digi- tal radio interface transfers. instead, soft ware should manually set the run bit after the dma is initialized an d the values in debug1 have been established. example: fram = hw_dri_debug1.swizzeled_frame; // then pilot peak is set for this frame; dri xml revision: 1.36 26:18 rsvd1 ro 0x0 always set this bit field to zero. 17:0 swizzled_frame ro 0x0000 current state of frame synchronizing register received from the digital radio receiver as swizzled by the various insurance flip bits. table 925. hw_dri_debug 1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 705 29. low-resolution adc an d touch-screen interface this chapter describes the low-resolution analog-to-digital converters and touch- screen interface included on the STMP36XX. it includes sections on scheduling con- versions and delay channels. programmable registers are described in section 29.5 . 29.1. overview the eight-channel low-resolution adc (lra dc) block is used for voltage measure- ment. figure 129 shows a block diagram of the lradc. six channels are available for general use. ? one channel is dedicated to measure the voltage on the batt pin (lradc7) and can be used to sense the amount of battery life remaining. ? one channel is dedicated to measuring the voltage on the vddio rail (lradc6). and is used to calibrate the vo ltage levels measured on the auxiliary channels. ? the other channels, lradc0?lradc5 , measure the voltage on the six application-dependen t lradc pins. the auxiliary channels ca n be used for a variety of different uses, including a resistor-based wired remote control, temperature sensing, touch screen, etc. lradc lradc programmable registers arm core ahb slave ahb shared dma ahb master apbx master apbx ahb-to-apbx bridge sram apbx clock domain state machines and logic xtal/4 clock domain state machines and logic 8-channel lradc touch-screen controller temp-sensor controller lradc_pins[5:0] figure 129. low-resolution adc and touch-screen interface block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 706 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 the lradc has 12 bits of resolution and an absolute accuracy of 2%. all channels sample on the same divided clock rate from the 24.0-mhz crystal clock. the lradc controller includes an integrated touch-screen controller with drive volt- age generation for touch-screen coordinate measurement as well as a touch-detec- tion interrupt circuit. the lradc controller also contains four delay control channels that can be used to automatically time and schedule control events within the lradc. all eight channels of the lradc share a common successive approximation style analog-to-digital converter through a common analog mux front end (see figure 130 ). the batt pin has a built-in 2:1 voltage divider on its analog multiplexor input, so that it can measure battery voltages that are at a higher potential than the vddio rail. all other channel inputs are restricted by the vddio rail voltage. the touch-screen driver was designed to dr ive typical touch-screen impedances of 200?900 ohm (measured across x or y terminals). however, it should work for higher impedance touch-screens as well. the touch-detect feature may not work reliably for touchscreen impedances greater than 20 kohm (40 kohm total imped- ance across x and y dimensions). for higher impedance touch-screens, it may be necessary to use the lradc to sample ?xplus? to determine a touch event, rather than using the touch-detect feature. the lradc channels 0 and 1 have optional current source outputs to allow these channels to be used with an external th ermistor for temperature sensing. the con- trols for these current sources are in lradc_ctrl2. the current source values can be changed to allow significant temperature sensing range. the currents are derived using the on-chip 1% accurate bandgap voltage reference and the accurate external 620-ohm resistor. the bandgap voltage is accurate to 1% and 620-ohm external resistor should also be 1% accurate. with the addition of current mirror errors, the total error of the temperature sensor current sources should be typically within 3%. most thermistors are no more than 5% accurate, so this level of current source accuracy is acceptable to almost all applications. 29.2. scheduling conversions the apb-x clock domain logic schedules conversions on a per channel basis and handles interrupt processing back to the cpu. each of the eight channels has its own interrupt request enable bit and it s own interrupt request status bit. there is a schedule request bit for each channel, hw_lradccsr0_schedule. setting this bit causes the lradc to sche dule a conversion for that channel. each channel schedule bit is sequentially chec ked and, if scheduled, causes a conver- sion. the schedule bit is cleared upon completion of a successive approximation conversion, and its corresponding interrupt request status bit is set. thus, software controls how often a conversion is reques ted. as each scheduled channel is con- verted, its interrupt status bit is set and its schedule bit is reset. there is a mecha- nism to continuously reschedule a conversion for a particular channel. with set/clear/toggle addressing modes, independent threads can request conver- sions without needing any information from unrelated threads using other channels. setting a schedule bit can be performed in an atomic way. setting a ?gang? of four channel-schedule bits can also be perf ormed atomically. the lradc scheduler is round-robin. it snapshots all schedule bits at once, and then processes them in sequence until all are converted. it then monitors the schedule bits. if any schedule free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 707 bits are set, it snapshots them and starts a new conversion operation for all sched- uled channels. thus, one can set the schedule bits for four channels on the same clock edge. the channel with the largest channel number is converted last and has its interrupt status bit set last. if that channe l is the only one of the four with an inter- rupt enable bit set, then it interrupts the arm after all four channels have been con- verted, effectively ganging four channels together. lradc7 ( batt ) analog mux 12-bit dac lradc6 ( vddio ) lradc0 lradc1 lradc3 lradc5 lradc4 lradc2 + - xtalsar state machine pwrdwn apbx clk state machine apbxclk = xtal_clk/n vddio + - touch_detect 100k ? vts_pu ~ 1.85v x+ x- y- y+ drive_yplus drive_xminus drive_xplus drive_yminus softpu_xplus vts_pu temp_isrc1[3:0] temp_isrc0[3:0] 50 k ? 50 k ? 50 k ? 50 k ? 1/2 clkdiv (1:4,1:6,1:8,1:12) 0 1 5 3 2 4 6 7 8-15 sigmatel internal test points 24.0 mhz channel 6 active li-ion mode channel 7 active figure 130. low-resolution adc successive approximation unit free datasheet http:/// STMP36XX official product documentation 5/3/06 708 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 29.3. delay channels to minimize the interrupt load on the arm processor, four delay channels are pro- vided. each has an 11-bit counter that in crements at 2 khz. a delay channel can be kicked off either by an arm store instruction or at the completion of a delay channel time out. at time-out, each channel has the option of kicking off any combination of lradc conversions, as well as any combination of delay channels. consider the case of a touch-screen that requires 4 x oversampling of its coordinate values. further, suppose you wish to receive an oversampled x or y coordinate approximately every 5 ms and that the oversampling should be spaced at 1-ms intervals. ? in the touch-screen, first select either x or y drive, then setup the appropriate lradc. ? in setting up the lradc, clear the accumu lator associated with it by setting the accumulate bit and set the num_samples field to 3 (4 samples before interrupt request). ? next, setup two delay channels. ? delay channel 1 is set to delay 1 ms (delay = 1, two ticks) and then kick the schedule bit for lradc 4. its loop_count bit field is also set to 3, so that four kicks of lradc 4 occur, each spaced by 1 ms. ? delay channel 0 is set to delay 1 ms with loop_count = 0, i.e., one time. its triger_delays field is set to tr igger delay channel 1 when it times out. the isr routine kicks off delay channel 0 immediately before it does its return from in terrupt. another interrupt (lradc4_irq) is asserted once the entire 4x oversample data captur e is complete. a sample timeline for such a sequence is shown in figure 131 . free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 709 warning : the pad esd protection limits maximum voltage on all lradc inputs. the batt lradc is specifically designed to handle higher voltages, but lradc1? lradc7 inputs are limited to vddio. 29.4. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. touch-screen isr: 1. sets y+,y- drive and clears lradc4 acc. 2. set delay channel 1 for lradc4. 3. kicks delay channel 0. 4. return from interrupt. touchscreenirq lradc4irq kick delaychannel_0 delaychannel_0 kicks delaychannel1 delaychannel_1 kicks lradc4_x+ delaychannel_1 kicks lradc4_x+ delaychannel_1 kicks lradc4_x+ delaychannel_1 kicks lradc4_x+ delay channel 0 (touch-screen settling time): 1. times out. 2. kicks delay channel 1. delay channel 1 oversample intervals: 1. times out. 2. kicks lradc4 (x+ sample). 3. repeats 3 more times. final conversion sets irq. figure 131. using delay channels to oversample a touch-screen free datasheet http:/// STMP36XX official product documentation 5/3/06 710 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 29.5. programmable registers the following programmable registers are available to software for controlling and using the low-resolution analog-to-digital converters. 29.5.1. lradc control register 0 description the lradc control register 0 provides ov erall control of the eight low-resolution analog-to-digital converters. hw_lradc_ctrl0 0x80050000 hw_lradc_ctrl0_set 0x80050004 hw_lradc_ctrl0_clr 0x80050008 hw_lradc_ctrl0_tog 0x8005000c table 926. hw_lradc_ctrl0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate rsrvd2 onchip_groundref touch_detect_enable yminus_enable xminus_enable yplus_enable xplus_enable rsrvd1 schedule table 927. hw_lradc_ctrl 0 bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 when set to one, this bit causes a reset to the entire lradc block. in addition, it turns off the converter clock and powers down the analog portion of the lradc. set this bit to zero for normal operation. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. 29:22 rsrvd2 ro 0x0 reserved 21 onchip_groundref rw 0x0 set this bit to one to use the on-chip ground as reference for conversions. off = 0x0 turn it off. on = 0x1 turn it on. 20 touch_detect_enable rw 0x0 set this bit to one to enable the touch-panel touch detector. off = 0x0 turn it off. on = 0x1 turn it on. 19 yminus_enable rw 0x0 set this bit to one to enable the yminus pulldown on the lradc5 pin. off = 0x0 turn it off. on = 0x1 turn it on. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 711 description: the lradc control register provides control over the shared eight-channel lradc converter. it allows software to independently schedule conversion cycles on any number of any size subsets of the ei ght channels. in addition, it allows soft- ware to manage the interrupt reporting for the channel conversion sets. example: bw_lradc_ctrl0_yplus_enable(bv_lradc_ctrl0_yplus_enable__on); 29.5.2. lradc control register 1 description the lradc control register 1 provides ov erall control of the eight low-resolution analog-to-digital converters. hw_lradc_ctrl1 0x80050010 hw_lradc_ctrl1_set 0x80050014 hw_lradc_ctrl1_clr 0x80050018 hw_lradc_ctrl1_tog 0x8005001c 18 xminus_enable rw 0x0 set this bit to one to enable the xminus pulldown on the lradc4 pin. off = 0x0 turn it off. on = 0x1 turn it on. 17 yplus_enable rw 0x0 set this bit to one to enable the yplus pullup on the lradc3 pin. both hw_lradc_ctrl3_force_analog_pwup and hw_lradc_ctrl3_pwd40ua_pwup must be set to one for this switch to turn on. off = 0x0 turn it off. on = 0x1 turn it on. 16 xplus_enable rw 0x0 set this bit to one to enable the xplus pullup on the lradc2 pin. both hw_lradc_ctrl3_force_analog_pwup and hw_lradc_ctrl3_pwd40ua_pwup must be set to one for this switch to turn on. off = 0x0 turn it off. on = 0x1 turn it on. 15:8 rsrvd1 ro 0x00 reserved 7:0 schedule rw 0x00 setting a bit to one schedules the corresponding lradc channel to be converted. when the conversion of a scheduled channel is completed, the corresponding schedule bit is reset by the hardware and the corresponding interrupt request is set to one. thus, any thread can request a conversion asynchronously from any other thread. table 927. hw_lradc_ctrl 0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 712 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 table 928. hw_lradc_ctrl1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 touch_detect_irq_en lradc7_irq_en lradc6_irq_en lradc5_irq_en lradc4_irq_en lradc3_irq_en lradc2_irq_en lradc1_irq_en lradc0_irq_en rsrvd1 touch_detect_irq lradc7_irq lradc6_irq lradc5_irq lradc4_irq lradc3_irq lradc2_irq lradc1_irq lradc0_irq table 929. hw_lradc_ctrl 1 bit field descriptions bits label rw reset definition 31:25 rsrvd2 ro 0x00 reserved 24 touch_detect_irq_en rw 0x0 set to one to enable an interrupt for the touch detector comparator. disable = 0x0 disable interrupt request. enable = 0x1 enable interrupt request. 23 lradc7_irq_en rw 0x0 set to one to enable an interrupt for channel 7 (batt) conversions. disable = 0x0 disable interrupt request. enable = 0x1 enable interrupt request. 22 lradc6_irq_en rw 0x0 set to one to enable an interrupt for channel 6 (vddio) conversions. disable = 0x0 disable interrupt request. enable = 0x1 enable interrupt request. 21 lradc5_irq_en rw 0x0 set to one to enable an interrupt for channel 5 conversions. disable = 0x0 disable interrupt request. enable = 0x1 enable interrupt request. 20 lradc4_irq_en rw 0x0 set to one to enable an interrupt for channel 4 conversions. disable = 0x0 disable interrupt request. enable = 0x1 enable interrupt request. 19 lradc3_irq_en rw 0x0 set to one to enable an interrupt for channel 3 conversions. disable = 0x0 disable interrupt request. enable = 0x1 enable interrupt request. 18 lradc2_irq_en rw 0x0 set to one to enable an interrupt for channel 2 conversions. disable = 0x0 disable interrupt request. enable = 0x1 enable interrupt request. 17 lradc1_irq_en rw 0x0 set to one to enable an interrupt for channel 1 conversions. disable = 0x0 disable interrupt request. enable = 0x1 enable interrupt request. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 713 16 lradc0_irq_en rw 0x0 set to one to enable an interrupt for channel 0 conversions. disable = 0x0 disable interrupt request. enable = 0x1 enable interrupt request. 15:9 rsrvd1 ro 0x00 reserved 8 touch_detect_irq rw 0x0 this bit is set to one upon detection of a touch condition in the touch panel attached to lradc2- lradc5. it is anded with its corresponding interrupt enable bit to request an interrrupt. once set by the conversion hardware, this bit remains set until cleared by software. clear = 0x0 interrupt request cleared. pending = 0x1 interrupt request pending. 7 lradc7_irq rw 0x0 this bit is set to one upon completion of a scheduled conversion for channel 7 (batt). it is anded with its corresponding interrupt enable bit to request an interrrupt. once set by the conversion hardware, this bit remains set until cleared by software. clear = 0x0 interrupt request cleared. pending = 0x1 interrupt request pending. 6 lradc6_irq rw 0x0 this bit is set to one upon completion of a scheduled conversion for channel 6 (vddio). it is anded with its corresponding interrupt enable bit to request an interrrupt. once set by the conversion hardware, this bit remains set until cleared by software. clear = 0x0 interrupt request cleared. pending = 0x1 interrupt request pending. 5 lradc5_irq rw 0x0 this bit is set to one upon completion of a scheduled conversion for channel 5. it is anded with its corresponding interrupt enable bit to request an interrrupt. once set by the conversion hardware, this bit remains set until cleared by software. clear = 0x0 interrupt request cleared. pending = 0x1 interrupt request pending. 4 lradc4_irq rw 0x0 this bit is set to one upon completion of a scheduled conversion for channel 4. it is anded with its corresponding interrupt enable bit to request an interrrupt. once set by the conversion hardware, this bit remains set until cleared by software. clear = 0x0 interrupt request cleared. pending = 0x1 interrupt request pending. 3 lradc3_irq rw 0x0 this bit is set to one upon completion of a scheduled conversion for channel 3. it is anded with its corresponding interrupt enable bit to request an interrrupt. once set by the conversion hardware, this bit remains set until cleared by software. clear = 0x0 interrupt request cleared. pending = 0x1 interrupt request pending. table 929. hw_lradc_ctrl 1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 714 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 description: the lradc control register 1 provides control over the shared eight-channel lradc converter. it allows software to independently schedule conversion cycles on any number of any size subsets of the ei ght channels. in addition, it allows soft- ware to manage the interrupt reporting for the channel conversion sets. example: if(hw_lradc_ctrl1.touch_detect_irq == bv_lradc_ctrl1_touch_detect_irq__pending){ // then handle the interrupt. hw_lradc_ctrl1.touch_detect_irq_en = bv_lradc_ctrl1_touch_detect_irq_en__disable; } 29.5.3. lradc control register 2 description the lradc control register 2 provides ov erall control of the eight low-resolution analog-to-digital converters. hw_lradc_ctrl2 0x80050020 hw_lradc_ctrl2_set 0x80050024 hw_lradc_ctrl2_clr 0x80050028 hw_lradc_ctrl2_tog 0x8005002c 2 lradc2_irq rw 0x0 this bit is set to one upon completion of a scheduled conversion for channel 2. it is anded with its corresponding interrupt enable bit to request an interrrupt. once set by the conversion hardware, this bit remains set until cleared by software. clear = 0x0 interrupt request cleared. pending = 0x1 interrupt request pending. 1 lradc1_irq rw 0x0 this bit is set to one upon completion of a scheduled conversion for channel 1. it is anded with its corresponding interrupt enable bit to request an interrrupt. once set by the conversion hardware, this bit remains set until cleared by software. clear = 0x0 interrupt request cleared. pending = 0x1 interrupt request pending. 0 lradc0_irq rw 0x0 this bit is set to one upon completion of a scheduled conversion for channel 0. it is anded with its corresponding interrupt enable bit to request an interrrupt. once set by the conversion hardware, this bit remains set until cleared by software. clear = 0x0 interrupt request cleared. pending = 0x1 interrupt request pending. table 929. hw_lradc_ctrl 1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 715 table 930. hw_lradc_ctrl2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 divide_by_two lradc6select lradc7select rsrvd2 temp_sensor_ienable1 temp_sensor_ienable0 temp_isrc1 temp_isrc0 table 931. hw_lradc_ctrl 2 bit field descriptions bits label rw reset definition 31:24 divide_by_two rw 0x0 each bit of this eight bit field corresponds to a channel of an lradc. setting the bit to one caused the a/d converter to use its analog divide-by-two circuit for the conversion of the corresponding channel. 23:20 lradc6select rw 0x6 this bit field selects which analog mux input is used for conversion on lradc channel 6 (vddio). channel0 = 0x0 channel1 = 0x1 channel2 = 0x2 channel3 = 0x3 channel4 = 0x4 channel5 = 0x5 channel6 = 0x6 vddio channel7 = 0x7 battery channel8 = 0x8 pmos thin channel9 = 0x9 nmos thin channel10 = 0xa nmos thick channel11 = 0xb pmos thick channel12 = 0xc channel13 = 0xd channel14 = 0xe channel15 = 0xf 19:16 lradc7select rw 0x7 this bit field selects which analog mux input is used for conversion on lradc channel 7 (batt). channel0 = 0x0 channel1 = 0x1 channel2 = 0x2 channel3 = 0x3 channel4 = 0x4 channel5 = 0x5 channel6 = 0x6 vddio channel7 = 0x7 battery channel8 = 0x8 pmos thin channel9 = 0x9 nmos thin channel10 = 0xa nmos thick channel11 = 0xb pmos thick channel12 = 0xc channel13 = 0xd channel14 = 0xe channel15 = 0xf 15:10 rsrvd2 ro 0x00 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 716 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 description: the lradc control register 2 provides control over the shared eight-channel lradc converter. it allows software to independently schedule conversion cycles on any number of any size subsets of the ei ght channels. in addition, it allows soft- ware to manage the interrupt reporting for the channel conversion sets. example: bw_lradc_ctrl2_temp_sensor_ienable1(bv_lradc_ctrl2_temp_sensor_ienable1__disable); 9 temp_sensor_ienable1 rw 0x0 set this bit to one to enable the current source onto lradc1. warning: temperature sensor current source requires vddio greater than 2.9 v for correct operation. disable = 0x0 disable temperature sensor current source. enable = 0x1 enable temperature sensor current source. 8 temp_sensor_ienable0 rw 0x0 set this bit to one to enable the current source onto lradc0. warning: temperature sensor current source requires vddio greater than 2.9 v for correct operation. disable = 0x0 disable temperature sensor current source. enable = 0x1 enable temperature sensor current source. 7:4 temp_isrc1 rw 0x0 this four-bit field encodes the current magnitude to inject into an external temperature sensor attached to lradc1. 300 = 0xf 300ua. 280 = 0xe 280ua. 260 = 0xd 260ua. 240 = 0xc 240ua. 220 = 0xb 220ua. 200 = 0xa 200ua. 180 = 0x9 180ua. 160 = 0x8 160ua. 140 = 0x7 140ua. 120 = 0x6 120ua. 100 = 0x5 100ua. 80 = 0x4 80ua. 60 = 0x3 60ua. 40 = 0x2 40ua. 20 = 0x1 20ua. zero = 0x0 0ua. 3:0 temp_isrc0 rw 0x0 this four-bit field encodes the current magnitude to inject into an external temperature sensor attached to lradc0. 300 = 0xf 300ua. 280 = 0xe 280ua. 260 = 0xd 260ua. 240 = 0xc 240ua. 220 = 0xb 220ua. 200 = 0xa 200ua. 180 = 0x9 180ua. 160 = 0x8 160ua. 140 = 0x7 140ua. 120 = 0x6 120ua. 100 = 0x5 100ua. 80 = 0x4 80ua. 60 = 0x3 60ua. 40 = 0x2 40ua. 20 = 0x1 20ua. zero = 0x0 0ua. table 931. hw_lradc_ctrl 2 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 717 29.5.4. lradc control register 3 description the lradc control register 3 specifies t he voltages at which a touch-detect inter- rupt is generated. hw_lradc_ctrl3 0x80050030 hw_lradc_ctrl3_set 0x80050034 hw_lradc_ctrl3_clr 0x80050038 hw_lradc_ctrl3_tog 0x8005003c table 932. hw_lradc_ctrl3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd5 discard force_analog_pwup force_analog_pwdn force_pwd40ua_pwup force_pwd40ua_pwdn rsrvd4 vdd_filter rsrvd3 add_cap2inputs rsrvd2 cycle_time rsrvd1 high_time remove_cfilt short_rfilt delay_clock invert_clock table 933. hw_lradc_ctrl 3 bit field descriptions bits label rw reset definition 31:26 rsrvd5 ro 0x0 reserved 25:24 discard rw 0x0 this bit field specifies the number of samples to discard whenever the lradc analog is first powered up. 00= discard first 3 samples. 01= discard first sample. 10= discard first 2 samples. 11= discard first 3 samples. 1_sample = 0x1 discard first sample before first capture. 2_samples = 0x2 discard 2 samples before first capture. 3_samples = 0x3 discard 3 samples before first capture. 23 force_analog_pwup rw 0x0 set this bit to zero for normal operation. setting it to one forces an analog power up, regardless of where the digital state machine may be. off = 0x0 turn it off. on = 0x1 turn it on. 22 force_analog_pwdn rw 0x0 set this bit to zero for normal operation. setting it to one forces an analog power down, regardless of where the digital state machine may be. on = 0x0 turn it on. off = 0x1 turn it off. free datasheet http:/// STMP36XX official product documentation 5/3/06 718 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 21 force_pwd40ua_pwup rw 0x0 set to one to force a power up of the 40 microamp bias current source. set to zero for normal operation. this bit was added due to concerns that turning the 40ua bias current on and off at audible frequency rate, say 1ksps, might cause audible tones to appear during playback. lab experiments show that this concern was unfounded. therefore, this bit should not be set without approval from sigmatel. off = 0x0 turn it off. on = 0x1 turn it on. 20 force_pwd40ua_pwdn rw 0x0 set to one to force a power down of the 40 microamp bias current source. set to zero for normal operation. on = 0x0 turn it on. off = 0x1 turn it off. 19:18 rsrvd4 ro 0x0 reserved 17:16 vdd_filter rw 0x0 this bit field controls a test function that adds additional series resistance to the lradc vdd path to further filter the vdd noise. 00= 0 ohms 0db 01= 100 ohms 5db 10= 250 ohms 9.5db 11= 500 ohms 13.5db 0ohms = 0x0 0 ohms additional vdd filter. 100ohms = 0x1 100 ohms additional vdd filter. 250ohms = 0x2 250 ohms additional vdd filter. 5000ohms = 0x3 500 ohms additional vdd filter. 15:14 rsrvd3 ro 0x0 reserved 13:12 add_cap2inputs rw 0x0 this bit field controls a test function that adds additional capacitance to the filter inputs. 00= 0 pf additional cap 01= 0.5 pf 10= 1.0 pf 11= 2.5 pf 0pf = 0x0 0 pf additional capacitance. 0_5pf = 0x1 0.5 pf additional capacitance. 1_0pf = 0x2 1.0 pf additional capacitance. 2_5pf = 0x3 2.5 pf additional capacitance. 11:10 rsrvd2 ro 0x0 reserved 9:8 cycle_time rw 0x0 changes the lradc clock frequency. note: the sample rate is one-thirteenth of the frequency selected here. 00= 6 mhz 01= 4 mhz 10= 3 mhz 11= 2 mhz 6mhz = 0x0 6-mhz clock. 4mhz = 0x1 4-mhz clock. 3mhz = 0x2 3-mhz clock. 2mhz = 0x3 2-mhz clock. 7:6 rsrvd1 ro 0x0 reserved table 933. hw_lradc_ctrl 3 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 719 description: the lradc touch detect control and status register controls the voltage at which a touch detection interrupt is generated. th is register also contains the interrupt request status bit and enable bit for the touch detection interrupt request to the cpu's irq interrupt input. example: bw_lradc_ctrl3_high_time(bv_lradc_ctrl3_high_time__83ns); bw_lradc_ctrl3_invert_clock(bv_lradc_ctrl3_invert_clock__normal); 29.5.5. lradc status register description the lradc status register returns vari ous read-only status bit field values. hw_lradc_status 0x80050040 hw_lradc_status_set 0x80050044 hw_lradc_status_clr 0x80050048 hw_lradc_status_tog 0x8005004c 5:4 high_time rw 0x0 changes the duty cycle (time high) for the lradc clock. 00= 41.66 ns 01= 83.33 ns 10= 125 ns 11= 250 ns 42ns = 0x0 duty cycle high time to 41.66 ns. 83ns = 0x1 duty cycle high time to 83.33 ns. 125ns = 0x2 duty cycle high time to 125 ns. 250ns = 0x3 duty cycle high time to 250 ns. 3 remove_cfilt rw 0x0 changes filtering on the output of the d/a converter. off = 0x0 turn it off. on = 0x1 turn it on. 2 short_rfilt rw 0x0 changes filtering on the output of the d/a converter. off = 0x0 turn it off. on = 0x1 turn it on. 1 delay_clock rw 0x0 set this bit to one to delay the 24-mhz clock used in the lradc even further away from the predominant rising edge used within the digital section. the delay inserted is approximately 400 ps. normal = 0x0 normal operation, that is no delay. delayed = 0x1 delay the clock. 0 invert_clock rw 0x0 set this bit field to one to invert the 24-mhz clock where it comes into the lradc analog section. this moves it away from the predominant digital rising edge. setting this bit to one causes the a/d converter to run from the negative edge of the divided clock, effectively shifting the conversion point away from the edge used by the dcdc converter. normal = 0x0 run the clock in normal (not inverted) mode. invert = 0x1 invert the clock. table 933. hw_lradc_ctrl 3 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 720 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 description: table 934. hw_lradc_status 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd3 temp1_present temp0_present touch_panel_present channel7_present channel6_present channel5_present channel4_present channel3_present channel2_present channel1_present channel0_present rsrvd2 touch_detect_raw table 935. hw_lradc_status bit field descriptions bits label rw reset definition 31:27 rsrvd3 ro 0x0 reserved 26 temp1_present ro 0x1 this read-only bit returns a one when the temperature sensor 1 current source is present on the chip. 25 temp0_present ro 0x1 this read-only bit returns a one when the temperature sensor 0 current source is present on the chip. 24 touch_panel_present ro 0x1 this read-only bit returns a one when the touch panel controller function is present on the chip. 23 channel7_present ro 0x1 this read-only bit returns a one when the lradc channel 7 converter function is present on the chip. 22 channel6_present ro 0x1 this read-only bit returns a one when the lradc channel 6 converter function is present on the chip. 21 channel5_present ro 0x1 this read-only bit returns a one when the lradc channel 5 converter function is present on the chip. 20 channel4_present ro 0x1 this read-only bit returns a one when the lradc channel 4 converter function is present on the chip. 19 channel3_present ro 0x1 this read-only bit returns a one when the lradc channel 3 converter function is present on the chip. 18 channel2_present ro 0x1 this read-only bit returns a one when the lradc channel 2 converter function is present on the chip. 17 channel1_present ro 0x1 this read-only bit returns a one when the lradc channel 1 converter function is present on the chip. 16 channel0_present ro 0x1 this read-only bit returns a one when the lradc channel 0 converter function is present on the chip. 15:1 rsrvd2 ro 0x0 reserved 0 touch_detect_raw ro 0x0 this read-only bit shows the status of the touch detect comparator in the analog section. open = 0x0 no contact, i.e., open connection. hit = 0x1 someone is touching the panel. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 721 the status register returns the value of a number of status bit fields. example: if(hw_lradc_status.touch_detect_raw == bv_lradc_status_touch_detect_raw__hit){ // then something is touching the screen. } 29.5.6. lradc 0 result register description the lradc 0 result register returns the 12-bit result for low-resolution analog-to- digital converter channel 0. hw_lradc_ch0 0x80050050 hw_lradc_ch0_set 0x80050054 hw_lradc_ch0_clr 0x80050058 hw_lradc_ch0_tog 0x8005005c description: table 936. hw_lradc_ch0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 toggle rsrvd2 accumulate num_samples rsrvd1 value table 937. hw_lradc_ch0 bit field descriptions bits label rw reset definition 31 toggle rw 0x0 this bit toggles at every completed conversion, so that software can detect a missed or duplicated sample. 30 rsrvd2 ro 0x0 reserved 29 accumulate rw 0x0 set this bit to one to add successive samples to the 18-bit accumulator. 28:24 num_samples rw 0x0 this bit field contains the number of conversion cycles to sum together before report ing operation complete interrupt status. set this field to zero for a single conversion per interrupt. 23:18 rsrvd1 ro 0x000 reserved 17:0 value rw 0x0000 this bit field contains the most recent 12-bit conversion value for this channel. if automatic oversampling is enabled, this bit field contains the sum of the most recent n oversampled values, where n is set in the num_samples field for this channel. when 32 full-scale samples are added together, the 12-bit results can sum up to 256 k. software is responsible for dividing this value by the number of samples summed together. software must clear this register in preparation for a mult i-cycle accumulation. free datasheet http:/// STMP36XX official product documentation 5/3/06 722 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 the lradc 0 result register contains the most recent conversion results for one channel of the lradc. note that each channel can be converted at an independent rate. the toggle bit is used to debug missed conversion cycles. when using oversampling, the channel must be individualy scheduled for conversion n times for when n samples are required before an interrupt is generated. this is most easily accomplished by using one of the lradc delay channels. example: if (hw_lradc_chn(0).toggle == 1) { } // toggle is high. // ... unsigned long channelaverage; hw_lradc_chn_wr(0, (bf_lradc_chn_accumulate(1) | // enable accumulation mode. bf_lradc_chn_num_samples(5) | // set samples to five. bf_lradc_chn_value(0) ) ); // clear accumulator. // ... setup delay channel (see hw_lradc_delay0 through 3) while (hw_lradc_ctrl1.lradc0_irq != bv_lradc_ctrl1_lradc0_irq__pending) { // wait for interrupt. } channelaverage = hw_lradc_chn(0).value / 5; 29.5.7. lradc 1 result register description the lradc 1 result register returns the 12-bit result for low-resolution analog-to- digital converter channel 1. hw_lradc_ch1 0x80050060 hw_lradc_ch1_set 0x80050064 hw_lradc_ch1_clr 0x80050068 hw_lradc_ch1_tog 0x8005006c table 938. hw_lradc_ch1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 toggle rsrvd2 accumulate num_samples rsrvd1 value table 939. hw_lradc_ch1 bit field descriptions bits label rw reset definition 31 toggle rw 0x0 this read-only bit toggles at every completed conversion, so that software can detect a missed or duplicated sample. 30 rsrvd2 ro 0x0 reserved 29 accumulate rw 0x0 set this bit to one to add successive samples to the 18-bit accumulator. 28:24 num_samples rw 0x0 this bit field contains the number of conversion cycles to sum together before report ing operation complete interrupt status. set this field to zero for a single conversion per interrupt. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 723 description: the lradc 1 result register contains the most recent conversion results for one channel of the lradc. note that each channel can be converted at an independent rate. the toggle bit is used to debug missed conversion cycles. when using oversampling, the channel must be individualy scheduled for conversion n times for when n samples are required before an interrupt is generated. this is most easily accomplished by using one of the lradc delay channels. example: if (hw_lradc_chn(1).toggle == 1) { } // toggle is high. // ... unsigned long channelaverage; hw_lradc_chn_wr(1, (bf_lradc_chn_accumulate(1) | // enable accumulation mode. bf_lradc_chn_num_samples(5) | // set samples to five. bf_lradc_chn_value(0) ) ); // clear accumulator. // ... setup delay channel (see hw_lradc_delay0 through 3) while (hw_lradc_ctrl1.lradc1_irq != bv_lradc_ctrl1_lradc1_irq__pending) { // wait for interrupt. } channelaverage = hw_lradc_chn(1).value / 5; 29.5.8. lradc 2 result register description the lradc 2 result register returns the 12-bit result for low-resolution analog-to- digital converter channel 2. hw_lradc_ch2 0x80050070 hw_lradc_ch2_set 0x80050074 hw_lradc_ch2_clr 0x80050078 hw_lradc_ch2_tog 0x8005007c 23:18 rsrvd1 ro 0x000 reserved 17:0 value rw 0x0000 this bit field contains the most recent 12-bit conversion value for this channel. if automatic oversampling is enabled, this bit field contains the sum of the most recent n oversampled values, where n is set in the num_samples field for this channel. when 32 full-scale samples are added together, the 12-bit results can sum up to 256 k. software is responsible for dividing this value by the number of samples summed together. software must clear this register in preparation for a mult i-cycle accumulation. table 940. hw_lradc_ch2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 toggle rsrvd2 accumulate num_samples rsrvd1 value table 939. hw_lradc_ch1 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 724 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 description: the lradc 2 result register contains the most recent conversion results for one channel of the lradc. note that each channel can be converted at an independent rate. the toggle bit is used to debug missed conversion cycles. when using oversampling, the channel must be individualy scheduled for conversion n times for when n samples are required before an interrupt is generated. this is most easily accomplished by using one of the lradc delay channels. example: if (hw_lradc_chn(2).toggle == 1) { } // toggle is high. // ... unsigned long channelaverage; hw_lradc_chn_wr(2, (bf_lradc_chn_accumulate(1) | // enable accumulation mode. bf_lradc_chn_num_samples(5) | // set samples to five. bf_lradc_chn_value(0) ) ); // clear accumulator. // ... setup delay channel (see hw_lradc_delay0 through 3) while (hw_lradc_ctrl1.lradc2_irq != bv_lradc_ctrl1_lradc2_irq__pending) { // wait for interrupt. } channelaverage = hw_lradc_chn(2).value / 5; 29.5.9. lradc 3 result register description the lradc 3 result register returns the 12-bit result for low-resolution analog-to- digital converter channel 3. hw_lradc_ch3 0x80050080 hw_lradc_ch3_set 0x80050084 hw_lradc_ch3_clr 0x80050088 hw_lradc_ch3_tog 0x8005008c table 941. hw_lradc_ch2 bit field descriptions bits label rw reset definition 31 toggle rw 0x0 this read-only bit toggles at every completed conversion, so that software can detect a missed or duplicated sample. 30 rsrvd2 ro 0x0 reserved 29 accumulate rw 0x0 set this bit to one to add successive samples to the 18-bit accumulator. 28:24 num_samples rw 0x0 this bit field contains the number of conversion cycles to sum together before report ing operation complete interrupt status. set this field to zero for a single conversion per interrupt. 23:18 rsrvd1 ro 0x000 reserved 17:0 value rw 0x0000 this bit field contains the most recent 12-bit conversion value for this channel. if automatic oversampling is enabled, this bit field contains the sum of the most recent n oversampled values, where n is set in the num_samples field for this channel. when 32 full-scale samples are added together, the 12-bit results can sum up to 256 k. software is responsible for dividing this value by the number of samples summed together. software must clear this register in preparation for a mult i-cycle accumulation. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 725 description: the lradc 3 result register contains the most recent conversion results for one channel of the lradc. note that each channel can be converted at an independent rate. the toggle bit is used to debug missed conversion cycles. when using oversampling, the channel must be individualy scheduled for conversion n times for when n samples are required before an interrupt is generated. this is most easily accomplished by using one of the lradc delay channels. example: if (hw_lradc_chn(3).toggle == 1) { } // toggle is high. // ... unsigned long channelaverage; hw_lradc_chn_wr(3, (bf_lradc_chn_accumulate(1) | // enable accumulation mode. bf_lradc_chn_num_samples(5) | // set samples to five. bf_lradc_chn_value(0) ) ); // clear accumulator. // ... setup delay channel (see hw_lradc_delay0 through 3) while (hw_lradc_ctrl1.lradc3_irq != bv_lradc_ctrl1_lradc3_irq__pending) table 942. hw_lradc_ch3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 toggle rsrvd2 accumulate num_samples rsrvd1 value table 943. hw_lradc_ch3 bit field descriptions bits label rw reset definition 31 toggle rw 0x0 this read-only bit toggles at every completed conversion, so that software can detect a missed or duplicated sample. 30 rsrvd2 ro 0x0 reserved 29 accumulate rw 0x0 set this bit to one to add successive samples to the 18-bit accumulator. 28:24 num_samples rw 0x0 this bit field contains the number of conversion cycles to sum together before report ing operation complete interrupt status. set this field to zero for a single conversion per interrupt. 23:18 rsrvd1 ro 0x000 reserved 17:0 value rw 0x0000 this bit field contains the most recent 12-bit conversion value for this channel. if automatic oversampling is enabled, this bit field contains the sum of the most recent n oversampled values, where n is set in the num_samples field for this channel. when 32 full-scale samples are added together, the 12-bit results can sum up to 256 k. software is responsible for dividing this value by the number of samples summed together. software must clear this register in preparation for a mult i-cycle accumulation. free datasheet http:/// STMP36XX official product documentation 5/3/06 726 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 { // wait for interrupt. } channelaverage = hw_lradc_chn(3).value / 5; 29.5.10. lradc 4 result register description the lradc 4 result register returns the 12-bit result for low-resolution analog-to- digital converter channel 4. hw_lradc_ch4 0x80050090 hw_lradc_ch4_set 0x80050094 hw_lradc_ch4_clr 0x80050098 hw_lradc_ch4_tog 0x8005009c description: table 944. hw_lradc_ch4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 toggle rsrvd2 accumulate num_samples rsrvd1 value table 945. hw_lradc_ch4 bit field descriptions bits label rw reset definition 31 toggle rw 0x0 this read-only bit toggles at every completed conversion, so that software can detect a missed or duplicated sample. 30 rsrvd2 ro 0x0 reserved 29 accumulate rw 0x0 set this bit to one to add successive samples to the 18-bit accumulator. 28:24 num_samples rw 0x0 this bit field contains the number of conversion cycles to sum together before report ing operation complete interrupt status. set this field to zero for a single conversion per interrupt. 23:18 rsrvd1 ro 0x000 reserved 17:0 value rw 0x0000 this bit field contains the most recent 12-bit conversion value for this channel. if automatic oversampling is enabled, this bit field contains the sum of the most recent n oversampled values, where n is set in the num_samples field for this channel. when 32 full-scale samples are added together, the 12-bit results can sum up to 256 k. software is responsible for dividing this value by the number of samples summed together. software must clear this register in preparation for a mult i-cycle accumulation. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 727 the lradc 4 result register contains the most recent conversion results for one channel of the lradc. note that each channel can be converted at an independent rate. the toggle bit is used to debug missed conversion cycles. when using oversampling, the channel must be individualy scheduled for conversion n times for when n samples are required before an interrupt is generated. this is most easily accomplished by using one of the lradc delay channels. example: if (hw_lradc_chn(4).toggle == 1) { } // toggle is high. // ... unsigned long channelaverage; hw_lradc_chn_wr(4, (bf_lradc_chn_accumulate(1) | // enable accumulation mode. bf_lradc_chn_num_samples(5) | // set samples to five. bf_lradc_chn_value(0) ) ); // clear accumulator. // ... setup delay channel (see hw_lradc_delay0 through 3) while (hw_lradc_ctrl1.lradc4_irq != bv_lradc_ctrl1_lradc4_irq__pending) { // wait for interrupt. } channelaverage = hw_lradc_chn(4).value / 5; 29.5.11. lradc 5 result register description the lradc 5 result register returns the 12-bit result for low-resolution analog-to- digital converter channel five. hw_lradc_ch5 0x800500a0 hw_lradc_ch5_set 0x800500a4 hw_lradc_ch5_clr 0x800500a8 hw_lradc_ch5_tog 0x800500ac table 946. hw_lradc_ch5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 toggle rsrvd2 accumulate num_samples rsrvd1 value table 947. hw_lradc_ch5 bit field descriptions bits label rw reset definition 31 toggle rw 0x0 this read-only bit toggles at every completed conversion, so that software can detect a missed or duplicated sample. 30 rsrvd2 ro 0x0 reserved 29 accumulate rw 0x0 set this bit to one to add successive samples to the 18-bit accumulator. 28:24 num_samples rw 0x0 this bit field contains the number of conversion cycles to sum together before report ing operation complete interrupt status. set this field to zero for a single conversion per interrupt. free datasheet http:/// STMP36XX official product documentation 5/3/06 728 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 description: the lradc 5 result register contains the most recent conversion results for one channel of the lradc. note that each channel can be converted at an independent rate. the toggle bit is used to debug missed conversion cycles. when using oversampling, the channel must be individualy scheduled for conversion n times for when n samples are required before an interrupt is generated. this is most easily accomplished by using one of the lradc delay channels. example: if (hw_lradc_chn(5).toggle == 1) { } // toggle is high. // ... unsigned long channelaverage; hw_lradc_chn_wr(5, (bf_lradc_chn_accumulate(1) | // enable accumulation mode. bf_lradc_chn_num_samples(5) | // set samples to five. bf_lradc_chn_value(0) ) ); // clear accumulator. // ... setup delay channel (see hw_lradc_delay0 through 3) while (hw_lradc_ctrl1.lradc5_irq != bv_lradc_ctrl1_lradc5_irq__pending) { // wait for interrupt. } channelaverage = hw_lradc_chn(5).value / 5; 29.5.12. lradc 6 (vddio) result register description the lradc 6 (vddio) result register returns the 12-bit result for low-resolution analog-to-digital converter channel 6 (vddio). hw_lradc_ch6 0x800500b0 hw_lradc_ch6_set 0x800500b4 hw_lradc_ch6_clr 0x800500b8 hw_lradc_ch6_tog 0x800500bc 23:18 rsrvd1 ro 0x000 reserved 17:0 value rw 0x0000 this bit field contains the most recent 12-bit conversion value for this channel. if automatic oversampling is enabled, this bit field contains the sum of the most recent n oversampled values, where n is set in the num_samples field for this channel. when 32 full-scale samples are added together, the 12-bit results can sum up to 256 k. software is responsible for dividing this value by the number of samples summed together. software must clear this register in preparation for a mult i-cycle accumulation. table 948. hw_lradc_ch6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 toggle rsrvd2 accumulate num_samples rsrvd1 value table 947. hw_lradc_ch5 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 729 description: the lradc 6 (vddio) result register co ntains the most recent conversion results for one channel of the lradc. note that each channel can be converted at an inde- pendent rate. the toggle bit is used to debug missed conversion cycles. when using oversampling, the channel must be individualy scheduled for conversion n times for when n samples are required before an interrupt is generated. this is most easily accomplished by using one of the lradc delay channels. example: if (hw_lradc_chn(6).toggle == 1) { } // toggle is high. // ... unsigned long channelaverage; hw_lradc_chn_wr(6, (bf_lradc_chn_accumulate(1) | // enable accumulation mode. bf_lradc_chn_num_samples(5) | // set samples to five. bf_lradc_chn_value(0) ) ); // clear accumulator. // ... setup delay channel (see hw_lradc_delay0 through 3) while (hw_lradc_ctrl1.lradc6_irq != bv_lradc_ctrl1_lradc6_irq__pending) { // wait for interrupt. } channelaverage = hw_lradc_chn(6).value / 5; 29.5.13. lradc 7 (batt) result register description the lradc 7 (batt) result register retu rns the 12-bit result for low-resolution analog-to-digital converter channel 7 (batt). hw_lradc_ch7 0x800500c0 hw_lradc_ch7_set 0x800500c4 hw_lradc_ch7_clr 0x800500c8 hw_lradc_ch7_tog 0x800500cc table 949. hw_lradc_ch6 bit field descriptions bits label rw reset definition 31 toggle rw 0x0 this read-only bit toggles at every completed conversion, so that software can detect a missed or duplicated sample. 30 rsrvd2 ro 0x0 reserved 29 accumulate rw 0x0 set this bit to one to add successive samples to the 18-bit accumulator. 28:24 num_samples rw 0x0 this bit field contains the number of conversion cycles to sum together before report ing operation complete interrupt status. set this field to zero for a single conversion per interrupt. 23:18 rsrvd1 ro 0x000 reserved 17:0 value rw 0x0000 this bit field contains the most recent 12-bit conversion value for this channel. if automatic oversampling is enabled, this bit field contains the sum of the most recent n oversampled values, where n is set in the num_samples field for this channel. when 32 full-scale samples are added together, the 12-bit results can sum up to 256 k. software is responsible for dividing this value by the number of samples summed together. software must clear this register in preparation for a mult i-cycle accumulation. free datasheet http:/// STMP36XX official product documentation 5/3/06 730 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 description: the lradc 7 (batt) result register contains the most recent conversion results for one channel of the lradc. note that each channel can be converted at an inde- pendent rate. the toggle bit is used to debug missed conversion cycles. when using oversampling, the channel must be individualy scheduled for conversion n table 950. hw_lradc_ch7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 toggle testmode_toggle accumulate num_samples rsrvd1 value table 951. hw_lradc_ch7 bit field descriptions bits label rw reset definition 31 toggle rw 0x0 this read-only bit toggles at every completed conversion, so that software can detect a missed or duplicated sample. 30 testmode_toggle ro 0x0 this read-only bit toggles at every completed conversion of interest in test mode so software can synchornize to the desired sample. when the test mode count is loaded with a value of 7, this will toggle every eighth conversion on channel 7. if testmode operation for channel 5 and or 6 are set then the sample rate will be lower for channel 7. 29 accumulate rw 0x0 set this bit to one to add successive samples to the 18 bit accumulator. 28:24 num_samples rw 0x0 this bit field contains the number of conversion cycles to sum together before report ing operation complete interrupt status. set this field to zero for a single conversion per interrupt. 23:18 rsrvd1 ro 0x000 reserved 17:0 value rw 0x0000 this bit field contains the most recent 12-bit conversion value for this channel. if automatic oversampling is enabled, this bit field contains the sum of the most recent n oversampled values, where n is set in the num_samples field for this channel. when 32 full-scale samples are added together, the 12-bit results can sum up to 256 k. software is responsible for dividing this value by the number of samples summed together. software must clear this register in preparation for a mult i-cycle accumulation. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 731 times for when n samples are required before an interrupt is generated. this is most easily accomplished by using one of the lradc delay channels. example: if (hw_lradc_chn(7).toggle == 1) { } // toggle is high. // ... unsigned long channelaverage; hw_lradc_chn_wr(7, (bf_lradc_chn_accumulate(1) | // enable accumulation mode. bf_lradc_chn_num_samples(5) | // set samples to five. bf_lradc_chn_value(0) ) ); // clear accumulator. // ... setup delay channel (see hw_lradc_delay0 through 3) while (hw_lradc_ctrl1.lradc7_irq != bv_lradc_ctrl1_lradc7_irq__pending) { // wait for interrupt. } channelaverage = hw_lradc_chn(7).value / 5; 29.5.14. lradc scheduling delay 0 register description the lradc scheduling delay 0 register controls one delay operation. at the end of this delay, this channel can trigger one or more lradc channels or one or more scheduling delay channels. hw_lradc_delay0 0x800500d0 hw_lradc_delay0_set 0x800500d4 hw_lradc_delay0_clr 0x800500d8 hw_lradc_delay0_tog 0x800500dc table 952. hw_lradc_delay0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 trigger_lradcs rsrvd2 kick trigger_delays loop_count delay table 953. hw_lradc_dela y0 bit field descriptions bits label rw reset definition 31:24 trigger_lradcs rw 0x00 setting a bit in this bit field to one causes the delay controller to trigger the corresponding lradc channel. this trigger occurs when the delay count of this delay channel reaches zero. note that all eight lradc channels can be triggered at the same time. any channel with its corresponding bit set in this field is triggered. the hardware accomplishes this by setting the corresponding bit(s) in hw_lradc_ctrl0_schedule. 23:21 rsrvd2 ro 0x0 reserved 20 kick rw 0x0 setting this bit to one initiates a delay cycle. at the end of that cycle, any trigger_lradcs or trigger_delays will start. free datasheet http:/// STMP36XX official product documentation 5/3/06 732 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 description: the radc scheduling delay 0 register provides control by which lradc chan- nels and delay channels (including itself) may be triggered. the triggering of the selected delay and lradc channel(s) is delayed by the delay field value which counts down on a 2-khz clock. it is possible to use delay channels chained together to configure dependent timing of channel c onversions as in the example provided in introduction to this block. a delay channel may also be configured to trigger itself. in this case, it could be used to simultan eously trigger an lradc channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the delay field. the delay channel is started by setting the kick bit to one. example: hw_lradc_delayn_wr(0, (bf_lradc_delayn_trigger_lradcs(0x05) | // lradc channel 0 and 2 bf_lradc_delayn_kick(1) | // start the delay channel bf_lradc_delayn_trigger_delays(0x1) | // restart delay channel 0 each time bf_lradc_delayn_delay(0x0e45) ) ); // delay 3653 periods of 2 khz clock // ... do other things until the triggered lradc channels report an interrupt. 29.5.15. lradc scheduling delay 1 register description the lradc scheduling delay 1 register controls one delay operation. at the end of this delay, this channel can trigger one or more lradc channels or one or more scheduling delay channels . hw_lradc_delay1 0x800500e0 hw_lradc_delay1_set 0x800500e4 hw_lradc_delay1_clr 0x800500e8 hw_lradc_delay1_tog 0x800500ec 19:16 trigger_delays rw 0x0 setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. this trigger occurs when the delay count of this delay channel reaches zero. note that all four delay channels can be triggered at the same time, including the one that issues the trigger. this can have the effect of automatically retriggering a delay channel. 15:11 loop_count rw 0x00 this bit field specifies the number of times this delay counter will count down and then trigger its designated targets. this is particularly useful for scheduling multiple samples of an lradc channel set. if this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target lradc and/or delay channels. note setting the loop count to 0x01 will yield two conversions. 10:0 delay rw 0x000 this 11-bit field counts down to zero. at zero, it triggers either a set of lradc channel conversions or another delay channel, or both. it can trigger up to all eight lradcs and all four delay channels in a single even. this counter operates on a 2-khz clock derived from the crystal clock. table 953. hw_lradc_dela y0 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 733 description: table 954. hw_lradc_delay1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 trigger_lradcs rsrvd2 kick trigger_delays loop_count delay table 955. hw_lradc_dela y1 bit field descriptions bits label rw reset definition 31:24 trigger_lradcs rw 0x00 setting a bit in this bit field to one causes the delay controller to trigger the corresponding lradc channel. this trigger occurs when the delay count of this delay channel reaches zero. note that all eight lradc channels can be triggered at the same time. any channel with its corresponding bit set in this field is triggered. the hw accomplishes this by setting the corresponding bit(s) in hw_lradc_ctrl0_schedule. 23:21 rsrvd2 ro 0x0 reserved 20 kick rw 0x0 setting this bit to one initiates a delay cycle. at the end of that cycle, any trigger_lradcs or trigger_delays will start. 19:16 trigger_delays rw 0x0 setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. this trigger occurs when the delay count of this delay channel reaches zero. note that all four delay channels can be triggered at the same time, including the one that issues the trigger. this can have the effect of automatically retriggering a delay channel. 15:11 loop_count rw 0x00 this bit field specifies the number of times this delay counter will count down and then trigger its designated targets. this is particularly useful for scheduling multiple samples of an lradc channel set. if this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target lradc and/or delay channels. 10:0 delay rw 0x000 this 11-bit field counts down to zero. at zero, it triggers either a set of lradc channel conversions or another delay channel, or both. it can trigger up to all eight lradcs and all four delay channels in a single even. this counter operates on a 2-khz clock derived from the crystal clock. free datasheet http:/// STMP36XX official product documentation 5/3/06 734 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 the lradc scheduling delay 1 register provides control by which lradc chan- nels and delay channels (including itself) may be triggered. the triggering of the selected delay and lradc channel(s) is delayed by the delay field value which counts down on a 2-khz clock. it is possible to use delay channels chained together to configure dependent timing of channel c onversions as in the example provided in introduction to this block. a delay channel may also be configured to trigger itself. in this case, it could be used to simultan eously trigger an lradc channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the delay field. the delay channel is started by setting the kick bit to one. example: hw_lradc_delayn_wr(1, (bf_lradc_delayn_trigger_lradcs(0x05) | // lradc channel 0 and 2 bf_lradc_delayn_kick(1) | // start the delay channel bf_lradc_delayn_trigger_delays(0x2) | // restart delay channel 1 each time bf_lradc_delayn_delay(0x0e45) ) ); // delay 3653 periods of 2 khz clock // ... do other things until the triggered lradc channels report an interrupt. 29.5.16. lradc scheduling delay 2 register description the lradc scheduling delay 2 register controls one delay operation. at the end of this delay, this channel can trigger one or more lradc channels or one or more scheduling delay channels . hw_lradc_delay2 0x800500f0 hw_lradc_delay2_set 0x800500f4 hw_lradc_delay2_clr 0x800500f8 hw_lradc_delay2_tog 0x800500fc table 956. hw_lradc_delay2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 trigger_lradcs rsrvd2 kick trigger_delays loop_count delay table 957. hw_lradc_dela y2 bit field descriptions bits label rw reset definition 31:24 trigger_lradcs rw 0x00 setting a bit in this bit field to one causes the delay controller to trigger the corresponding lradc channel. this trigger occurs when the delay count of this delay channel reaches zero. note that all eight lradc channels can be triggered at the same time. any channel with its corresponding bit set in this field is triggered. the hw accomplishes this by setting the corresponding bit(s) in hw_lradc_ctrl0_schedule. 23:21 rsrvd2 ro 0x0 reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 735 description: the lradc scheduling delay 2 register provides control by which lradc chan- nels and delay channels (including itself) may be triggered. the triggering of the selected delay and lradc channel(s) is delayed by the delay field value which counts down on a 2-khz clock. it is possible to use delay channels chained together to configure dependent timing of channel c onversions as in the example provided in introduction to this block. a delay channel may also be configured to trigger itself. in this case, it could be used to simultan eously trigger an lradc channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the delay field. the delay channel is started by setting the kick bit to one. example: hw_lradc_delayn_wr(2, (bf_lradc_delayn_trigger_lradcs(0x05) | // lradc channel 0 and 2 bf_lradc_delayn_kick(1) | // start the delay channel bf_lradc_delayn_trigger_delays(0x4) | // restart delay channel 2 each time bf_lradc_delayn_delay(0x0e45) ) ); // delay 3653 periods of 2 khz clock // ... do other things until the triggered lradc channels report an interrupt. 29.5.17. lradc scheduling delay 3 register description the lradc scheduling delay 3 register controls one delay operation. at the end of this delay, this channel can trigger one or more lradc channels or one or more scheduling delay channels . hw_lradc_delay3 0x80050100 hw_lradc_delay3_set 0x80050104 hw_lradc_delay3_clr 0x80050108 hw_lradc_delay3_tog 0x8005010c 20 kick rw 0x0 setting this bit to one initiates a delay cycle. at the end of that cycle, any trigger_lradcs or trigger_delays will start. 19:16 trigger_delays rw 0x0 setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. this trigger occurs when the delay count of this delay channel reaches zero. note that all four delay channels can be triggered at the same time, including the one that issues the trigger. this can have the effect of automatically retriggering a delay channel. 15:11 loop_count rw 0x00 this bit field specifies the number of times this delay counter will count down and then trigger its designated targets. this is particularly useful for scheduling multiple samples of an lradc channel set. if this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target lradc and/or delay channels. 10:0 delay rw 0x000 this 11-bit field counts down to zero. at zero, it triggers either a set of lradc channel conversions or another delay channel, or both. it can trigger up to all eight lradcs and all four delay channels in a single even. this counter operates on a 2-khz clock derived from the crystal clock. table 957. hw_lradc_dela y2 bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 736 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 table 958. hw_lradc_delay3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 trigger_lradcs rsrvd2 kick trigger_delays loop_count delay table 959. hw_lradc_dela y3 bit field descriptions bits label rw reset definition 31:24 trigger_lradcs rw 0x00 setting a bit in this bit field to one causes the delay controller to trigger the corresponding lradc channel. this trigger occurs when the delay count of this delay channel reaches zero. note that all eight lradc channels can be triggered at the same time. any channel with its corresponding bit set in this field is triggered. the hw accomplishes this by setting the corresponding bit(s) in hw_lradc_ctrl0_schedule. 23:21 rsrvd2 ro 0x0 reserved 20 kick rw 0x0 setting this bit to one initiates a delay cycle. at the end of that cycle, any trigger_lradcs or trigger_delays will start. 19:16 trigger_delays rw 0x0 setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. this trigger occurs when the delay count of this delay channel reaches zero. note that all four delay channels can be triggered at the same time, including the one that issues the trigger. this can have the effect of automatically retriggering a delay channel. 15:11 loop_count rw 0x00 this bit field specifies the number of times this delay counter will count down and then trigger its designated targets. this is particularly useful for scheduling multiple samples of an lradc channel set. if this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target lradc and/or delay channels. errata: ta1 and ta2 silicon revisions do not correctly support the loop_count field, do not use. 10:0 delay rw 0x000 this 11-bit field counts down to zero. at zero, it triggers either a set of lradc channel conversions or another delay channel, or both. it can trigger up to all eight lradcs and all four delay channels in a single even. this counter operates on a 2-khz clock derived from crystal clock. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 737 description: the lradc scheduling delay 3 register provides control by which lradc chan- nels and delay channels (including itself) may be triggered. the triggering of the selected delay and lradc channel(s) is delayed by the delay field value which counts down on a 2-khz clock. it is possible to use delay channels chained together to configure dependent timing of channel c onversions as in the example provided in introduction to this block. a delay channel may also be configured to trigger itself. in this case, it could be used to simultan eously trigger an lradc channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the delay field. the delay channel is started by setting the kick bit to one. example: hw_lradc_delayn_wr(3, (bf_lradc_delayn_trigger_lradcs(0x05) | // lradc channel 0 and 2 bf_lradc_delayn_kick(1) | // start the delay channel bf_lradc_delayn_trigger_delays(0x8) | // restart delay channel 3 each time bf_lradc_delayn_delay(0x0e45) ) ); // delay 3653 periods of 2 khz clock // ... do other things until the triggered lradc channels report an interrupt. 29.5.18. lradc debug register 0 description the lradc debug register 0 provides read -only access to various internal states and other debug information. hw_lradc_debug0 0x80050110 hw_lradc_debug0_set 0x80050114 hw_lradc_debug0_clr 0x80050118 hw_lradc_debug0_tog 0x8005011c description: the lradc debug register 0 contains read-only diagnostic information regarding the internal state machine. this only used in debugging. example: if (hw_lradc_debug0.state == 0x33) {} // some action based on this state. table 960. hw_lradc_debug0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 readonly rsrvd1 state table 961. hw_lradc_debug0 bit field descriptions bits label rw reset definition 31:16 readonly ro 0x4321 lradc internal state machine current state. 15:12 rsrvd1 ro 0x0 reserved 11:0 state ro 0x0 lradc internal state machine current state. free datasheet http:/// STMP36XX official product documentation 5/3/06 738 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 29.5.19. lradc debug register 1 description the lradc debug register 1 provides read -only access to various internal states and other debug information. hw_lradc_debug1 0x80050120 hw_lradc_debug1_set 0x80050124 hw_lradc_debug1_clr 0x80050128 hw_lradc_debug1_tog 0x8005012c table 962. hw_lradc_debug1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd3 request rsrvd2 testmode_count rsrvd1 testmode6 testmode5 testmode table 963. hw_lradc_debug1 bit field descriptions bits label rw reset definition 31:24 rsrvd3 ro 0x0 reserved 23:16 request ro 0x0 lradc internal request register. 15:13 rsrvd2 ro 0x0 reserved 12:8 testmode_count rw 0x0 when in test mode, the value in this register will be loaded in to a counter which is decremented upon each channel 7 conversion. when that counter decrements to zero, the hw_lradc_ch7_testmode_toggle field will be toggled, indicating that the conversion value of interest is available in the hw_lradc_ch7_value bit field. 7:3 rsrvd1 ro 0x0 reserved 2 testmode6 rw 0x0 force dummy conversion cycles on channel 6 during test mode. normal = 0x0 normal operation. test = 0x1 put it in test mode, i.e., continuously sample channel 6. 1 testmode5 rw 0x0 force dummy conversion cycles on channel 5 during test mode. normal = 0x0 normal operation. test = 0x1 put it in test mode, i.e., continuously sample channel 5. 0 testmode rw 0x0 place the lradc in a special test mode in which the analog section is free-running at its clock rate. lradc_ch7 result is continuously updated every n conversions from the analog source selected in ctrl2, where n is determined by testmode_count. normal = 0x0 normal operation. test = 0x1 put it in test mode, i.e., continuously sample channel 7. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 29: low-resolution adc and touch-screen interface 739 description: the lradc debug register 1 provides read-only diagnostic information and con- trol over the test modes of lradc channels 5, 6, and 7. this is only used in debug- ging the lradc. example: bw_lradc_debug1_testmode(bv_lradc_debug1_testmode__test); 29.5.20. lradc battery conversion register description the lradc battery conversion register provides access to the battery voltage scale multiplier. hw_lradc_conversion 0x80050130 hw_lradc_conversion_set 0x80050134 hw_lradc_conversion_clr 0x80050138 hw_lradc_conversion_tog 0x8005013c table 964. hw_lradc_conversion 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd3 automatic rsrvd2 scale_factor rsrvd1 scaled_batt_voltage table 965. hw_lradc_conver sion bit field descriptions bits label rw reset definition 31:21 rsrvd3 ro 0x0 reserved 20 automatic rw 0x0 control the automatic update mode of the batt_val bit field in the hw_power_monitor register. disable = 0x0 no automatic update of the scaled value. enable = 0x1 automatically compute the scaled battery voltage each time an lradc channel 7 (batt) conversion takes place. 19:18 rsrvd2 ro 0x0 reserved 17:16 scale_factor rw 0x0 scale factors of 29/512, 29/256 or 29/128 are selected here. nimh = 0x0 single nimh battery operation, 29/512. dual_nimh = 0x1 two nimh battery operation, 29/256. li_ion = 0x2 lithium ion battery operation, 29/128. alt_li_ion = 0x3 lithium ion battery operation, 29/128. 15:10 rsrvd1 ro 0x0 reserved 9:0 scaled_batt_voltage rw 0x80 lradc battery voltage divided by approximately 17.708. the actual scale factor is (battery voltage) times 29 divided by 512, 256, or 128. free datasheet http:/// STMP36XX official product documentation 5/3/06 740 chapter 29: low-resolution adc and touch-screen interface 5-36xx-d1-1.02-050306 description: the lradc battery conversion register controls the volta ge scaling multiplier that is used to multiply the lradc battery voltage by 29 divided by 512 for nimh, battery voltage times 29 divided by 256 for dual nimh and battery voltage times 29 divided by 128 for lithium ion batteries. example: hw_lradc_conversion.automatic = 1; lradc xml revision: 1.49 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 30: memory copy device 741 30. memory copy device this chapter describes the memory copy device included on the STMP36XX. along with programming examples. programmable registers are described in section 30.4 . 30.1. overview the memory copy or memcpy apb device provides a path from a source dma channel to a destination dma channel, allowing blocks of data located on any slave on the ahb to be copied to any slave on the ahb. in particular, it can be used to copy data from sdram to on-chip sram or sram to sdram without cpu involve- ment. it is also used to copy blocks of data and instructions from on-chip rom to on-chip ram. it is also used by the overlay/paging software to copy pages from sdram to on-chip ram when page faults are detected. figure 132 shows a block diagram of the memory copy device included on the STMP36XX. the memcpy device is removed from soft reset and has its clocks enabled. then, both a source and destination dma are initia lized. either the source or destination dma command structure contains one pio register value to write to the memcpy device. as a result, the memcpy device copi es all of the bytes from the source to the destination. scatter and/or gather op erations can be implemented by chaining multiple source dma comm ands or multiple destination dma commands together. clkgen (hclk) memcpy memcpy programmable regs arm core ahb slave ahb shared dma ahb master apbh master ahb-to-apbh bridge sram fifo src dmareq sink dmareq apbh figure 132. memory copy device block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 742 chapter 30: memory copy device 5-36xx-d1-1.02-050306 a memory-fill operation can be created by chaining a source dma descriptor back on itself, so that the memcpy device copi es the same source values over and over to the destination. if the user wants to program apbh dma channel 2 (the memcpy source channel) to utilize a different count value than apbh dma channel 3 (the memcpy destina- tion channel), the count value for channel 2 needs to be a multiple of 4 bytes. if the user programs the channel 2 and channel 3 count values to be the same value, then any byte count value can be used. not following these guidelines can lead to expected behavior. 30.2. programming examples 30.2.1. block copy //////////////////////////////////////////////////////// // the two descriptors need to be placed in non-cached memory //////////////////////////////////////////////////////// static reg32_t source_descriptor[4]; static reg32_t destination_descriptor[3]; //////////////////////////////////////////////////////// // block copy routine using memcpy device //////////////////////////////////////////////////////// unsigned block_copy(const void* source, void* destination, unsigned bytes) { const unsigned timeout = 100; unsigned retries; // setup source descriptor. source_descriptor[0] = 0; source_descriptor[1] = (bf_apbh_chn_cmd_xfer_count(bytes) | bf_apbh_chn_cmd_cmdwords(1) | bv_fld(apbh_chn_cmd, command, dma_read)); source_descriptor[2] = (reg32_t) source; source_descriptor[3] = bf_memcpy_ctrl_xfer_size(bytes); // setup destination descriptor. destination_descriptor[0] = 0; destination_descriptor[1] = (bf_apbh_chn_cmd_xfer_count(bytes) | bf_apbh_chn_cmd_semaphore(1) | bv_fld(apbh_chn_cmd, command, dma_write)); destination_descriptor[2] = (reg32_t) destination; // reset both source and destination channels. hw_apbh_ctrl0_set(bf_apbh_ctrl0_reset_channel((1 << 3) | (1 << 2))); // setup source and destination descriptor pointers. bf_wrn(apbh_chn_nxtcmdar, 2, cmd_addr, (reg32_t) source_descriptor); bf_wrn(apbh_chn_nxtcmdar, 3, cmd_addr, (reg32_t) destination_descriptor); // start both source and destination channels by incrementing semaphore. bf_wrn(apbh_chn_sema, 2, increment_sema, 1); bf_wrn(apbh_chn_sema, 3, increment_sema, 1); // poll for decrement of destination channel's semaphore. for (retries = 0; retries < timeout; retries++) if (!bf_rdn(apbh_chn_sema, 3, phore)) break; // return false if timed out waiting for semaphore. if (retries == timeout) return 0; // otherwise, return true; the block has been copied. return 1; } free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 30: memory copy device 743 30.2.2. rom dot data copying and bss fill the following sample code shows how the memcpy device can be used to copy the dot data section from rom to ram and how it can then be used to zero the bss section. //////////////////////////////////////////////////////// // the descriptors and dma data buffer need to be placed // in non-cached memory //////////////////////////////////////////////////////// unsigned long fill_buffer[32] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; const reg32_t source_descriptor_bss_fill[3] = { (reg32_t) source_descriptor_bss_fill, // repeat this one over and over (reg32_t) (bf_apbh_chn_cmd_xfer_count(32) | bf_apbh_chn_cmd_chain(1) |// repeat bv_fld(apbh_chn_cmd, command, dma_read)), (reg32_t) fill_buffer; }; const reg32_t source_descriptor_dot_data[3] = { (reg32_t) source_descriptor_bss_fill, (reg32_t) (bf_apbh_chn_cmd_xfer_count(bytes) | bf_apbh_chn_cmd_chain(1) | bv_fld(apbh_chn_cmd, command, dma_read)), (reg32_t) &dot_data_start_address }; const reg32_t destination_descriptor_bss_fill[4] = { (reg32_t) 0x0, (reg32_t) (bf_apbh_chn_cmd_xfer_count(bytes) | bf_apbh_chn_cmd_semaphore(1) | bf_apbh_chn_cmd_cmdwords(1) | bf_apbh_chn_cmd_chain(0) | bv_fld(apbh_chn_cmd, command, dma_write)), (reg32_t) &bss_target_address_in_ram, (reg32_t) bf_memcpy_ctrl_xfer_size(bytes) }; const reg32_t destination_descriptor_dot_data[4] = { (reg32_t) destination_descriptor_bss_fill, (reg32_t) (bf_apbh_chn_cmd_xfer_count(bytes) | bf_apbh_chn_cmd_cmdwords(1) | bf_apbh_chn_cmd_chain(1) | bv_fld(apbh_chn_cmd, command, dma_write)), (reg32_t) &dot_data_target_address_in_ram, (reg32_t) bf_memcpy_ctrl_xfer_size(bytes) }; //////////////////////////////////////////////////////// // rom routine for copying dot data section from rom to ram // and for zero filling the bss section. //////////////////////////////////////////////////////// void rom_dot_data_copy() { unsigned retries; // remove soft reset from the memcpy device and start the clock hw_memcpy_ctrl_clr(bm_memcpy_ctrl_sftrst | bm_memcpy_ctrl_clkgate); // reset both source and destination channels. hw_apbh_ctrl0_set(bf_apbh_ctrl0_reset_channel((1 << 3) | (1 << 2))); // setup source and destination descriptor pointers. bf_wrn(apbh_chn_nxtcmdar, 2, cmd_addr, (reg32_t) source_descriptor_dot_data); bf_wrn(apbh_chn_nxtcmdar, 3, cmd_addr, (reg32_t) destination_descriptor_dot_data); free datasheet http:/// STMP36XX official product documentation 5/3/06 744 chapter 30: memory copy device 5-36xx-d1-1.02-050306 // start both source and destination channels by incrementing semaphore. bf_wrn(apbh_chn_sema, 2, increment_sema, 1); bf_wrn(apbh_chn_sema, 3, increment_sema, 1); // return and do other things while the various memory blocks are copied } int rom_wait4_dot_data_copy() // poll for decrement of destination channel's semaphore. for (retries = 0; retries < timeout; retries++) if (!bf_rdn(apbh_chn_sema, 3, phore)) break; // return false if timed out waiting for semaphore. if (retries == timeout) return 0; // otherwise, return true; the block has been copied. return 1; } 30.3. behavior during reset a soft reset (sftrst) can take multiple clock periods to comp lete, so do not set clkgate when setting sftrst. the reset process gates the clocks automatically. see section 33.4.10 , ?correct way to soft reset a block? on page 805 for additional information on using the sftrst and clkgate bit fields. 30.4. programmable registers the following registers are available for programmer access and control of the memory copy device. 30.4.1. memory copy device control and status register description the memcpy control and status register specifies the reset state, and the inter- rupt and control information for the memory copy device. hw_memcpy_ctrl 0x80014000 hw_memcpy_ctrl_set 0x80014004 hw_memcpy_ctrl_clr 0x80014008 hw_memcpy_ctrl_tog 0x8001400c table 966. hw_memcpy_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 sftrst clkgate present rsrvd1 burst xfer_size free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 30: memory copy device 745 description: empty description. example: empty example. 30.4.2. memcpy device dma read and write data register description the memcpy device dma read and write data register is the target, for both source and destination dma transfers. this register is backed by an eight-deep fifo. hw_memcpy_data 0x80014010 hw_memcpy_data_set 0x80014014 hw_memcpy_data_clr 0x80014018 hw_memcpy_data_tog 0x8001401c table 967. hw_memcpy_ctrl bit field descriptions bits label rw reset definition 31 sftrst rw 0x1 set to zero for normal operation. when this bit is set to one (default), then the entire block is held in its reset state. run = 0x0 allow memcpy to operate normally. reset = 0x1 hold memcpy in reset. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. run = 0x0 allow memcpy to operate normally. no_clks = 0x1 do not clock memcpy gates in order to minimize power consumption. 29 present ro 0x1 this read-only bit indicates that the memcpy function is present when it reads back a one. the memcpy function is not available on a device that returns a zero for this bit field. unavailable = 0x0 memcpy is not present in this product. available = 0x1 memcpy is present in this product. 28:17 rsrvd1 ro 0x0 these bits always read back zero. 16 burst rw 0x0 when set, the memcpy performs 4-beat burst instead of the 1-beat burst. 15:0 xfer_size rw 0x0000 a write to this register sets the number of bytes to transfer. a read from this register reflects the number of bytes remaining for the dma read channel to read from the memcpy device. table 968. hw_memcpy_data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 data table 969. hw_memcpy_data bit field descriptions bits label rw reset definition 31:0 data rw 0x00000000 the source dma channel writes to this address. the destination dma channel reads from this address. free datasheet http:/// STMP36XX official product documentation 5/3/06 746 chapter 30: memory copy device 5-36xx-d1-1.02-050306 description: empty description. 30.4.3. memcpy device debug register description the memcpy device debug register provid es a diagnostic view into the internal state machine and states of the memcpy device. hw_memcpy_debug 0x80014020 hw_memcpy_debug_set 0x80014024 hw_memcpy_debug_clr 0x80014028 hw_memcpy_debug_tog 0x8001402c description: empty description. memcpy xml revision: 1.21 table 970. hw_memcpy_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsvd2 dst_end_cmd dst_kick dst_dma_req rsvd1 src_kick src_dma_req rsvd0 write_state read_state table 971. hw_memcpy_debug bit field descriptions bits label rw reset definition 31 rsvd2 ro 0x0 reserved. 30 dst_end_cmd ro 0x0 this bit reflects the state of the destination channel end command signal. 29 dst_kick ro 0x0 this bit reflects the state of the destination channel kick signal. 28 dst_dma_req ro 0x0 this bit reflects the state of the destination channel dma request signal. 27:26 rsvd1 ro 0x0 reserved. 25 src_kick ro 0x0 this bit reflects the state of the source channel kick signal. 24 src_dma_req ro 0x0 this bit reflects the state of the source channel dma request signal. 23:4 rsvd0 ro 0x0 reserved. 3:2 write_state ro 0x0 these bits reflect the state of the memcpy state machine. 1:0 read_state ro 0x0 these bits reflect the state of the memcpy state machine. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 747 31. power supply this chapter describes the power supply subsystem provided on the STMP36XX. it includes sections on the dc-dc converters, linear regulators, pswitch pin func- tions, battery monitor and charger, and silicon speed se nsor. programmable regis- ters are described in section 31.8 . 31.1. overview the STMP36XX integrates a comprehensive power supply subsystem, including the following features. ? two integrated dc-dc converters support 1-cell, 2-cell, and li-ion batteries ? two linear regulators supply power directly from 5v. ? linear battery charger for nimh and li-ion cells. ? battery voltage and brownout monitor. ? reset controller. ? system monitors for temperature and speed. ? brownout detect for v dd, i/o and 5v supplies ? generates usb-otg 5v from li-ion battery (using pwm). ? support for on-the-fly transitioni ng between 5v and battery power. ? integrated fet switch to gate power to peripheral devices. the STMP36XX power supply is designed to offer maximum flexibility and perfor- mance, while minimizing external component requirements. figure 133 shows a functional block diagram of the power supply components including switching con- verters (dc-dc#1 and #2), two linear regulators, battery charge support, as well as battery monitoring, supply brownout detect ion, and silicon proc ess/temperature sen- sors. this figure can be used to understand which register and status bits relate to which subsystems, but it is not intended to be a complete architecture description. free datasheet http:/// STMP36XX official product documentation 5/3/06 748 chapter 31: power supply 5-36xx-d1-1.02-050306 31.2. dc-dc converters the dc-dc converters efficiently scale battery voltage to the required supply volt- ages. the dc-dc converters include several advanced features: ? flexible battery support ? single inductor modes for 1-cell and low-power li-ion ? dual-inductor modes fo r 2-cell and high-power li-ion (hdd player) ? programmable output voltages ? programmable brownout detection thresholds ? pulse frequency modulation (pfm) mode for low-current load operation 31.2.1. dc-dc operating modes the dc-dc converter?s operation is set up using a combination of hardware and software configuration. the basic operati on, including battery type and inductor con- figuration, is set by hardware configuration during product design. operating param- eters, such as output voltage, are programmable after power-up. power_sts_v0dio power_sts_vd0dbot dc-dc #1 and #2 minpower dcimultout dc1limits dc2limits loopctrl vbg disable_ilimit x vdd5v power_sts_vod5v_gt_vddio power_sts_avalid power_sts_bvalid power_sts_sessend x vddio vbg x battery battchrg x vddd disable_ilimit power_sts_batt_bo battmonitor power_sts_dc2_ok power_sts_dc1_ok power_sts_mode<1:0> x dcdc_mode vddctrl speed temp speedtemp x battery vddd status bits are in italic register names are underlined vddio vdio ilimit_ed_zero vddio vddio_p power_miwpwr_peripheralswoff notes: figure 133. power supply block diagram free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 749 the dc-dc mode pin determines which battery and inductor configuration is used. table 972 lists the various dc-dc battery modes. the STMP36XX dc-dc converter has several advanced modes. it offers buck/boost modes that maintain the vio voltage even as the battery voltage drops below it. this allows hard drive operation at 3.3 v while a li-ion battery discharges to 3.0 v, pro- viding 10% better battery life than buck-only designs that must shut down when the battery reaches 3.3 v. the STMP36XX also offers modes for 1-cell and li-ion batter- ies that can supply both the vdd and vio rails with a single inductor. the single- inductor operation allows the lowest cost an d area for products that do not require high peak power. 31.2.2. dc-dc operation the STMP36XX dc-dc converter enables a low-power system and features pro- grammable output voltages and control modes. most products adjust vdd dynami- cally to provide the minimum voltage requ ired for proper system operation. vio is typically set once during system initialization and not changed during operation, because most lcd displays are not compatible with dynamic voltage adjustment. 31.2.2.1. brownout/error detection the power subsystem has several mechanisms active by default that safely return the device to the off state if any one of the following errors or brownouts occur: ? the crystal oscillator frequency is detected below a certain threshold?this threshold is process- and voltage-sensitive, but will always be between 100 khz and 2 mhz. this feature can be disabled in the dcdc_ctrl field in the hw_rtc_persistent0 register. ? the battery voltage falls below the battery brownout level (field brwnout_lvl in hw_power_battmonitor)?this feature is disabled by clearing pwdn_battbrnout in the same register ? 5 v is detected, then removed?this feature is disabled by clearing hw_power_5vctrl_pwdn_5vbrnout. all three mechanisms are active by defaul t to ensure that the device always has a valid transition to a known state in case the power source is unexpectedly removed before software has complete d system configuration. soft ware can disable the func- table 972. dc-dc battery modes dc-dc mode pin mode batt vdd vio inductor max power comments open 3 1-cell 0.9v to 1.6v boost boost 1 200mw @ 1.0v low cost and area 270k 2 2-cell 1.8 to 3.2v buck boost 2 400mw @ 1.8v vio must be higher than max battery voltage 120k 1 li-ion 2.9v to 4.2v buck buck/boost 1 600mw @ 3.1v low cost and area 0-ohm 0 li-ion 2.9v to 4.2v buck buck/boost (169bga) buck (100qfp) 2 1600mw @ 3.1v high power capability, battery > 3.1 to startup free datasheet http:/// STMP36XX official product documentation 5/3/06 750 chapter 31: power supply 5-36xx-d1-1.02-050306 tionality of pwdn_5vbrnout and pwdn _battbrnout after system configura- tion is complete, as shown in figure 134 . system configuration generally includes setting up brownout detection thresholds on the supply voltages, battery, etc. to obtain the desired system op eration as the battery or power source is depleted or removed. typically, each voltage output is set to some voltage margin above the minimum operating level via vddd_trg and vddio_trg in hw_power_vddctrl. the brownout detection threshold is also set (vddd_bo and vddio_bo) above the minimum operation level, but below the rail?s operating leve l. if the voltage drops to the brownout detector?s level, then it opti onally triggers a cpu fast interrupt (fiq). the cpu can then alleviate the problem and/or shut down the system elegantly. see chapter 2 , ?characteristics and specifications? on page 39 for suggested volt- age settings for the supply and brownout targets for different operating frequencies. to eliminate false detection, the brownout circuit filters transient noise above 1 mhz. any system with an STMP36XX should include at least 10 f of decoupling capaci- tance on all power rails. the capacitors should be arranged to filter supply noise in the 1-mhz and higher frequencies. see figure 134 . 31.2.2.2. dc-dc extended battery life features the dc-dc converter has several other power-reducing programmable modes use- ful in maximizing battery life: ? li-ion buck/boost ?both li-ion battery configurations support buck/boost operation, which means that a vddio volt age can be supported that is higher than the input li-ion battery voltage. this is important to maximize battery life in all applications, but is cruc ial in hard drives that have large transient current requirements. in the li-ion configuration mo de 0, the dc-dc converter will only power up as a buck converter to prevent over-discharge of the battery, and boost operation is enabled after powerup by setting en_boost high and increasing poslimit_buck to 0x30 in hw_p ower_dc2limits. however, mode 0 buck/boost requires the 169-pin bga package option, so that the necessary connections can be made to the power tr ansistors. the single inductor li-ion configuration is automatically configur ed for buck/boost and can even powerup with a li-ion battery less than 3.0 v in either 100-pin or 169-pin options. ? transient loading optimizations ?several new incremental improvements have been made to the control architecture of the switching converters. at this time, it is recommended the following bits be set via software in hw_power_loopctrl to obtain maximum efficiency and minimum supply ripple: en_cmp_hyst, tran_n ohyst, en_dc2_rcscale, and en_rcscale . en_dc1_rcscale should be set only in alkaline battery configuration, mode 3, or in li-ion configurations when large decoupling inductors and capacitors (at least 22-uf capacitors and 15-uh inductors) are used. also, converter configurations that use one inductor to produce two outputs (modes 3 and 1) should set en_batadj and toggle_dif after programming funcv as described in the hw_power_dc1multout register definition. lastly, single alkaline/nimh configurations (mode 3) should also set en_pfetoff. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 751 ? pulse frequency modulation (pfm) ?pfm, also known as pulse-skipping mode, is used to reduce power consumed by the dc-dc converter when the voltage outputs are lightly-loaded at a cost of higher transient noise. each dc-dc converter can be separately placed in pfm mode via the en_dc2_pfm off unplug=1 brownout=1 rom bist (pswitch or rtc wakeup or power_5vctrl_vdd5v_gt_vddio=1) enable lradc to measure battery and put value into batt_val. set up battery brownout code. power_dc1multout_en_batadj=1 do you want to reset or continue on a future plugin? do you want to reset or continue on a future unplug? set up irq for vddio5v plug in. power_ctrl_polarity_ vdd5v_gt_vddio=1 power_ctrl_enirq_ vdd5v_gt_vddio=1 power_5vctrl_pwdn_ 5vbrnout=1 power_sts_vdd5v_gt_vddio=0 power_sts_vdd5v_gt_vddio=1 reset continue power_5vctrl_en_dcdc1=1 power_5vctrl_en_dcdc2=1 power_5vctrl_pwdn_ 5vbrnout=0 5v device plugin (interrupt-driven event) power_sts_ vdd5v_gt_vddio=1 (any instance) configure* 5v unplug detection. power_5vctrl_dcdc_xfer=1 power_5vctrl_pwdn_5vbrnout=0 power_battmonitor_pwdn_battbrnout=1 application continue reset power_ctrl_enirqbatt_bo=1 power_battmonitor_pwdn_battbrnout=0 base state defaults: power_5vctrl_pwdn_5vbrnout=1 power_battmonitor_pwdn_battbrnout=1 brownout=(power_sts_vdd5v_gt_vddio=0) & (power_battmonitor_pwdn_battbrnout=1) & (power_sts_batt_bo=1) unplug=(on falling edge of power_sts_vdd5v_gt_vddio) & (power_5vctrl_pwdn_5vbrnout=1) power_5vctrl_pwdn_ 5vbrnout=1 figure 134. brownout detection flowchart note:* see section 31.3.2.1 . free datasheet http:/// STMP36XX official product documentation 5/3/06 752 chapter 31: power supply 5-36xx-d1-1.02-050306 and en_dc1_pfm bits in hw_power_min pwr. when using pfm mode, it is also necessary to set hyst _sign in hw_power_loopctrl . when pfm mode is not enabled, hyst_sign should be set low . ? dc-dc switching frequency ?the standard dc-dc switching frequency is 1.5 mhz, which provides a good mix of efficiency and power output. the frequency can be reduced to 750 khz to reduce operating current in some light load situations via dc1_halfclk and dc2_halfclk in hw_power_minpwr. ? dc-dc converter power down ?if the system is to operate from linear regulators or an external power supply, then the internal dc-dc converters can be powered down via dc1_stopclk and dc2_stopclk in hw_power_minpwr. these bits are not intended to power down the whole system. use the hw_power_reset bits to power the system off. 31.3. linear regulators the STMP36XX integrates two linear regula tors that are typically used when the system is powered from a 5-v supply. both of these regulators have an output impedance of approximately one ohm. one regulator generates vio from the vdd5v pin, and the other generates vdd from the vio supply. therefore, all of the current is supplied by the vdd5v->vio regulator. in normal system operation, the battery voltage is relative ly stable. however, the vdd5v voltage can dynamically change as the product is plugged into a usb port or other 5-v supply. the STMP36XX is programmable to provide a variety of behaviors when the vdd5v supply becomes valid or inva lid, as well as to support operation via usb or external power. 31.3.1. usb compliance features upon connection of 5 v to the powered-down dev ice, the linear r egulators will auto- matically power up the device. to meet u sb inrush specificatio ns, linear regulators have a current limit which is <100ma, nomina lly 50ma, and is active by default. this current limit is disabled in the rom via the power_5vctrl_disable_ilimit after the supplies have reached their target values. system designers must under- stand that the current limit during 5-v power-up places restrictions on application current consumption until it is disabled. spec ifically, after connection to 5 v, if the system draws more curr ent than the current limit allows, the startup sequence does not complete and the rom code does not execute. further, usb otg implies that b-devices must draw very little current from 5 v. this requirement can be met by sett ing power_5vctrl_ilimit_eq_zero when the otg application is active. the comparat ors required for otg can be enabled by power_5vctrl_otg_pwrup_cmps . it is also possible to change the thresh- old of the vbus valid comparator via power_5vctrl_vbusvalid_trsh . if very low power operation is required, as in usb suspend, then the circuits required to elegantly switch to the dc-dc converter may have to be powered off. in those cases, the syst em will have to fully power dow n after vdd5v becomes invalid. it can auto restart with dc-dc conver ter if hw_rtc_per sist0_autorestart is set. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 753 31.3.2. 5v to battery power interaction the STMP36XX supports several different options related to the interaction of the switching converters with the linear regula tors. the two primary options are a reset on 5-v insertion/removal or a handoff to the dc-dc converters that is invisible to the end-user of the application. figure 135 includes these two options as the two sys- tem architecture decision boxes in the figure. 31.3.2.1. battery power to 5-v power by default, the dc-dc converters turn off when vdd5v becomes valid and the sys- tem does not reset. if the system is op erating from the dc-dc converter and using more than 50 ma, then if vdd5v becomes valid, the dc-d c will turn off and the lin- ear regulators may not be able to supply the required current. the vdd and vio rails will droop and the system will brownout and shut down. to avoid this issue, the linreg_offset, en_dcdc1 (in all modes) and en_dcdc2 (if using mode 0 or 2) bits should be set in anticipation of vdd5v becoming present. the en_dcdc1 and en_dcdc2 two bits will cause the dc-d c converters to remain on even after 5 v is connected and, thus, guarantee a stable supply voltage until the system is configured for removal of 5 v. the linreg_offset causes the dc-dc converters to regulate a higher target voltage than the linear regulators to prevent unwanted interaction between the two power supplies. linreg_offset affects the decode of the voltage targets as described in the vddctrl register. after the system is configured for removal of 5 v, en_ dcdc1 and en_dcdc2 can be set low and disable_ilimit se t high in hw_power_5vctrl to allow the linea r regulators to supply the system power. 31.3.2.2. 5-v power to battery power configuring the system for a 5-v-to-battery power handoff requires setup code to monitor the battery voltage as well as detect the removal of 5 v. monitoring the battery voltage is performed by the lradc. typically, this involves programming the lradc registers to peri odically monitor the battery voltage as described in chapter 29 , ?low-resolution adc and touch-screen interface? on page 705 . the measured battery voltage should be written into the hw_power_battmonitor register field batt_val using the automatic field in the hw_lradc_conversion register. also , configuring battery brownout should be performed so that the system behaves as desired when 5 v is no longer present and the battery is low. the recommended method to detect removal of 5v requires setting vbusvalid_5vdetect and programming the detection threshold vbusvalid_trsh to 0x1 in hw_power_5vctrl . next, in order to minimize lin- ear regulator and dc-dc converter interaction, it is necessary to set linreg_offset . finally, set dcdc_xfer and clear pwdn_5vbrnout in the hw_power_5vctrl register. this sequence is important because it is safe to disable the powerdown-on-unplug functiona lity of the device only after the system is completely ready for a tran sition to battery power. 31.3.2.3. 5-v power and battery power it is also possible to operate from both the 5-v and the dc-dc converters. this may be desirable under heavier load conditions than the 5 v can support. this function- ality is enabled by setting en_dcdc1 /2 (to enable the switching converters when 5v is present) and using either linregoffset or disable_ilimit in free datasheet http:/// STMP36XX official product documentation 5/3/06 754 chapter 31: power supply 5-36xx-d1-1.02-050306 hw_power_5vctrl to determine which path is the dominant power source. bat- tery charge can also be enabled in li-ion configurations to provide additional power efficiency when connected to 5 v, because the buck swit ching converters will effi- ciently convert the battery voltage to the desired vddd and vddio voltages. it is also possible to improve power efficiency in li-ion modes when connected to 5 v by enabling battery charge and also enabling the dc-dc converters by setting en_dcdc1/2. 31.3.3. power-up sequence the dc-dc converters control the power-up and reset of the STMP36XX. the power-up sequence begins when the battery is connected to the batt pin of the device (or a 5-v source is connected to the vdd5v pin). either the batt pin or vdd5v provides power through vod_xtal to the dc-dc startup circuitry, the crys- tal oscillator, and the real-time clock. this means that the crystal oscillator can be running, if desired, whenever a battery is connected to batt pin. this feature allows the real-time clock to operate when the chip is in the off state. the crystal oscilla- tor/rtc is the only power drain on the battery in this state and consumes only a very small amount of power. during this time, the vdd supply is held at ground, while the vio rail is either shorted to the battery (modes 3 or 2) or held at ground (li-ion modes). this is the off state that continues until the system power up begins. power-up can be started with one of several events: ? pswitch pin > 0.9 * vbat (1-cell) or > 0.5 * vbat (2-cell and li-ion) for 100 ms ? vdd5v power pin > 4.25 v for 100 ms ? real-time clock alarm wakeup when a power-up event has occurred, if vdd5v is valid, then the on-chip linear reg- ulators charge the vdd and vio rails to thei r default voltages. if vdd5v is not valid, then the dc-dc supply the vdd and vio ra ils. when the voltage rails have reached their target values, the digital logic reset is deasserted and the cpu begins execut- ing code. if the power supplies do not reach the target values by the time pswitch is deasserted, the system returns to the off state. the power-up time is dependent on the vdd/vio load and battery or vdd5v volt- age, but should be less than 100 ms. t he vdd/vio load should be minimal during power up to ensure proper startup of the dc-dc converters. there is an integrated 5k ? resistor that can be switch ed in between the vddxtal pin and the pswitch pin. if enabled ( hw_rtc_persist0_autorestart ), then the device immediately begins the power-up sequence after power down. 31.3.4. power-down sequence power-down is also controlled by the dc-dc converters. when the dc-dc convert- ers detect a power-down event, they return the player to the off state described above. the power-down sequence is started when one of these events occurs: ? hw_power_reset_pwd bit set while the register is unlocked. ? pswitch pin has a fast (<15-ns) falling edge ? watchdog timer expires while enabled the hw_power_reset_pwd_off bit disabl es all power-down paths except for the watchdog timer when it is set. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 755 the lower 16 bits of the hw_power_reset register can only be written if the value 0x3e77 is placed in the unlock field. an external capacitor on the pswitch can be used to prevent unwanted power down due to falling e dges. this can also be disabled in register hw_power_reset_pwd_off. 31.3.4.1. powered-down state while the chip is powered down, the vddd rail is pulled down to ground. the vddio rail is either shorted to ground (li-ion) or to the battery (1- or 2-cell). the crystal oscillator and the rt c can continue to operate by drawing power from the batt pin. see chapter 19 , ?real-time clock, alarm, watc hdog, and persistent bits? on page 497 for more information about operating an xtal and rtc in the pow- ered-down state. to support peripherals that need to be completely powered down in the off state, the 1- and 2-cell operating modes integrate a pe ripheral power switch. this switch sep- arates the vio rail, which will be at the battery voltage in the off state, from peripher- als that need to have their supply grou nded. this switch is opened during the power-down state and active pulldowns are turned on to hold the peripheral power supply at ground, which ensures that any devices connected to this rail receive a valid power-on reset. 31.3.5. reset sequence a reset event can be triggered by unlocking the hw_power_reset register and setting the hw_power_reset_rst_dig bit. this reset only affects the digital logic, although the digital logic also includes most of the register s that control the ana- log portions of the chip. the persistent bi ts within the real-time clock block and the power module control bits are not reset using this method. the dc-dc converters and/or linear regulators continue to maintain the power supply rails during the reset. free datasheet http:/// STMP36XX official product documentation 5/3/06 756 chapter 31: power supply 5-36xx-d1-1.02-050306 31.3.6. power up, power down, and reset flow chart no power no battery, no 5v. power on reset (clock and persistent bits reset) battery insert or 5v_detect=1 state zero (persistent bits retain state, xtal and clock active if enabled) power up (start xtal if it?s off, start 5v linear regs if 5v detect, else start dcdc converter) pswitch=1 or rtc alarm or auto_restart=1 or 5v_detect=1 power is stable start digital clocks (digital reset asserted. digital clocks all = 1 mhz) reset dcdc pio registers (all non-persistent flop resets asserted, note that the dcdc continues to operate even if the pio registers are reset. digital clocks all = 1 mhz) reset non-dcdc digital registers (non persistent and non-power flop resets asserted. digital clocks all = 1 mhz) release reset (digital clock domains at default frequency and gating, boot cpu ) wait 16 cycles for all resets to propogate to power down and clear persistent bits: set power_reset_por then power_reset_pwd (chip will not be able to auto-restart unless pswitch=1 or 5v_detect=1) normal power-up flow software-controlled resets to power down: set power_reset_pwd for cold reboot: set rtc_persistent0_auto_restart then power_reset_pwd to reset dcdc and digital: set power_reset_rst_all to reset digital but not dcdc (warm boot): set power_reset_rst_dig figure 135. power up, power down, and reset flow chart free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 757 31.4. pswitch pin functions the pswitch pin has several functions whose operation is determined by the STMP36XX-based product?s hardware and software design. 31.4.1. power on when the pswitch pin voltage is higher than approximately 0.9*vbat for 1-cell or vbat/2 for 2-cell or li-ion modes for >100 ms, the dc-dc converter begins its star- tup routine. this is the primary method of starting the system. all products based on the STMP36XX must have a mechan ism of bringing pswitch high. 31.4.2. power down if the pswitch pin voltage has a falling edge faster than 15 ns, then this sends a power-down request to th e dc-dc converter. the fa st-falling-edge power-down may be blocked by the hw_power_reset_pwd_off function. the fast-falling edge can also be prevented by placing an rc filter on the pswitch pin. most STMP36XX-based systems do not use th e pswitch fast-fallin g-edge power-down and include the rc filter to prevent it from occurring accidentally. 31.4.3. software functions/recovery mode when the pswitch pin voltage is pulled up to at least 0.9 * vbat (1-cell) or vbat/2 (2-cell and li-ion), the lower hw_digctl_status bit is set. software can poll this bit and perform a function as desired by the product designer. example functions include a play/pause/power-down button, delay for startup, etc. when the pswitch pin is connected to vddio through a current limiting resistor, the upper hw_digctl_status bit is also set. if this bit is set for more than five seconds during rom boot, the system executes the sigmatel usb firmware recovery function. if the product designer does not wish to use sigmatel usb firm- ware recovery, the product can be designed to not assert a voltage higher than the battery on the pswitch pin. refer to the sigmatel STMP36XX reference schematics for example configurations of the pswitch pin. 31.5. battery monitor the power control system includes a battery monitor. the battery monitor has two functions: battery brownout detection and battery voltage feedback to the dc-dc converter. if the battery voltage drops below the programmable brownout, then a fast interrupt (fiq) can be generated for the cpu. softwa re typically uses the lradc to monitor the battery voltage and shut down elegantly while there is a minimal operating mar- gin. but, if an unexpected event (such as a battery removal) occurs, then the system needs to be placed immediately in the off state to ensure that it can restart properly. the brownout is controlled in the hw_p ower_battmonitor register. the irq must also be enabled in the interrupt collector. to enable optimum performance over the battery range in modes 3 and 1, the dc- dc converter needs to be provided with the battery voltage, which is measured by the battery pin lradc. normally, lradc channel 7 is dedicated to periodically measuring the battery voltage with a period in the millis econd range for most appli- cations. the voltage is automatically placed into the batt_val field of the free datasheet http:/// STMP36XX official product documentation 5/3/06 758 chapter 31: power supply 5-36xx-d1-1.02-050306 hw_power_battmonitor register via the hw_lradc_conversion regis- ter. if necessary, software can turn off the automatic battery voltage update and set the batt_val field manually. 31.6. battery charger some products in the STMP36XX family in tegrate charging for li-ion and nimh batter- ies from a 5-v source connected to the vdd5v pin. the battery charger is essentially a linear regulator that has current and voltage limits. charge current is software programmable within the hw_battcharge register. the charger supports 0.1c for nimh batteries, which results in a 12-hour charge time. li-ion batteries can be charged at the lower of 1c, 785 ma, or the vdd5v current limit. usb charging is typically limited to 500 ma or less to meet compliance requirements. typical charge times for a li-ion battery are 1.5 to 3 hours with >70% of the charge delivered in the first hour. the battery charge voltage limit is determi ned by the battery type. if the dc-dc con- verter is configured for 1-cell mode, then the charge voltage is limited to 1.75 v. if the dc-dc converter is configured for li-ion mode, then the charge voltage is limited to 4.2 v. the li-ion charge is typically stopped after a certain time limit or when the charging current drops below 10% of the charge current setting. the hw_battcharge regis- ter includes controls for the maximum charge current and for the stop charge current. while the charger is delivering current greater than the stop charge limit, the hw_power_sts_chrgsts bit will be high. this bit should be polled (a low rate of 1 second or greater is ok) during charge. when the bit goes low, the charging is com- plete. it would be good practice to check that this bit is low for two consecutive checks, as the dc-dc switching might cause a spurious ?low? result. once this bit goes low, the charger can either be stopped immediately or stopped after a ?top-off? time limit. although the charger will avoid exceeding the charge voltage limit on the battery, it is not recommended to leave the charger active indefinitely. it should be turned off when the charge is complete. nimh charging does not use the ?stop char ge current? feature. nimh charging should be stopped after 12 hours (at a 0.1c rate) regardless of the output current. one can programatically monitor the battery voltage using the lradc. the charger has its own (very robust) voltage limiting that operates independently of the lradc. but monitoring the battery voltage during th e charge might be helpful for reporting the charge progress. the battery charger is capable of generating a large amount of heat within the STMP36XX, especially at currents above 400 ma. the dissipated power can be esti- mated as: (5v ? battery_volt) * current. at max current (785 ma) and a 3-v battery, the charger can dissipate 1.57 w, raising the di e temp as much as 80 c. to ensure that the system operates correctly, the die temperature sensor should be monitored every 100 ms. if the die temperature exceeds 115 c (the max value for the chip temp sen- sor), then the battery charge current must be reduced. the lradc can also be used to monitor the battery temperature or chip temperature. there is an integrated current source for the external temperature s ensor that can be configured and enabled via hw_lradc_ctrl2 register. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 759 31.7. silicon speed sensor the STMP36XX integr ates two silicon sp eed sensors to meas ure the performance characteristics of an individual die at its ambient temperature and process paramet- rics. each sensor consists of a ring os cillator and a frequency coun ter. the ring oscillator runs on the vdd pow er rail. therefore, its frequency trac ks the silicon per- formance as it changes in response to changes in operating voltage and tempera- ture. the crystal oscilla tor is directly used as the pr ecision time base for measuring the frequency of a ring oscillator. the ring oscillator is normally disabled. there is a 7-bit counter connected to th e ring oscillator that perf orms the fre quency measure- ment. see the hw_power_speed_temp register. thus, the counter holds the nu mber of cycles the ring oscillator was able to gener- ate during one crystal clock period. the natural frequency of the ring oscillator strongly tracks the silicon process parametrics, i.e., fa ster silicon processes yield ring oscillators that run fast er and ther eby yield larger count values. the natural fre- quency tracks junction temperatur e effects on silicon speed as well. the information given by th e speed sensor can be used with t he silicon temperature and process parameters, which can also be monitored by system software. sigma- tel can provide a power management applic ation note and firmware that takes full advantage of the on-chip monitoring func tions to enable minimum-voltage opera- tion. 31.8. dc-dc programmable registers 31.8.1. power control register description the power control register contains contro l bits specific to the digital section. hw_power_ctrl 0x80044000 hw_power_ctrl_set 0x80044004 hw_power_ctrl_clr 0x80044008 hw_power_ctrl_tog 0x8004400c table 973. hw_power_ctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 clkgate rsrvd1 batt_bo_irq enirqbatt_bo vddio_bo_irq enirqvddio_bo vddd_bo_irq enirqvddd_bo polarity_vdd5v_gt_vddio vdd5v_gt_vddio_irq enirqvdd5v_gt_vddio free datasheet http:/// STMP36XX official product documentation 5/3/06 760 chapter 31: power supply 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 31.8.2. dc-dc 5v control register description this register contains the configuration options of the power management sub- system that are available when external 5v is applied. hw_power_5vctrl 0x80044010 hw_power_5vctrl_set 0x80044014 hw_power_5vctrl_clr 0x80044018 hw_power_5vctrl_tog 0x8004401c table 974. hw_power_ctrl bit field descriptions bits label rw reset definition 31 rsrvd2 ro 0x0 empty description. 30 clkgate rw 0x1 this bit must be set to zero for normal operation. when set to one, it gates off the clocks to the block. this bit has no effect on the rtc analog section. 29:9 rsrvd1 ro 0x0 empty description. 8 batt_bo_irq rw 0x0 interrupt status for batt_bo. it is reset by software by writing a zero to the bit position or by writing a one to the sct clear address space. 7 enirqbatt_bo rw 0x0 enable interrupt for battery brownout. 6 vddio_bo_irq rw 0x0 interrupt status for vddio_bo. it is reset by software by writing a zero to the bit position or by writing a one to the sct clear address space. 5 enirqvddio_bo rw 0x0 enable interrupt for vddio brownout. 4 vddd_bo_irq rw 0x0 interrupt status for vddd_bo. it is reset by software by writing a zero to the bit position or by writing a one to the sct clear address space. 3 enirqvddd_bo rw 0x0 enable interrupt for vddd brownout. 2 polarity_vdd5v_gt_vddi o rw 0x1 set to 1 to check for 5v connected. set to 0 to check for 5v disconnected. 1 vdd5v_gt_vddio_irq rw 0x0 interrupt status for vdd5v_gt_vddio signal. interrupt polarity is set using polarity_vdd5v_gt_vddio. it is reset by software by writing a zero to the bit position or by writing a one to the sct clear address space. 0 enirqvdd5v_gt_vddio rw 0x0 enable interrupt for 5v detect. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 761 table 975. hw_power_5vctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 pwdn_5vbrnout pwdn_iobrnout disable_ilimit dcdc_xfer en_batt_pulldn vbusvalid_5vdetect rsrvd1 vbusvalid_trsh usb_suspend_i vbusvalid_to_b ilimit_eq_zero otg_pwrup_cmps en_dcdc2 pwd_vddd_linreg en_dcdc1 linreg_offset table 976. hw_power_5vctrl bit field descriptions bits label rw reset definition 31:22 rsrvd2 ro 0x0 empty description. 21 pwdn_5vbrnout rw 0x1 the purpose of this bit is to power down the device if 5v is removed before the system is completely initialized. clear this bit to disable automatic hardware powerdown after the system is configured for 5v removal. the removal of 5v is detected via the vdd5v_gt_vddio status signal and is latched internally. due to this latch, it is not recommended to reset this bit high after it has been cleared. this bit should not be set if dcdc_xfer is set. 20 pwdn_iobrnout rw 0x0 it is not recommended to use this bit, as the functionality to better supported via pwdn_5vbrnout. this bit enables automatic hardware power-down of the system when vddio crosses the vddio brownout threshold. setting this bit assumes that the 5v is present and enables the vddio brownout comparator automatically. (only set this bit after 5v has been detected; otherwise incorrect behavior will result.) this bit should not be set if dcdc_xfer is set. 19 disable_ilimit rw 0x0 disable the current limit in the linear regulators. the current limit defaults to enabled so that the system can meet the usb in rush current specification of 100ma + 50uc. note that this bit does not affect the battery charger current. 18 dcdc_xfer rw 0x0 enable automatic transition to switching dc-dc converters when vdd5v is removed. the lradc must be operational and the batt_val field must be written with the battery voltage using 8-mv step-size. when using one of the single-inductor/two-output configurations, it is also important to set the en_batadj field. also, this bit should not be set if the pwdn_iobrnout is set. free datasheet http:/// STMP36XX official product documentation 5/3/06 762 chapter 31: power supply 5-36xx-d1-1.02-050306 17 en_batt_pulldn rw 0x0 add very small current source (less than 5ua) to drain the battery pin. this maybe useful to detect the presence of an external battery when operating from an external 5-v supply. this information could be important if the dcdc_xfer functionality is enabled. 16 vbusvalid_5vdetect rw 0x0 enable the vbus valid comparator and use it as detection circuit for 5v in the switching converters. default is for the switching converter to use the vdd5v_gt_vddio status bit to determine the presence of 5v in the system. the vbus valid comparator provides a more accurate and adjustable threshold to determine the presence of 5v in the system. 15:10 rsrvd1 ro 0x0 empty description. 9:8 vbusvalid_trsh rw 0x0 set the threshold for the vbus valid comparator, 00=4.5v 01: 4.3v 10: 2.5v 11: 4.75v 7 usb_suspend_i rw 0x0 turn off switching dc-dc converter bias current. this bit will prevent the switching dc-dc converters from working correctly and should only be used as needed to minimize system power to meet the usb suspend current specification. 6 vbusvalid_to_b rw 0x0 this bit muxes the bvalid comparator to the vbus valid comparator and is used for test purposes only. 5 ilimit_eq_zero rw 0x0 the amount of current the device will consume from the 5v rail is minimized. the vddio linear regulator current limit is set to zero ma. also, the source of current for the crystal oscillator and rtc is switched to the battery. note that this functionality does not affect battery charge. 4 otg_pwrup_cmps rw 0x0 vbus valid comparators are enabled. 3 en_dcdc2 rw 0x0 enables the switching dc-dc converter #2 when 5v is present. use of the dc-dc converters and battery charge together may r educe system current requirements from the 5-v supply. 2 pwd_vddd_linreg rw 0x0 disable vddd linear regulator. the bit can be used with en_dcdc1 to force vddd to be generated from the battery supply using dc-dc#1 even when external 5v is connected. table 976. hw_power_5vctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 763 description: empty description. example: empty example. 31.8.3. dc-dc minimum power and miscellaneous control register description this register controls options to drop the power used by the switching dc-dc con- verters. these bits should only be modified with guidance from sigmatel. hw_power_minpwr 0x80044020 hw_power_minpwr_set 0x80044024 hw_power_minpwr_clr 0x80044028 hw_power_minpwr_tog 0x8004402c 1 en_dcdc1 rw 0x0 enables the switching dc-dc converter#1 when 5v is present. 0 linreg_offset rw 0x0 reverses the offset in the dc-dc converters so that the switching dc-dc converter regulates to a higher voltage than the linear regulators. the default is that the linear regulators regulate to one setting higher than the switching converters as described in vddctrl. setting this bit is useful in dc-dc handoff to prevent the linear regulators from fighting with the switching dc-dc converters, because the regulators can only pull up the supplies. note that this bit does not affect battery charge. table 977. hw_power_minpwr 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd2 test_dischrg_vbus test_chrg_vbus dc2_tst dc1_tst peripheralswoff toggle_dif disable_vddiostep disable_vddstep rsrvd1 sel_plldiv16clk pwd_vddiobo lessana_i dc1_halffets dc2_stopclk dc1_stopclk en_dc2_pfm en_dc1_pfm dc2_halfclk dc1_halfclk table 978. hw_power_minpwr bit field descriptions bits label rw reset definition 31:24 rsrvd2 ro 0x0 empty description. 23 test_dischrg_vbus rw 0x0 test function for otg disharge vbus. only for test purposes. table 976. hw_power_5vctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 764 chapter 31: power supply 5-36xx-d1-1.02-050306 22 test_chrg_vbus rw 0x0 test function for otg charge vbus. only for test purposes. 21 dc2_tst rw 0x0 reserved. 20 dc1_tst rw 0x0 reserved 19 peripheralswoff rw 0x0 turn off peripheral switch and force peripheral supply to ground. this switch is used in single or series aa/aaa configuration. the peri pheral switch is always active when 5v is present. 18 toggle_dif rw 0x0 set high to enable supply stepping to change only after the differential control loop has toggled as well. this should eliminate any chance of large transients when supply voltage changes are made in single- inductor dual-output dc-dc converter modes 01 or 11. in modes 10 or 00, this bit has no effect. 17 disable_vddiostep rw 0x0 dc-dc#1 or #2 steps the target vddd voltage one programming step at a time to minimize transient noise. this feaure can be disabled by setting this bit. in dc-dc#1 pfm, this bit will prevent vddio from being toggled as well as vddd. this pfm feature may be necessary if vddio is lightly loaded relative to vddd. 16 disable_vddstep rw 0x0 dc-dc#1 steps the target vddd voltage one programming step at a time to minimize transient noise. this feaure can be disabled by setting this bit. 15:10 rsrvd1 ro 0x0 empty description. 9 sel_plldiv16clk rw 0x0 this bit selects the sour ce of the clock used for the dc-dc converter and the lradc. the default is to use the 24-mhz clock. setting this bit selects the pll clock divided by 16 as a clock source for both the dc- dc converter and the lradc. 8 pwd_vddiobo rw 0x0 power-down the vddio brownout comparator. this should only be done when it is acceptable to lose the ability to detect a vddio brownout. default is vddio brownout comparator enabled. 7 lessana_i rw 0x0 reduce dc-dc analog bias current 20%. this bit is intended to reduce power in low-performance operating modes, such as usb suspend. 6 dc1_halffets rw 0x0 disable half the power transistors in dc-dc#1. this maybe be useful in low-power conditions when the increased resistance of the power fets is acceptable. 5 dc2_stopclk rw 0x0 stop the clock to internal logic of switching converter dc-dc#1. this bit will take effect only after the switching fets are off, due to battery configuration, pfm mode, or internal linear regulator operation. 4 dc1_stopclk rw 0x0 stop the clock to internal logic of switching converter dc-dc#1. this bit will take effect only after the switching fets are off, due to battery configuration, pfm mode, or internal linear regulator operation. table 978. hw_power_minpwr bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 765 description: empty description. example: empty example. 31.8.4. battery charge control register description this register cotrols the battery charge fe atures for both nimh slow charge and li- ion charge. hw_power_battchrg 0x80044030 hw_power_battchrg_set 0x80044034 hw_power_battchrg_clr 0x80044038 hw_power_battchrg_tog 0x8004403c 3 en_dc2_pfm rw 0x0 forces dc-dc#2 to operate in a pulse frequency modulation (pfm) mode. intended to allow minimum system power in very low-power configurations when increased ripple on the supplies is acceptable. also, hyst_sign in hw_power_loopctrl should be set high when using pfm mode. 2 en_dc1_pfm rw 0x0 forces dc-dc#1 to operate in a pulse frequency modulation mode. intended to allow minimum system power in very low-power configurations when increased ripple on the supplies is acceptable. also, hyst_sign in hw_power_loopctrl should be set high when using pfm mode. 1 dc2_halfclk rw 0x0 slow down dc-dc#2 clock from 1.5 mhz to 750 khz. this maybe be useful to improve efficiency at light loads or improve emi radiation, although peak-to-peak voltage on the supplies will increase. 0 dc1_halfclk rw 0x0 slow down dc-dc#1 clock from 1.5 mhz to 750 khz. this maybe be useful to improve efficiency at light loads or improve emi radiation, although peak-to-peak voltage on the supplies will increase. table 979. hw_power_battchrg 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd3 chrg_sts_off liion_4p1 use_extern_r pwd_battchrg rsrvd2 stop_ilimit rsrvd1 battchrg_i table 978. hw_power_minpwr bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 766 chapter 31: power supply 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 31.8.5. vddd and vddio supply targets and brownouts control register description this register controls the voltage targets and brownout targets for the vddd and vddio supplies generated from the switching dc-dc converters and integrated lin- ear regulators. both vddd and vddio brownout comparators default enabled. when the vddd and vddio are generated us ing the internal switching converters, the following guideline is recommended: alterations to vddd_trg and vddio_trg should not be done at the same time. after making a voltage target change, another one should not be programmed until the dc1_ok and dc2_ok flags return to the high state. hw_power_vddctrl 0x80044040 table 980. hw_power_battchrg bit field descriptions bits label rw reset definition 31:20 rsrvd3 ro 0x0 empty description. 19 chrg_sts_off rw 0x0 setting this bit disables the chrgsts status bit. disabling chrgsts should only be done when the switching converters are enabled during battery charge if noise from the switching converters causes chrgsts to toggle excessively. 18 liion_4p1 rw 0x0 default is 4.2-v final charging voltage 17 use_extern_r rw 0x0 set to 1 to use internal resistor to generate the battery charge current. default uses externally generated precision bias current. 16 pwd_battchrg rw 0x1 power-down the battery charge circuitry. this should only be set low when 5v is present 15:12 rsrvd2 ro 0x0 empty description. 11:8 stop_ilimit rw 0x0 current threshold at which li-ion battery charge stops. the current represented by each bits is as follows: (100 ma, 50 ma, 20 ma, 10 ma) = (bit 3, bit 2, bit 1, bit 0) it is recommended to set this value to 10% of the charge current. 7:6 rsrvd1 ro 0x0 empty description. 5:0 battchrg_i rw 0x00 magnitude of the battery charge current, the current represented by each bits is as follows: (400 ma, 200 ma, 100 ma, 50 ma, 20 ma, 10 ma) = (bit 5,bit 4, bit 3, bit 2, bit 1, bit 0) free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 767 table 981. hw_power_vddctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 vddio_bo rsrvd3 vddio_trg rsrvd2 vddd_bo rsrvd1 vddd_trg table 982. hw_power_vddct rl bit field descriptions bits label rw reset definition 31:29 rsrvd4 ro 0x0 empty description. 28:24 vddio_bo rw 0x0c voltage level of the brownout for the vddio supply. the step size is 64 mv with 0x00 = 2.049 v, 0x1f = 4.034 v, and the reset value is 2.817 v. the decode is identical when using linear regulators or the switching dc-dc converters and is not affected by linreg_offset. these values represent a mean value, but individual parts will have slight part-to-part variations with a sigma of around 12 mv from either switching converters or linear regulators. 23:21 rsrvd3 ro 0x0 empty description. 20:16 vddio_trg rw 0x10 voltage level of the vddio supply. the step size of this field is 64 mv. when using the switching converters, 0x00 = 2.049 v, 0x1f = 4.034 v, and the reset value = 3.073 v. due to impedance between the pcb and the internal dcdc regulation circuit, the measured supply voltage off chip will be typically higher than the programmed voltage due to ir drop. thus, the magnitude of this drop will depend on board layout as well as application current requirements. when using the linear regulators, this field is interpreted with a one-step offset, such that 0x00 = 2.113 v, 0x1e-0x1f = 4.034 v, and the reset value of x10=3.137 v. however, it should be noted the linear regulators have an output impedance of near one ohm, so the supply voltages will also sag depending on the magnitude of current being drawn from the linear regulators. these target voltage values represent a mean value, but individual parts will have slight part-to- part variations with a sigma of around 12 mv from either switching converters or linear regulators. note that the offset between switching converters and linear regulators can be reversed using linreg_offset. 15:13 rsrvd2 ro 0x0 empty description. free datasheet http:/// STMP36XX official product documentation 5/3/06 768 chapter 31: power supply 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 31.8.6. dc-dc#1 multioutput converter modes control register description this register contains controls that may need to be adjusted when using dc-dc converter configurations that support two outputs using a single inductor. for single output/single inductor modes, this register should be left in its default state. hw_power_dc1multout 0x80044050 12:8 vddd_bo rw 0x10 voltage level of the brownout for the vddd supply. 0x00 - 0x08 = 1.280 v. 0x09 - 0x1d = 32m v / per step above 0x08. 0x1e = 2.108 v, 0x1f = 2.20 v, and the reset value is 1.536 v. the decode is identical when using linear regulators or the switching dc-dc converters and is not affected by linreg_offset. these values represent a mean value, but individual parts will have slight part -to-part variations with a sigma of around 6 mv from either switching converters or linear regulators. 7:5 rsrvd1 ro 0x0 empty description. 4:0 vddd_trg rw 0x16 voltage level of the vddd supply. the step size of this field is 32 mv. when using the switching converters, 0x00 - 0x08 = 1.280 v. 0x09 - 0x1d = 32 mv / per step above 0x08. 0x1e = 2.108 v, 0x1f = 2.20 v, and the reset value of x16=1.728 v. due to impedance between the pcb and the internal dcdc regulation circuit, the measured supply voltage off chip will be typically higher than the programmed voltage due to ir drop. thus, the magnitude of this drop will depend on board layout as well as application current requirements. when using the linear regulators, this field is interpreted with a one step offset such that 0x00 - 0x08 = 1.309 v. 0x09 - 0x1c = 32 mv / per step above 0x08. 0x1d=2.108 v 0x1e-0x1f = 2.20 v, and the reset value is 1.760 v. however, it should be noted the linear regulators have an output impedance of near one ohm, so the supply voltages will also sag depending on the magnitude of current being drawn from the linear regulator. these values represent a mean value, but individual parts will have slight part-to-part variations with a sigma of around 6mv from either switching converters or linear regulators. note that the offset between switching converters and linear regulators can be reversed using linreg_offset. programming vddd_trg to a value above 2.0 volts is not intended for customer applications. table 982. hw_power_vddct rl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 769 description: empty description. example: empty example. table 983. hw_power_dc1multout 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd3 funcv rsrvd2 en_batadj rsrvd1 adjtn table 984. hw_power_dc1multout bit field descriptions bits label rw reset definition 31:25 rsrvd3 ro 0x0 empty description. 24:16 funcv rw 0x000 this field should be programmed before en_batadj and should be updated whenever the target values for the supplies are changed. for mode 01, single- inductor li-ion, write (vddio - vdd)/8e-03, and for mode 11, nimh, write (vddio*vdd)/((vddio- vdd)*8e-03)). the values of vddio and vddd are in volts, and the final result can be rounded. note that this field cannot be programmed above x1ff. for example, for a vddio target voltage of 3.07 v in mode 11, funcv will not reach x1ff until vddd > 1.74 v. if it desired to use a higher value of vddd, set funcv=x1ff and begin to use adj_tn after consulting sigmatel. 15:9 rsrvd2 ro 0x00 empty description. 8 en_batadj rw 0x0 this bit enables dc-dc#1 to improve efficiency and minimize ripple in the double output / single inductor configurations. both of these features require that the lradc be enabled and constantly monitoring the battery voltage. the battery voltage should be written to the batt_val field in the batt_monitor register using 8-mv step size. the funcv field in this register must also be written correctly when powering from the dc-dc converter in modes 01 or 11. it is not recommended to use the bit at the same time as en_dc1_pfm 7:4 rsrvd1 ro 0x0 empty description. 3:0 adjtn rw 0x0 two's complement number that can be used to adjust the duty cycle of vddio when using modes 01 or 11. this can be used to optimize efficiency performance of the double output boost converter after the funcv input is limited at 0x1ff. free datasheet http:/// STMP36XX official product documentation 5/3/06 770 chapter 31: power supply 5-36xx-d1-1.02-050306 31.8.7. dc-dc#1 duty cycle limits control register description this register defines the upper and lower duty cycle limits of dc-dc#1. these val- ues depend on details of switching converter implementation and should not be changed without guidance from sigmatel. hw_power_dc1limits 0x80044060 description: empty description. example: empty example. 31.8.8. dc-dc#2 duty cycle limits control register description this register defines the upper and lower duty cycle limits of dc-dc#2. these val- ues depend on details of switching converter implementation and should not be changed without guidance from sigmatel. hw_power_dc2limits 0x80044070 table 985. hw_power_dc1limits 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 en_pfetoff rsrvd3 poslimit_boost rsrvd2 poslimit_buck rsrvd1 neglimit table 986. hw_power_dc1limits bit field descriptions bits label rw reset definition 31:25 rsrvd4 ro 0x0 empty description. 24 en_pfetoff rw 0x0 enables dc-dc#1 vddd pfet to turn off when battery is greater than vddd target voltage in double output boost mode. this bit will allow vddd to be less than the battery voltage even though dc-dc#1 is configured as a boost converter. this bit should only be used in double output boost configuration, mode 3. 23 rsrvd3 ro 0x0 empty description. 22:16 poslimit_boost rw 0x02 upper limit duty cycl e limit in dc-dc#1 in boost mode. 15 rsrvd2 ro 0x0 empty description. 14:8 poslimit_buck rw 0x1e upper limit duty cycle limit in dc-dc#1 in buck mode. 7 rsrvd1 ro 0x0 empty description. 6:0 neglimit rw 0x5f negative dut y cycle limit of dc-dc#1. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 771 description: empty description. example: empty example. 31.8.9. converter loop behavior control register description this register defines the control loop parameters available for dc-dc#1 and dc- dc#2. hw_power_loopctrl 0x80044080 hw_power_loopctrl_set 0x80044084 hw_power_loopctrl_clr 0x80044088 hw_power_loopctrl_tog 0x8004408c table 987. hw_power_dc2limits 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd4 en_boost rsrvd3 poslimit_boost rsrvd2 poslimit_buck rsrvd1 neglimit table 988. hw_power_dc2limits bit field descriptions bits label rw reset definition 31:25 rsrvd4 ro 0x0 empty description. 24 en_boost rw 0x0 enables buck-boost operation in mode 00 li-ion configuration. this is intended to allow vddio to support hard drive current loads with li-ion battery voltages down below 3.0 v. both ends of the inductor must be connected to different pairs of integrated switching fets to permit this functionality. poslimit_buck will need to be increased to allow the control loop to operate in the boost region. 23 rsrvd3 ro 0x0 empty description. 22:16 poslimit_boost rw 0x02 upper limit duty cycl e limit in dc-dc#2 in boost mode. 15 rsrvd2 ro 0x0 empty description. 14:8 poslimit_buck rw 0x1e upper limit duty cycl e limit in dc-dc#2 in buck mode 7 rsrvd1 ro 0x0 empty description. 6:0 neglimit rw 0x5f negative dut y cycle limit of dc-dc#2. free datasheet http:/// STMP36XX official product documentation 5/3/06 772 chapter 31: power supply 5-36xx-d1-1.02-050306 table 989. hw_power_loopctrl 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd5 tran_nohyst hyst_sign en_cmp_hyst en_dc2_rcscale en_dc1_rcscale rc_sign en_rcscale rsrvd4 dc2_ff dc2_r rsrvd3 dc2_c rsrvd2 dc1_ff dc1_r rsrvd1 dc1_c table 990. hw_power_loopctrl bit field descriptions bits label rw reset definition 31 rsrvd5 ro 0x0 empty description. 30 tran_nohyst rw 0x0 disables hysteresis when dc1_ok or dc2_ok is low. this will speed voltage transitions. 29 hyst_sign rw 0x0 invert the sign of the hysteresis in dc-dc analog comparators. this bit should set when using pfm mode. 28 en_cmp_hyst rw 0x0 enable hysteresis in switching converter analog comparators. this feature will improve transient supply ripple and efficiency. 27 en_dc2_rcscale rw 0x0 enables digital dc-dc#2 control loop to respond faster to heavy transient loads 26 en_dc1_rcscale rw 0x0 enables digital dc-dc#1 control loop to respond faster to heavy transient loads. it is not recommended to set this bit in li-ion applications unless using 15-uh inductors and capacitors larger than 22 uf. there are no restrictions when using this bit in alkaline battery applications. 25 rc_sign rw 0x0 invert the sign of the heavy load detection in the dc- dc analog circuits 24 en_rcscale rw 0x0 enable analog circuit of dc-dc converter to detect heavy load conditions. this field should be set high when either en_dc1_rcscale or en_dc2_rcscale is set. 23 rsrvd4 ro 0x0 empty description. 22:20 dc2_ff rw 0x0 two's complement feed-f orward step in duty cycle in dc-dc#2. each time this field makes a transition from 0x0, the loop filter of the dc-dc converter is stepped once by a value proportional to the change. this can be used to force a certain control loop behavior, such as improving response under known heavy load transients. 19:16 dc2_r rw 0x2 magnitude of proportional control parameter in dc- dc#2 control loop. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 773 description: empty description. example: empty example. 31.8.10. power subsystem status register description hw_power_sts 0x80044090 15:14 rsrvd3 ro 0x0 empty description. 13:12 dc2_c rw 0x0 ratio of integral control parameter to proportional control parameter in dc-dc#2. 00: nominal, 01: increase ratio, 10: decrease ratio, 11: lowest ratio. this setting is used to optimize efficiency and loop response. 11 rsrvd2 ro 0x0 empty description. 10:8 dc1_ff rw 0x0 two's complement feed forward step in duty cycle in dc-dc#1. each time this field makes a transition from 0x0, the loop filter of the dc-dc converter is stepped once by a value proportional to the change. this can be used to force a certain control loop behavior, such as improving response under known heavy load transients. 7:4 dc1_r rw 0x2 magnitude of proportional control parameter in dc- dc#1 control loop. 3:2 rsrvd1 ro 0x0 empty description. 1:0 dc1_c rw 0x0 ratio of integral control parameter to proportional control parameter in dc-dc#1. 00: nominal, 01: increase ratio, 10: decrease ratio, 11: lowest ratio. this setting is used to optimize efficiency and loop response table 991. hw_power_sts 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 batt_chrg_present rsrvd5 mode rsrvd4 batt_bo rsrvd3 chrgsts dc2_ok dc1_ok rsrvd2 vddio_bo vddd_bo rsrvd1 vdd5v_gt_vddio avalid bvalid vbusvalid sessend table 990. hw_power_loopctrl bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 774 chapter 31: power supply 5-36xx-d1-1.02-050306 description: empty description. example: table 992. hw_power_sts bit field descriptions bits label rw reset definition 31 batt_chrg_present ro 0x1 0= battery charge circuit is not present in this product. 30:22 rsrvd5 ro 0x0 empty description. 21:20 mode ro 0x0 battery configuration of system, 00= li-ion dual- converter, 01 = li-ion single-inductor, 10 = series aa or aaa , 11 = single aa or aaa 19:17 rsrvd4 ro 0x0 empty description. 16 batt_bo ro 0x0 output of battery brownout comparator. 15 rsrvd3 ro 0x0 empty description. 14 chrgsts ro 0x0 battery charging status. high during li-ion battery charge until the charging current falls below the stop_ilimit threshold. 13 dc2_ok ro 0x0 high when dc-dc#2 control loop has stabilized after a voltage target change. 12 dc1_ok ro 0x0 high when dc-dc#1 control loop has stabilized after a voltage target change. 11:10 rsrvd2 ro 0x0 empty description. 9 vddio_bo ro 0x0 output of vddio brownout comparator. high when a brownout is detected. this comparator defaults powered up, but can be powered down via the power_minpwr register. 8 vddd_bo ro 0x0 output of vddd brownout comparator. high when a brownout is detected. it is not possible to power-down this comparator. 7:5 rsrvd1 ro 0x0 empty description. 4 vdd5v_gt_vddio ro 0x0 indicates the voltage on the vdd5v pin is higher than vddio by a vt voltage, nominally 500 mv. however, if pwdn_iobrnout is set, this bit is high when the vdd5v pin is higher than the level indicated by vddio_bo, the brownout level of vddio. 3 avalid rw 0x0 indicates vbus is valid for a a-peripheral, high if vbus greater than 2.0, low if vbus less than 0.8, otherwise unknown. 2 bvalid rw 0x0 indicates vbus is valid for a b-peripheral, high if vbus greater than 4.0, low if vbus less than 0.8, otherwise unknown. 1 vbusvalid rw 0x0 vbus valid for usb otg. see power_5vctrl to enable and set threshold for comparison. 0 sessend rw 0x0 session end for usb otg. 0 if vbus is greater than 0.8 v, 1 if vbus is less than 0.2 v, otherwise unknown. see power_5vctrl to enable comparators. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 775 empty example. 31.8.11. temperature and transistor speed control and status register description this register contains the setup and c ontrols needed to measure die temperature and silicon speed. hw_power_speedtemp 0x800440a0 hw_power_speedtemp_set 0x800440a4 hw_power_speedtemp_clr 0x800440a8 hw_power_speedtemp_tog 0x800440ac table 993. hw_power_speedtemp 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 speed_sts1 speed_sts2 rsrvd2 temp_sts rsrvd1 speed_ctrl temp_ctrl table 994. hw_power_speedt emp bit field descriptions bits label rw reset definition 31:24 speed_sts1 ro 0x0 result from first speed sensor. this result is only valid when speedctrl=0b11; otherwise this field contains debug information from the switching dc-dc converters. 23:16 speed_sts2 ro 0x0 result from second speed sensor. this circuit is simply a duplicate of speed sensor 1, and is included for redundancy. this result is only valid when speedctrl=0b11; otherwise this field contains debug information from the switching dc-dc converters. 15:12 rsrvd2 ro 0x0 empty description. free datasheet http:/// STMP36XX official product documentation 5/3/06 776 chapter 31: power supply 5-36xx-d1-1.02-050306 description: empty description. example: 11:8 temp_sts ro 0x0 die temperature result: 0000: temp less than -40 0001: temp greater than -40 and less than or equal to -30 0010: temp greater than -30 and less than or equal to -20 0011: temp greater than -20 and less than or equal to -10 0100: temp greater than -10 and less than or equal to 0 0101: temp greater than 0 and less than or equal to 15 0110: temp greater than 15 and less than or equal to 25 0111: temp greater than 25 and less than or equal to 35 1000: temp greater than 35 and less than or equal to 45 1001: temp greater than 45 and less than or equal to 55 1010: temp greater than 55 and less than or equal to 70 1011: temp greater than 70 and less than or equal to 85 1100: temp greater than 85 and less than or equal to 95 1101: temp greater than 95 and less than or equal to 105 1110: temp greater than 105 and less than or equal to 115 1111: temp greater than 115 temp and less than 130 answer invalid when temp above 130 7:6 rsrvd1 ro 0x0 empty description. 5:4 speed_ctrl rw 0x0 speed control bits. 00: speed sensor off, 0b01: speed sensor enabled, 11: enable speed sensor measurement. every time a measurement is taken, the sequence of 0x00 ; 01 ; 11 must be repeated. this sequence should proceed no faster than 1.5 mhz to ensure proper operation. 3:0 temp_ctrl rw 0x0 control bits to enable temperature sensor: bit 3: 1=pwd, 0=operational bit 2: 1=shift warmer mode, 0=shift cooler mode bits 1:0: 00=no shift, 01=shift by 1, 10=shift by 1+2, 11=shift by 1+2+3 (shift unit is 3 degrees c) bits 2,1,0 are used only to cancel offsets in the system and should not be set at this time. table 994. hw_power_speedt emp bit field descriptions bits label rw reset definition free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 777 empty example. 31.8.12. battery level monitor register description this register provides brownout controls and monitors the battery voltage. hw_power_battmonitor 0x800440b0 table 995. hw_power_battmonitor 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd3 batt_val rsrvd2 pwdn_battbrnout brwnout_pwd rsrvd1 brwnout_lvl table 996. hw_power_battmonitor bit field descriptions bits label rw reset definition 31:26 rsrvd3 ro 0x0 empty description. 25:16 batt_val rw 0x0 software should be configured to place the battery voltage in this register measured with an 8-mv lsb resolution. this value is used by the dc-dc converters and must be correct to ensure correct operation of the converters 15:10 rsrvd2 ro 0x0 empty description. 9 pwdn_battbrnout rw 0x1 powers down the device after the dc-dc converters complete startup if a battery brownout occurs before the system is completely in itialized. this function is only active when 5v is not present. additionally, software should clear this bit and disable this function after a battery brownout interrupt is enabled. 8 brwnout_pwd rw 0x0 power-down bit for battery brownout detector. 7:4 rsrvd1 ro 0x0 empty description. 3:0 brwnout_lvl rw 0x0 the default setting of the brownout settings decode to a voltage as follows: single-alkaline/nimh = 0.8 v dual-alkaline/nimh = 1.6 v li-ion = 2.8 v the voltage level can be calculated for other values by the following equation: single alkaline nimh brownout voltage = 0.8v + 0.02 * brwnout_lvl dual alkaline nimh brownout voltage = 1.6v + 0.04 * brwnout_lvl li-ion brownout voltage = 2.8v + 0.04 * brwnout_lvl free datasheet http:/// STMP36XX official product documentation 5/3/06 778 chapter 31: power supply 5-36xx-d1-1.02-050306 description: empty description. example: empty example. 31.8.13. power module reset register description this register allows software to put the chip into the off state. hw_power_reset 0x800440c0 hw_power_reset_set 0x800440c4 hw_power_reset_clr 0x800440c8 hw_power_reset_tog 0x800440cc description: table 997. hw_power_reset 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 unlock rsrvd1 pwd_off por pwd rst_dig rst_all table 998. hw_power_reset bit field descriptions bits label rw reset definition 31:16 unlock rw 0x0 write 0x3e77 to unlock this register and allow other bits to be changed. note: this register must be unlocked on a write-by-write basis, so the unlock bitfield must contain the correct key value during all writes to this register in order to update any other bitfield values in the register. key = 0x3e77 key needed to unlock hw_power_reset register. 15:5 rsrvd1 ro 0x0000 empty description. 4 pwd_off rw 0x0 optional bit to disable all paths to power off the chip except the watchdog timer. setting this bit will be useful for preventing fast falling edges on the pswitch pin from resetting the chip. it may also be useful increasing system tolerance of noisy emi environments. 3 por rw 0x0 clears the persistent bits. similar to removing and re- inserting the battery. 2 pwd rw 0x0 powers down the chip. 1 rst_dig rw 0x0 resets all non-power module digital registers and reboots the cpu. it is necessary to clear en_batadj and pwdn_5vbrnout before asserting this bit. 0 rst_all rw 0x0 resets all digital registers, including the power module, and reboots the cpu. it is not recommended to use rst_all, instead rst_dig should be used to reset and reboot the device. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 779 empty description. example: empty example. 31.8.14. power module debug register description debug register. hw_power_debug 0x800440d0 hw_power_debug_set 0x800440d4 hw_power_debug_clr 0x800440d8 hw_power_debug_tog 0x800440dc description: empty description. example: empty example. power xml revision: 1.67 table 999. hw_power_debug 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 rsrvd0 enctrlvbus vbusvalidpiolock avalidpiolock bvalidpiolock sessendpiolock table 1000. hw_power_de bug bit field descriptions bits label rw reset definition 31:5 rsrvd0 ro 0x0 empty description. 4 enctrlvbus rw 0x0 use the chrgvbus and dischrgvbus control from the usb controller (arc) instead of the power control register. 3 vbusvalidpiolock rw 0x0 empty description. 2 avalidpiolock rw 0x0 empty description. 1 bvalidpiolock rw 0x0 empty description. 0 sessendpiolock rw 0x0 empty description. free datasheet http:/// STMP36XX official product documentation 5/3/06 780 chapter 31: power supply 5-36xx-d1-1.02-050306 31.9. dc-dc conver ter efficiency the graphs in this section show typical efficiency plots vs. the battery voltage for the dc-dc converters configured in different modes. these graphs show measurements made with typical devices at room temperature with specific static loads. therefore, these graphs should not be interpreted as specifications, but as estimates of typical efficiencies under nominal conditions. it should be noted that the 24-mhz xtal bias current is counted as a loss term in the efficiency calculation, and thus the light load efficiency curves are somewhat pessimistic. 31.9.1. dc-dc1 mode 3 efficiency figure 136 and figure 137 show the efficiency of the dc-dc converter #1 in mode 3 versus battery voltage for several values of output power. the test conditions for the two graphs are identical except for the load to which the power is delivered. because the power fet that connects the inductor to the dcdc_vddio output has a higher resistance than the fet that connects the inductor to the dcdc_vddd output, the efficiency of the dc-dc converter is improved when the same power is delivered to the low-voltage output, vddd, relative to the high-voltage output, vddio. it should be noted that the boost configur ation of dc-dc #1 could be the least effi- cient heavy load configuration for two reasons. first, boost mode power conversion only transfers power to the load during one phase of the converters charge/dis- charge cycle. therefore, conservation of charge requires an inductor current that is higher than the load current, so i 2 r losses in the power fets that switch the induc- tor are increased relative to a buck mode configuration where current is transferred to the load during the entire charge/discharge cycle. secondly, since mode 3 gener- ates multiple outputs using one external inductor, the inductor current must increase figure 136. efficiency of dc-dc #1 in mode 3 for various vddd loads free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 781 to support multiple lo ad currents. thus, i 2 r losses are also increased when using the multiple output configurat ions relative to the configur ations that have one induc- tor per output voltage. therefore, mode 3 is primarily intended for lower power appli- cations that use a single battery and single inductor to achieve an ultra small form factor. 31.9.2. dc-dc1 mode 1 efficiency figure 138 and figure 139 show the efficiency of the dc-dc converter #1 in mode 1 versus battery voltage for several values of output power. the test conditions for the two graphs are identical except for the load to which the power is delivered. because the power fet that connects the inductor to the dcdc_vddio output has a higher resistance than the fet that connects the inductor to the dcdc_vddd output, the efficiency of the dc-dc converter is improved when the same power is delivered to the low-voltage output, vddd, relative to the high-voltage output, vddio. mode 1 supports higher output power than mode 3 because mode 1 operates with a li-ion battery range. thus, the dc-dc conv erter generally operates in a buck con- figuration, which causes inductor current to be reduced and thus i 2 r losses in the fets are higher. however, operating in buck mode shows decreased efficiency as the battery voltage rises, as there is capacitive loss driving the power fets that increases as the battery voltage increases. additional efficiency measurements have show n that the use of a higher inductor value than 4.7 uh can improve efficiency a few percent under light load conditions. figure 137. efficiency of dc-dc #1 in mode 3 for various vddio loads free datasheet http:/// STMP36XX official product documentation 5/3/06 782 chapter 31: power supply 5-36xx-d1-1.02-050306 figure 138. efficiency of dc-dc #1 in mode 1 for various vddd loads figure 139. efficiency of dc-dc #1 in mode 1 for various vddio loads free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 783 31.9.3. dc-dc1 mode 2/mode 0 efficiency figure 140 shows the efficiency for dc-dc #1 co nfigured as a single-channel buck converter. since dc-dc #1 is configured identically in modes 2 and 0, this graph is applicable in both modes. 31.9.4. dc-dc2 mode 2 efficiency figure 141 shows the efficiency of dc-dc #2 fo r various values of output power. since dc-dc #2 has a pfet with less on-resistance than the comparable dc-dc #1 pfet, and this configuration is a single-load converter, this mode is preferred for higher power vddio loads over mode 3 or 1. figure 140. effici ency of dc-dc #1 in mode 2/mo de 0 for various vddd loads free datasheet http:/// STMP36XX official product documentation 5/3/06 784 chapter 31: power supply 5-36xx-d1-1.02-050306 31.9.5. dc-dc2 mode 0 efficiency figure 142 shows the efficiency of dc-dc #2 fo r various values of output power. this converter configuration is intended fo r high power output applications, even as the li-ion battery voltage drops. for this reason, this converter is a buck-boost and can sustain a constant output voltage as the battery voltage decreases, even under heavy load conditions. figure 141. efficiency of dc-dc #2 in mode 2 for various current loads free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 31: power supply 785 31.9.6. max power out in boost modes for a boost mode converter, the power delivered to the load can be estimated using the following equation: in this equation, ?d? represents the duty cycle of dc-dc converter, vout represents the output voltage of the converter, rn and rp represent the on-resistance of the power fets appropriate for the particular dc-dc converter configuration, and rl represents the on-resistance of the dc-dc inductor. for multiple boost output mode 3, this equation is a reasonable approximation if it is assumed that all the power is transferred to one of the loads. this equation leads to the following expression for the duty cycle that gives to the maximum power trans- ferred to the load: substituting dmax into the equation for pout gives a maximum power that can be theoretically delivered to the load. note that this equation was derived using only v=ldi/dt and conservation of charge, and thus represents a theoretical maximum that neglects many significant sources of loss including frequency dependent core losses, bond wire ringing, switch non-overlap times, etc. from an application point of view, it is probably not desirable to operate the con- verter at the maximum power output, since i 2 r losses will also be maximized. figure 142. efficiency of dc-dc #2 in mode 0 for various current loads p out v out v bat 1 d ? () v out 1 d ? () 2 ? () r p r l dr n r p ? () ++ ------------------------------------------------------------------------------------------- = d max r p r n 1 v bat v out ------------- r p r n ? () r n ------------------------ + ? r p r n ? ------------------------------------------------------------------------------ - = free datasheet http:/// STMP36XX official product documentation 5/3/06 786 chapter 31: power supply 5-36xx-d1-1.02-050306 therefore, it is recommended to constrai n system power requirements to loads that can be supplied with efficiency 70% as shown in the graphs in figure 136 figure 137 and figure 141 . 31.9.7. max power out in buck modes unlike the boost case, the maximum output power from a buck mode configuration is limited simply by voltage difference between the load and the battery divided by the pfet on-resistance. thus, a buck-mode configuration can better supply large currents to the load than boost-mode configurations. p out v bat v out ? r p r l + -------------------------------- = free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 32: boot modes 787 32. boot modes this chapter describes the boot modes implemented on the STMP36XX. it includes sections on mode selection, the boot loader, and preparing bootable images. 32.1. overview the masked (on-chip) rom-resident boot l oader is responsible for booting from a subset of the peripherals attached to th e STMP36XX. peripherals supported by boot modes in current versions of the rom include: ?nand flash ?ata ?i 2 c eeprom ?nor flash ? special jtag debug spin loops ? sigmatel-only factory test modes special terms used in this chapter include the following: ? authentication signature ?a 4-byte value attached to each 508-byte block of boot commands. it is used to authenticate the contents of the 508-byte block of commands. ? cold boot ?the first chip power-up after external power has been supplied to the chip. ? warm boot ?chip power-up after cold boot. ? recovery mode ?a fail-safe rom boot mode that uses the sigmatel usb boot class. ? post (power on self test) ?tests the sram and provides repair vectors that may be used to repair the ram. the repair vectors are placed into persistent bits. ? repair ?repairs the sram by copying ram re pair vectors from persistent bits into the ram repair registers. 32.2. mode selection 32.2.1. boot pins and boot modes table 1001 shows the pins used to determine the boot mode. table 1001. boot pins 100-pin tqfp pin# 169-pin fpbga pin# pin label pinctrl bank:bit boot function bit name 11 22 gpmi_d07 0:7 enable ram repair erepair 10 20 gpmi_d06 0:6 test boot mode bit 2 tm2 9 18 gpmi_d05 0:5 test boot mode bit 1 tm1 8 16 gpmi_d04 0:4 test boot mode bit 0 tm0 7 14 gpmi_d03 0:3 boot mode bit 3 bm3 6 12 gpmi_d02 0:2 boot mode bit 2 bm2 3 8 gpmi_d01 0:1 boot mode bit 1 bm1 2 6 gpmi_d00 0:0 boot mode bit 0 bm0 free datasheet http:/// STMP36XX official product documentation 5/3/06 788 chapter 32: boot modes 5-36xx-d1-1.02-050306 these pads are powered during the initial loader sequence. the pads are enabled as gpios for sensing, and then disabled. however, the pads remain powered. the tbmx pins are not powered or configured as gpio unless bmx=0xf. the boot modes are shown in ta b l e 1 0 0 2 . 32.2.1.1. persistent bits persistent bits are used to control certain features in the rom, as shown table 1003 . for more information on the persistent bits, see chapter 19 , ?real-time clock, alarm, watchdog, and persistent bits? on page 497 . table 1002. boot modes tbm2 tbm1 tbm0 bm3 bm2 bm1 bm0 port boot mode x x x 0 0 0 0 usb stmp boot class xx x0001 i 2 ci 2 c master xx x0010 -reserved xx x0011gpmiata x x x 0 1 0 0 gpmi nand 3.3 volt xx x0101 eminor x x x 0 1 1 0 debug0 startup waits for jtag debugger connection. x x x 0 1 1 1 debug1 loader waits for jtag debugger connection xx x1000 -reserved xx x???? ?reserved xx x1110 -reserved 0 0 0 1 1 1 1 gpio tester loader (sigmatel use only) 0 0 1 1 1 1 1 gpio burn in (sigmatel use only) 0 1 0 1 1 1 1 gpio rom crc (sigmatel use only) 0 1 1 1 1 1 1 gpio ram test (sigmatel use only) 1 0 0 1 1 1 1 gpio bist (sigmatel use only) 1 0 1 1 1 1 1 uart uart (sigmatel use only) (currently not supported) will use standard sigmatel boot images. 11 01111 -reserved 11 11111 -reserved free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 32: boot modes 789 table 1004 shows how the persistent bits and the erepair pin are used in the rom. table 1003. persistent bits used by the rom persistent bit bit field name function hw_rtc_persistent2[31] wboot warm boot. hw_rtc_persistent0[31] sdboot sdram boot. if set, then the loader ignores the boot mode set by the boot pins. it will power up the sdram and jump to sdram_boot_strap(). hw_rtc_persistent0[24,23] sdram_cs_hi, sdram_cs_lo two-bit binary encoding of the chip select the boot rom should use when addressing the sdram. valid values are 0, 1, 2, and 3. hw_rtc_persistent0[22?19] sdram_ndx_3,2,1,0 four-bit binary encoding of the table index of sdram controller programming parameters. this table is stored internally in the rom. a value of b'111 is an indication to the loader to disregard its internal table and use the values stored in the ram_patch[] single- entry table located in th e sram section.bss.sdram. hw_rtc_persistent0[18] etm_enable if set, th e rom enables the embedded trace macrocell (etm) block. table 1004. ram post and repair test mode fpost frepair erepair usb wboot run post run repair description 0 1 x x x x 1 1 perform post and repair every time. don't copy repair vectors to persistent bits or set the warm boot. 0 0 0 0 x x 0 0 no post or repair. 0 0 0 1 0 x 1 1 perform post and repair, copy repair vectors to persistent bits, set warm boot persistent bit. 0 0 0 1 1 0 1 1 perform post and repair, copy repair vectors to persistent bits, set warm boot persistent bit. 0 0 0 1 1 1 0 1 no post. copy repair vectors from persistent bits to sram. 0 0 1 x 0 x 1 1 perform post and repair, copy repair vectors to persistent bits, set warm boot persistent bit. 0 0 1 x 1 0 1 1 perform post and repair, copy repair vectors to persistent bits, set warm boot persistent bit. free datasheet http:/// STMP36XX official product documentation 5/3/06 790 chapter 32: boot modes 5-36xx-d1-1.02-050306 where: test mode =true(1) if one of the special boot modes is selected via boot mode pins, false (0) otherwise. fpost = true(1) if result of bit-wise or of force_post and alt_force_post is true, false(0) otherwise. frepair = true (1) if result of bit-wise or of force_repair and alt_force_repair is true, false(0) otherwise. erepair = logical value of erepair pin (gpio0, bit 7). usb = true(1) if usb connection is detected, false(0) otherwise. wboot = value of persistent2, bit 31 32.3. boot loader the primary function of the boot loader is to load blocks of data into on-chip ram. it is also capable of initializing a block of memory to a specified value. data may be loaded/initialized to other parts of the me mory map, provided they are accessible (the loader will blindly do as instructed , so beware). the boot loader can initialize the emi to support an external sdram through code loaded and executed from the boot device. once initialized, the boot loader can load code and data directly to the sdram for subsequent execution. the boot loader is invoked to load from one of the supported peripheral devices and reads a stream of commands from an encrypted and authenticated image found on the desired boot device. one command can fill a block of physical address space (any memory) or it can copy a block code/ data from the peripheral storage device into any memory in the processors physical address space. at the end of loading an image, there is a command that can be used to branch into the loaded code and begin execution. 32.3.1. transition from boot loader to runtime image the boot loader is designed to ensure a well-defined hardware and software state before transitioning to the loaded runtime image using the following: ? the loader assumes the mmu is off. however, nothing precludes a boot image from containing one-shot code to turn it on. the loader does not turn off the mmu, so the user must take care when doing this. 0 0 1 x 1 1 0 1 no post. copy repair vectors from persistent bits to sram. 1 x x 0 x x 0 0 no post, no repair. 1 x x 1 x 0 1 1 perform post and repair, copy repair vectors to persistent bits, set warm boot persistent bit. 1 x x 1 x 1 0 1 no post. copy repair vectors from persistent bits to sram. table 1004. ram post and repair (continued) test mode fpost frepair erepair usb wboot run post run repair description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 32: boot modes 791 ? the loader turns on the instruction cache unless prohibited by laser fuse. the loader does not enable the data cache, but nothing precludes a boot image from containing one-shot code to turn it on. the loader does not turn off the data cache. the user must take care when do ing this. note: the mmu must be on for the data cache to be on. ? the runtime image may temporarily make use of the stacks and vectors left behind by the rom, but it is expected that the runtime image will establish its own environment, and the rom resources w ill then be discarded. ? fiq and irq are turned off. ? debug uart is disabled. ? the loader zeroes out the memory holding the encryption master key set. 32.3.2. constructing image to be loaded by boot loader the image is stored in an encrypted form t hat includes an authenticating hash. sig- matel supplies a program called elftosb to convert a fully resolved executable binary image into a boot image usable by the boot loader. a key set must be input to the elftosb program to properly encrypt and aut henticate the image. a default key set is supplied with elftosb . the process of creating a boot loader image is shown in figure 144 . ghs tools c and asm gnu tools libs elf libs elf elftosb load image (sb) figure 144. creating a boot loader image free datasheet http:/// STMP36XX official product documentation 5/3/06 792 chapter 32: boot modes 5-36xx-d1-1.02-050306 32.3.3. on-chip ram used by boot loader the loader initializes the supervisor mode, irq, fiq, and abort stacks. together, these occupy approximately 2 kbytes at address 0x0003d000. customer code is free to change these assignments as soon as it begins execution. in addition, for its own internal operatio n, the boot loader c onsumes, approximately 20 kbytes located at 0x0003b000. this area must not be overloaded by a boot load operation, but can be used for any purpose immediately after the load completes. 32.4. preparing bootable images preparing a bootable image for all boot modes (except special nor boot mode, as described below) includes the following high-level steps: ? prepare the elf file for the firmware that is to be booted by the STMP36XX rom. ? run the elf file through the elftosb program (available from sigmatel), which generates an encrypted sb file that can be booted from rom. any additional requirements for individual boot modes are identified in sections that follow. 32.4.1. i 2 c eeprom boot mode i 2 c eeprom boot mode does not require any special configuration. to boot from i 2 c eeprom, simply write the sb f ile to the appro priate device. 32.4.2. regular nor boot mode regular nor boot mode does not require any special configuration. to boot from regular nor, simply write the sb file to the appropriate device. 32.4.3. stmp (usb recovery) boot mode with stmp boot mode, also known as usb recovery mode, the user can configure a boot mode that always boots from usb. st mp boot mode requires that an sb file be sent to the 36xx and is otherwise treated like a boot from any other regular boot device. 32.4.4. ata hard disk drive boot mode after preparing the encrypted image through elftosb , the user simply writes that image onto a compactflash/ata device as co nsecutive sectors, starting at the loca- tion specified below. to prepare a cf/ata device for booting with the STMP36XX: ? add a partition entry to the master boot record with a drive type of 0x53 (?s?). ? in all other ways, the partition table entry should meet all the specifications required for a partition table by applicable specifications from the personal computer world. in particular, bios specifications may detail the use of the partition table. ? make the ?s? partition at least the size of the firmware plus four sectors, because the rom expects to find the first byte of the .sb file at the beginning of the fifth sector of the s partition. (the first four sectors form the ldt, or logical drive table, used by sigmatel firmware to describe the s partition layout.) free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 32: boot modes 793 this is all the information needed to locate and boot from a cf/ata device. how- ever, the rom may parse the ldt header. th e beginning of the ldt is at sector 0 of the s partition. the header is as follows: struct { uint32_t magic; // ?stmp? or 0x504d5453 uint32_t version; uint32_t sectorlba// points to the current lba + 4 uint32_t reserved; } the version field is not relevant to booting from rom. figure 145 shows the ata media layout. ` mbr ? partition table 0 partition table entry 1 partition table entry 0 sigmatel boot image (.sb file) sigmatel logical drive table (ldt) n n+4 reserved n+1..3 partition 1 (sigmatel system drives) partition 0 (data drive holding file system) fatx boot sector m figure 145. ata media layout free datasheet http:/// STMP36XX official product documentation 5/3/06 794 chapter 32: boot modes 5-36xx-d1-1.02-050306 32.4.5. large-block nand boot mode large-block nands use 2k pages and are a preferred nand type for portable media players because of their large ca pacities. these devices generally do not allow partial writes, meaning that all 2k bytes must be written at one time. after preparing the encrypted file through elftosb , the user writes the image onto the nand as specified in this section. to prepare a large-block nand device for booting with the STMP36XX: ? prepare and write a boot control block (bcb) to block 0 of the nand. crc and ecc must be calculated for the pages written. (see the sample crc code in section 32.4.5.5 ). ? program the nand on a page-by-page basis (one page has four sectors) at the starting location specified in the bcb (see section 32.4.5.4 ). be sure to calculate the ecc for each sector written to the nand (four times for each page) using the layout specified in this sect ion. also, be certain to fill out the metadata fields once per page and include that in the appropriate ecc calculation (see below). ? ecc is calculated over 512 bytes for the first three sectors of a page. ecc for the last sector should also include the physic ally first 7-byte metadata field for the page. tip: set the other three 7-byte me tadata fields to 0, and the ecc can include those bytes, making for uniform dma descriptors. 32.4.5.1. nand page layout figure 146 illustrates an lb nand with generalized page layout detail. (the special- ized page layout required by the bcb is described in section 32.4.5.4 .) lb nands are composed of blocks and typically have the following characteristics, as illustrated in figure 146 : ? 1 block = 128 kbytes, organized as 64 pages ? 1 page = 2112 bytes, of which 2048 bytes are data and 64 bytes are redundant area (ra) page 0 system blocks application space boot control block (bcb) page 0 generalized page layout number of bytes 512 512 512 512 7 7 7 7 9999 sector 1 sector 2 sector 3 sector 4 metadata 4 metadata 1 metadata 2 metadata 3 2112 bytes ecc 1 ecc 2 ecc 3 ecc 4 00 blk# s t m p STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 32: boot modes 795 ? 1 sector = 512 bytes of data ? 1 ra metadata field = 7 bytes ? 1 ra ecc field = 9 bytes ? each page is composed of 4 sectors, 4 metadata fields, and 4 ecc fields. ? the redundant area of the page includes the four 7-byte metadata fields and the four 9-byte ecc fields. ? physical block 0 is the bcb (boot control block) ? page 0 of this block is defined in a special way (different from pages in system blocks). see the specialized bcb page layout in figure 148 . ? blocks 1 through n in the system block are typically for the boot code, which is generated by taking the boot applicat ion, running it through the sigmatel- supplied elftosb program with a cipher key to generate an encrypted file. pages in these blocks follow the generalized page layout, as shown in figure 146 . note: blocks in the system block area start numbering from 0. blocks n+1 through the end of the device ar e typically for application space (usually a file system) and are not described here. 32.4.5.2. data in keeping with the rom requirement that all data is accessed in 512 byte chunks, each 2112-byte page consists of four 512-byte data sectors and a 64-byte redun- dant area. lb nands require that the entire 2112 bytes be written at once. the first three eccs cover their respective 512-byte data areas only, as shown in figure 147 . the last 512 bytes are paired with the metadata bytes (m4 in figure 147 ). the fourth ecc covers this entire grouping. 32.4.5.3. redundant area (ra) the redundant area consists of the last 64 bytes of the 2112 bytes in a page. the 64 redundant bytes start with the metadata bytes (m4 in figure 147 ) and extend through ecc4. m4 refers to the seven metadata bytes in the ra immediately follow- ing the data. only one metadata block is required per 2048 data bytes, which leaves 21 bytes of extra area for future use. currently, these extra bytes are set to zero, but they can be any value as long as they ar e included in the ec c calculation. future use of these bytes by sigmatel is possible. the redundant area the rom expects for the boot image sectors is defined in table 1005 . m4 ecc1 data ? 512 bytes data ? 512 bytes data ? 512 bytes data ? 512 bytes extra ecc1 ecc2 ecc3 ecc4 ecc2 ecc3 ecc4 figure 147. ecc coverage for nand pages free datasheet http:/// STMP36XX official product documentation 5/3/06 796 chapter 32: boot modes 5-36xx-d1-1.02-050306 as shown in table 1005 , the first byte contains the block status byte set to ?0x00?, which normally denotes a bad block, but when combined with the proper tag in bytes 2050?2053, is used to denote a proper boot image. the first byte in the meta- data area is the block status byte, because that position is typically used by the fac- tory to mark blocks as bad. the second byte (block number) contains a counter that counts up from zero for each good block that the boot image resides in. the first block of sectors generally resides in block 1. (physical block 1 maps to logical system block 0.) table 1005. redundant area byte definitions byte # definition 2048 block status byte = 0x00 2049 block number 2050 stmp tag 0 ?s? 2051 stmp tag 1 ?t? 2052 stmp tag 2 ?m? 2053 stmp tag 3 ?p? 2054 ra crc 2055?2075 extra area (0) 2076 rs_1_ecc1 2077 rs_1_ecc2 2078 rs_1_ecc3 2079 rs_1_ecc4 2080 rs_1_ecc5 2081 rs_1_ecc6 2082 rs_1_ecc7 2083 rs_1_ecc8 2084 rs_1_ecc9 2085 rs_2_ecc1 2086 rs_2_ecc2 2087 rs_2_ecc3 2088 rs_2_ecc4 2089 rs_2_ecc5 2090 rs_2_ecc6 2091 rs_2_ecc7 2092 rs_2_ecc8 2093 rs_2_ecc9 2094 rs_3_ecc1 2095 rs_3_ecc2 2096 rs_3_ecc3 2097 rs_3_ecc4 2098 rs_3_ecc5 2099 rs_3_ecc6 2100 rs_3_ecc7 2101 rs_3_ecc8 2102 rs_3_ecc9 2103 rs_4_ecc1 2104 rs_4_ecc2 2105 rs_4_ecc3 2106 rs_4_ecc4 2107 rs_4_ecc5 2108 rs_4_ecc6 2109 rs_4_ecc7 2110 rs_4_ecc8 2111 rs_4_ecc9 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 32: boot modes 797 the next four bytes contain the boot ta g, currently specified as bcb STMP36XX official product documentation 5/3/06 798 chapter 32: boot modes 5-36xx-d1-1.02-050306 32.4.5.5. bcb structure and initialization the following code describes the fields in the first sector of the bcb (block 0) on the nand. the structure below is packed. struct _bcb_sctruct { u32 m_u32signature1; struct { u16 m_u16major; u16 m_u16minor; u16 m_u16sub; } bcbversion; u32 m_u32nandbitmap;//bit 0 == nand 0, bit 1 == nand 1, bit 2 = nand 2, bit 3 = nand3 u32 m_u32signature2; u32 m_u32firmware_startingnand; u32 m_u32firmware_startingsector; u32 m_usectorsinfirmware; u32 m_ufirmwareboottag; struct { u16 m_u16major; u16 m_u16minor; u16 m_u16sub; } firmwareversion; u32 rsvd[10]; // set to zero u32 m_u32signature3; } bcb; #define bcb_signature1 0x504d5453// ?stmp? #define bcb_signature2 0x32424342// ?bcb ? #define bcb_signature3 0x41434143// ?caca? #define bcb_version_major 0x0001 #define bcb_version_minor 0x0000 #define bcb_version_sub 0x0000 it has been noted that since many of these elements are not aligned on word bound- aries, the compiled code is larger to handle these offsets. bcbversion structure?must be set to major = 1, minor = 0; sub = anything. u32nandbitmap?32-bit word detailing the nands that ar e in the system. bit0=nand0; bit1=nand1; bit2=nand2; bit3=nand3. therefore, a single nand implementation would be initialized with 0x00000001. m_u32firmware_starti ngnand?which nand holds the boot manager that will get downloaded. this is zero-based, so na nd0 will be 0, nand1 will be 1, etc. m_u32firmware_startingsector?which sector on the nand to start with. remem- ber that sectors from the rom?s perspective are 512 bytes. since the supported nands store data in 2k pages, this conversion will need a <<2 (or * 4). m_usectorsinfirmware?number of sectors (512 byte chunks) to be read by the rom. m_ufirmwareboottag?32-bit word consisting of stmp (stored as 0x504d5453) firmwareversion?not used by the rom. used for tracking the version of software. free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 32: boot modes 799 here is sample code to initialize the nand bcb: bcb.m_u32signature1 = bcb_signature1; bcb.bcbversion.m_u16major = bcb_version_major; bcb.bcbversion.m_u16minor = bcb_version_minor; bcb.bcbversion.m_u16sub = bcb_version_sub; bcb.m_u32nandbitmap = 0x00000001; bcb.m_u32signature2 = bcb_signature2; bcb.m_u32firmware_startingnand = 0; bcb.m_u32firmware_startingsector = 256;// assumes the f/w goes in first block after bcb bcb.m_usectorsinfirmware = g_num_sectors;// number of 512 byte sectors in f/w. round up! bcb.m_ufirmwareboottag = bcb_signature1; bcb.firmwareversion.m_u16major = 0; bcb.firmwareversion.m_u16minor = 0; bcb.firmwareversion.m_u16sub = 0; for (i=0; i < 10; i++) { bcb.rsvd[i] = 0; } bcb.m_u32signature3 = bcb_signature3; here is sample crc code: u8 crc(u8 *pra) { int i, wffcnt = 0; u8 // this is better as global data, but shown inside this function for clarity. crcvalues[256] = { 0x00,0x07,0x0e,0x09,0x1c,0x1b,0x12,0x15,0x38,0x3f,0x36,0x31,0x24,0x23,0x2a,0x2d, 0x70,0x77,0x7e,0x79,0x6c,0x6b,0x62,0x65,0x48,0x4f,0x46,0x41,0x54,0x53,0x5a,0x5d, 0xe0,0xe7,0xee,0xe9,0xfc,0xfb,0xf2,0xf5,0xd8,0xdf,0xd6,0xd1,0xc4,0xc3,0xca,0xcd, 0x90,0x97,0x9e,0x99,0x8c,0x8b,0x82,0x85,0xa8,0xaf,0xa6,0xa1,0xb4,0xb3,0xba,0xbd, 0xc7,0xc0,0xc9,0xce,0xdb,0xdc,0xd5,0xd2,0xff,0xf8,0xf1,0xf6,0xe3,0xe4,0xed,0xea, 0xb7,0xb0,0xb9,0xbe,0xab,0xac,0xa5,0xa2,0x8f,0x88,0x81,0x86,0x93,0x94,0x9d,0x9a, 0x27,0x20,0x29,0x2e,0x3b,0x3c,0x35,0x32,0x1f,0x18,0x11,0x16,0x03,0x04,0x0d,0x0a, 0x57,0x50,0x59,0x5e,0x4b,0x4c,0x45,0x42,0x6f,0x68,0x61,0x66,0x73,0x74,0x7d,0x7a, 0x89,0x8e,0x87,0x80,0x95,0x92,0x9b,0x9c,0xb1,0xb6,0xbf,0xb8,0xad,0xaa,0xa3,0xa4, 0xf9,0xfe,0xf7,0xf0,0xe5,0xe2,0xeb,0xec,0xc1,0xc6,0xcf,0xc8,0xdd,0xda,0xd3,0xd4, 0x69,0x6e,0x67,0x60,0x75,0x72,0x7b,0x7c,0x51,0x56,0x5f,0x58,0x4d,0x4a,0x43,0x44, 0x19,0x1e,0x17,0x10,0x05,0x02,0x0b,0x0c,0x21,0x26,0x2f,0x28,0x3d,0x3a,0x33,0x34, 0x4e,0x49,0x40,0x47,0x52,0x55,0x5c,0x5b,0x76,0x71,0x78,0x7f,0x6a,0x6d,0x64,0x63, 0x3e,0x39,0x30,0x37,0x22,0x25,0x2c,0x2b,0x06,0x01,0x08,0x0f,0x1a,0x1d,0x14,0x13, 0xae,0xa9,0xa0,0xa7,0xb2,0xb5,0xbc,0xbb,0x96,0x91,0x97,0x9f,0x8a,0x8d,0x84,0x38, 0xde,0xd9,0xd0,0xd7,0xc2,0xc5,0xcc,0xcb,0xe6,0xe1,0xe8,0xef,0xfa,0xfd,0xf4,0xf3 }, temp, crc, newindex; for(crc=0, i=0; i < 6; i++) { temp = pra[i]; newindex = crc ^ temp; crc = crcvalues[newindex]; if (temp == 0xff) wffcnt++; } ///////////////////////////////////////////////////////////////////////////////// // if the ra is all ffs, it's probably erased, so the crc byte will contain 0xff. // to match that, we force the computation to 0xff, here. ///////////////////////////////////////////////////////////////////////////////// if (wffcnt == 6) crc = 0xff; return (crc); } free datasheet http:/// STMP36XX official product documentation 5/3/06 800 chapter 32: boot modes 5-36xx-d1-1.02-050306 32.4.5.6. data organization in multiple nands the first sector of the boot image is in the first good block found in the array of nands, starting at nand0 and progressing to whatever other nands are reported to be present in the bcb, as illustrated in figure 149 . the next sector is drawn from the same block, until all sectors are drawn from the block. then, the block from the next nand is read, then the next nand, etc., returning to nand0 and repeating the process. if a block is de termined to be bad (either the block status byte of the block is marked bad or fails the ecc), then the algorithm skips to the next nand, etc. unused unused unused unused unused ... bad block bad block bcb bad block sector 0 sector 1 sector n-1 ... sector n sector n+1 sector 2n-1 sector 2n sector 2n+1 sector 3n-1 ... ... sector 3n sector 3n+1 sector 4n-1 ... sector 4n sector 4n+1 sector 5n-1 ... sector 5n sector 5n+1 sector 6n-1 ... sector 6n sector 6n+1 sector 7n-1 ... sector 7n sector 7n+1 sector 8n-1 ... sector 8n sector 8n+1 sector 9n-1 ... sector 9n sector 9n+1 sector 9n-1 ... nand0 nand1 nand2 nand3 figure 149. data organization in multiple nands free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 33: register macro usage 801 33. register macro usage this chapter provides ba ckground on the STMP36XX register set and illustra tes a consistent use of the c macros for registers. the examples provided here show how to use the hardware register mac- ros generated from the xml chip database. 33.1. definitions //////////////////////////////////////////////////////////////////////////////// // these macros will be generated from the xml in the future #define bf_gpmi_ctrl0_sftrst_v(v) (bv_gpmi_ctrl0_sftrst__##v << 31) #define bf_gpmi_ctrl0_clkgate_v(v) (bv_gpmi_ctrl0_clkgate__##v << 30) #define bf_gpmi_ctrl0_run_v(v) (bv_gpmi_ctrl0_run__##v << 29) #define bf_gpmi_ctrl0_udma_v(v) (bv_gpmi_ctrl0_udma__##v << 26) #define bf_gpmi_ctrl0_command_mode_v(v) (bv_gpmi_ctrl0_command_mode__##v << 24) #define bf_gpmi_ctrl0_word_length_v(v) (bv_gpmi_ctrl0_word_length__##v << 23) #define bf_gpmi_ctrl0_lock_cs_v(v) (bv_gpmi_ctrl0_lock_cs__##v << 22) #define bf_gpmi_ctrl0_address_v(v) (bv_gpmi_ctrl0_address__##v << 17) #define bf_gpmi_ctrl0_address_increment_v(v) (bv_gpmi_ctrl0_address_increment__##v << 16) #define bf_timrot_timctrln_select_v(v) (bv_timrot_timctrln_select__##v << 0) // these macros will be included in regs.h in the future #define or2(b,f1,f2) (b##_##f1 | b##_##f2) #define or3(b,f1,f2,f3) (b##_##f1 | b##_##f2 | b##_##f3) #define or4(b,f1,f2,f3,f4) (b##_##f1 | b##_##f2 | b##_##f3 | b##_##f4) //////////////////////////////////////////////////////////////////////////////// // prototypes //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // variables //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //! \brief provides examples of how to use the register access macros. //! //! \fntype function //! //! provides examples of how to use the register access macros. //////////////////////////////////////////////////////////////////////////////// void hw_regs_example(void) { int i, imode = 0, irun = 0; // 33.2. background the STMP36XX soc is built on a 32-bit architecture using an arm926 core. all hardware blocks are controlled and accessed through 32-bit wide register s. the design of these registers is maintained in an xml database that is part of the overall chip de sign. as part of the chip build process, a set of c include files are generated from the xml register descriptions. these include files provide a consis- tent set of c defines and macros that should be used to access th e hardware registers. the STMP36XX soc has a complex architecture that uses multiple buses to segment i/o traffic and clock domains. to facilitate low power consumption, clocks are set to just meet application demands. in general, the i/o buses and asso ciated hardware blocks run at s peeds much slower than the cpu. as a result, reading a hardware register incurs a potentially large number of wait cycles, as the cpu must wait for the register data to travel multiple buses and bridges. the soc does provide write buff- ering, meaning the cpu does not wait for register write transactions to complete. from the cpu per- spective, register writes occur much faster than reads. free datasheet http:/// STMP36XX official product documentation 5/3/06 802 chapter 33: register macro usage 5-36xx-d1-1.02-050306 most of the 32-bit registers are subdivided into sma ller functional fields. these bit fields can be any number of bits wide and are usually packed. thus, most fields do not align on byte or half-word boundaries. a common operation is to update one field without disturbing the contents of the remaining fields in the register. normally, this requires a read-modify-write (rmw) operation, where the cpu reads the register, modifies the target field, then writes the results back to the register. as already noted, this is an expensive operation in terms of cpu cycle s, because of the initial register read. to address this issue, most hardwa re registers are implemented as a set, including registers that can be used to either set, clear, or toggle (sct) individual bits of the primary register. when writing to an sct register, all bits set to 1 perform the associated operation on the primary register, while all bits set to 0 are not affected. the sct registers always read back zero, and should be considered write- only. the sct registers are not implemented if the primary register is read-only. with this architecture, it is possible to update one or more fields using only register writes. first, all bits of the target fields are cleared by a write to the associated clear register, then the desired value of the target fields is written to the set register. this sequence of two writes is referred to as a clear- set (cs) operation. a cs operation does have one potential drawback. whenever a field is modified, the hardware sees a value of 0 before the final value is written. for most fields, passing through the zero state is not a problem. nonetheless, this behavior is someth ing to consider when using a cs operation. also, a cs operation is not required for fields that are one bit wide. while the cs operation works in this case, it is more efficient to simply set or clea r the target bit (i.e., one write instead of two). a sim- ple set or clear operation is also atomic, while a cs operation is not. note that not all macros for set, clear, or toggle (sct) are atomic. for registers that do not provide hardware support for this functionality, these ma cros are implemented as a sequence of read/mod- ify/write operations. when atomic operation is r equired, the developer should pay attention to this detail, because unexpected behavior mi ght result if an inte rrupt occurs in the middle of the critical section comprising the update sequence. 33.3. naming convention the generated include files and macros follow a consistent naming convention that matches the soc documentation. this prev ents name-space collisio ns and makes the macros easier to remember. // // the include file for a specific hardware module is named: // // regs STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 33: register macro usage 803 // hw_ STMP36XX official product documentation 5/3/06 804 chapter 33: register macro usage 5-36xx-d1-1.02-050306 33.4.3. toggling 1-bit wide field // preferred (one atomic write to _tog register) hw_gpmi_ctrl0_tog(bm_gpmi_ctrl0_run); // alternate (same as above, just different syntax) bf_tog(gpmi_ctrl0, run); // avoid hw_gpmi_ctrl0.b.run ^= 1; // rmw 33.4.4. modifying n-bit wide field // preferred (does cs operation or byte/halfword write if the field is // 8 or 16 bits wide and properly aligned) bw_gpmi_ctrl0_command_mode(bv_gpmi_ctrl0_command_mode__read_and_compare); bw_gpmi_ctrl0_command_mode(imode); bw_gpmi_ctrl0_xfer_count(2); // this does a halfword write // alternate (same as above, just different syntax) bf_wr(gpmi_ctrl0, command_mode, bv_gpmi_ctrl0_command_mode__read_and_compare); bf_wr(gpmi_ctrl0, command_mode, imode); bf_wr(gpmi_ctrl0, xfer_count, 2); // this does a halfword write // avoid (rmw) hw_gpmi_ctrl0.b.command_mode = bv_gpmi_ctrl0_command_mode__read_and_compare; hw_gpmi_ctrl0.b.command_mode = imode; 33.4.5. modifying multiple fields // preferred (explicit cs operation) hw_gpmi_ctrl0_clr( or3(bm_gpmi_ctrl0, run, dev_irq_en, command_mode) ); hw_gpmi_ctrl0_set( or3(bf_gpmi_ctrl0, run(irun), dev_irq_en(1), command_mode_v(read_and_compare)) ); // alternate (same as above, just different syntax) bf_cs3(gpmi_ctrl0, run, irun, dev_irq_en, 1, command_mode, bv_gpmi_ctrl0_command_mode__read_and_compare); // avoid (multiple rmw - the c compiler does not merge into one rmw) hw_gpmi_ctrl0.b.run = irun; hw_gpmi_ctrl0.b.dev_irq_en = 1; hw_gpmi_ctrl0.b.command_mode = bv_gpmi_ctrl0_command_mode__read_and_compare; 33.4.6. writing entire register (all fields updated at once) // preferred hw_gpmi_ctrl0_wr(bm_gpmi_ctrl0_sftrst); // all other fields are set to 0 // alternate (same as above, just different syntax) hw_gpmi_ctrl0.u = bm_gpmi_ctrl0_sftrst; 33.4.7. reading a bit field // preferred irun = hw_gpmi_ctrl0.b.run; // alternate (same as above, just different syntax) irun = bf_rd(gpmi_ctrl0, run); // verbose alternate (example of using bit position (bp_) define) irun = (hw_gpmi_ctrl0_rd() & bm_gpmi_ctrl0_run) >> bp_gpmi_ctrl0_run; free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 33: register macro usage 805 33.4.8. reading entire register 0 // preferred i = hw_gpmi_ctrl0_rd(); // alternate (same as above, just different syntax) i = hw_gpmi_ctrl0.u; 33.4.9. accessing multiple instance register // preferred for (i = 0; i < hw_timrot_timctrln_count; i++) { // set 1-bit wide field hw_timrot_timctrln_set(i, bm_timrot_timctrln_irq_en); // write n-bit wide field bw_timrot_timctrln_prescale(i, bv_timrot_timctrln_prescale__div_by_1); // write multiple fields hw_timrot_timctrln_clr(i, or2(bm_timrot_timctrln, reload, select)); hw_timrot_timctrln_clr(i, or2(bf_timrot_timctrln, reload(1), select_v(1khz_xtal))); // read a field irun = hw_timrot_timctrln(i).b.irq; } // alternate (same as above, just different syntax) for (i = 0; i < hw_timrot_timctrln_count; i++) { // set 1-bit wide field bf_setn(timrot_timctrln, i, irq_en); // write n-bit wide field bf_wrn(timrot_timctrln, i, prescale, bv_timrot_timctrln_prescale__div_by_1); // write multiple fields bf_cs2n(timrot_timctrln, i, reload, 1, select, bv_timrot_timctrln_select__1khz_xtal); // read a field irun = bf_rdn(timrot_timctrln, i, irq); } 33.4.10. correct way to soft reset a block // a soft reset can take multiple clocks to complete, so do not gate the // clock when setting soft reset. the reset process will gate the clock // automatically. it is safe to issue these writes back-to-back. hw_gpmi_ctrl0_set(bm_gpmi_ctrl0_sftrst); hw_gpmi_ctrl0_clr(bm_gpmi_ctrl0_sftrst | bm_gpmi_ctrl0_clkgate); 33.5. summary preferred // setting, clearing, toggling 1-bit wide field hw_gpmi_ctrl0_set(bm_gpmi_ctrl0_udma); hw_gpmi_ctrl0_clr(bm_gpmi_ctrl0_dev_irq_en); hw_gpmi_ctrl0_tog(bm_gpmi_ctrl0_run); // modifying n-bit wide field bw_gpmi_ctrl0_xfer_count(2); // modifying multiple fields hw_gpmi_ctrl0_clr( or3(bm_gpmi_ctrl0, run, dev_irq_en, command_mode) ); hw_gpmi_ctrl0_set( or3(bf_gpmi_ctrl0, run(irun), dev_irq_en(1), command_mode_v(read_and_compare)) ); // reading a bitfield irun = hw_gpmi_ctrl0.b.run; // writing or reading entire register (all fields updated at once) hw_gpmi_ctrl0_wr(bm_gpmi_ctrl0_sftrst); i = hw_gpmi_ctrl0_rd(); free datasheet http:/// STMP36XX official product documentation 5/3/06 806 chapter 33: register macro usage 5-36xx-d1-1.02-050306 33.6. summary alternate syntax // setting, clearing, toggling 1-bit wide field bf_set(gpmi_ctrl0, udma); bf_clr(gpmi_ctrl0, dev_irq_en); bf_tog(gpmi_ctrl0, run); // modifying n-bit wide field bf_wr(gpmi_ctrl0, xfer_count, 2); // modifying multiple fields bf_cs3(gpmi_ctrl0, run, irun, dev_irq_en, 1, command_mode, bv_gpmi_ctrl0_command_mode__read_and_compare); // reading a bitfield irun = bf_rd(gpmi_ctrl0, run); // writing or reading entire register (all fields updated at once) hw_gpmi_ctrl0.u = bm_gpmi_ctrl0_sftrst; i = hw_gpmi_ctrl0.u; 33.7. assembly example // // the generated include files are safe to use with assembly code as well. not // all of the defines make sense in the assembly context, but many should prove // useful. // // hw_ STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 34: memory map 807 34. memory map table 1006 shows the memory map for the STMP36XX. table 1006. STMP36XX memory map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 00 alias space for copies of on-chip sram 256 kbyte on-chip sram 01 00 256mb sdram/nor/sync flash chip select 0 01 256mb sdram/nor/sync flash chip select 1 10 256mb sdram/nor/sync flash chip select 2 11 256mb sdram/nor/sync flash chip select 3 100 xxxxxxxxx 00 apbh decoder 0 interrupt collector xxxxx register selects set clear toggle byte apbh decoder 1 apbh dma apbh decoder 2 hwecc apbh decoder 3 gpmi apbh decoder 4 newspi apbh decoder 5 memcpy apbh decode 6 pincntrl apbh decoder 7 digctl apbh decode 8 emi apbh decode 9 apbx dma apbh decode a-e default apbh slave decode a-e unused apbh decode f simulation termination and printf registers. default apbh slave on real chip. free datasheet http:/// STMP36XX official product documentation 5/3/06 808 chapter 34: memory map 5-36xx-d1-1.02-050306 100 xxxxxxxxx 01 apbx 0 clkctrl xxxx register selects set clear toggle byte apbx 1 power apbx 2 audioout apbx 3 audioin apbx 4 lradc apbx 5 spdif apbx 6 i2c apbx 7 rtc apbx 8 lcd if apbx 9 pwm apbx a timrot apbx b uarta apbx c uartb apbx d dri apbx e irda apbx f usb phy 10 xxxxxxxxxx otg usb registers 11 xxxx default first-le vel page table16kb 101 ahb default slave 11 xxxxxxxxxxxxx 64k?on-chip? rom or interrupt vector register table 1006. STMP36XX memory map (continued) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 809 35. pin descriptions this chapter provides various view s of the pinout for the STMP36XX. section 35.1.1 details the 100-pin tqfp package pinout. section 35.1.2 details the bga pinout. functional subsets of the pinout are listed in section 35.2 . table 1007 lists the abbreviations used in the pin tables in this chapter. 35.1. pin placement and definitions note:almost all digital pins are powered down (i.e., high-i mpedance) at reset, until reprogrammed. the only exceptions are: testmode, once_dsi, once_dsk, once_dso , once_drn; these pins are always active. table 1007. nomenclature for pin tables type description module description a analog pin codec analog pins i input pin dcdc dc-dc converter pins i/o input/output pin emi-sd external memory interface pins (sdram) o output pin emi-nor external memory interface pins (nor) p power pin etm embedded trace macrocell gpio general-purpose input/output pins gpmi general-purpose media interface (nand/ata/cmos) hp head phones i 2 ci 2 c pins lcdif lcd interface power power pins pwm pulse width modulator ssp synchronous serial port pins system system pins timer timer pins uart either debug or application uarts usb usb pins note: for additional package measurements, see chapter 36 , ?package drawings? on page 843 . figure 150. chip package photographs 100 tqfp 169 fpbga 14 x 14 mm 11 x 11 mm pin 1 pin a1 pin a1 free datasheet http:/// STMP36XX official product documentation 5/3/06 810 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 35.1.1. pin definitions for 100-pin tqfp package table 1008. pin definition s?100-pin tqfp package pin number pin name module type pin mux description 1 gpmi_rdy2 gpmi i/o 0 ata dmack or nand2 ready/busy# pinctrl i/o 3 gpio0[20] 2 gpmi_d00 gpmi i/o 0 ata/nand data 0 pinctrl i/o 3 gpio0[0] 3 gpmi_d01 gpmi i/o 0 ata/nand data 1 pinctrl i/o 3 gpio0[1] 4 vddio1 power p 0 digital i/o power 1 / lradc7?2 5 vssd1 power p 0 digital ground 1 6 gpmi_d02 gpmi i/o 0 ata/nand data 2 pinctrl i/o 3 gpio0[2] 7 gpmi_d03 gpmi i/o 0 ata/nand data 3 pinctrl i/o 3 gpio0[3] 8 gpmi_d04 gpmi i/o 0 ata/nand data 4 pinctrl i/o 3 gpio0[4] 9 gpmi_d05 gpmi i/o 0 ata/nand data 5 pinctrl i/o 3 gpio0[5] 10 gpmi_d06 gpmi i/o 0 ata/nand data 6 pinctrl i/o 3 gpio0[6] 11 gpmi_d07 gpmi i/o 0 ata/nand data 7 pinctrl i/o 3 gpio0[7] 12 vddd1 power p digital core power 1 / lradc7?1 13 vssd2 power p digital ground 2 14 gpmi_irq gpmi i 0 ata intrq or nand1 ready/busy# pinctrl i/o 3 gpio0[16] 15 gpmi_rdy gpmi i 0 ata iordy:dstrobe or nand0 ready/busy# pinctrl i/o 3 gpio0[18] 16 gpmi_a0 gpmi o 0 ata_a0 or nand cle emi o 1 emi_a23 pinctrl i/o 3 gpio0[22] 17 gpmi_a1 gpmi o 0 ata_a1 or nand ale emi o 1 emi_a24 pinctrl i/o 3 gpio0[23] 18 gpmi_rdn gpmi o 0 ata dior-:hstrobe or nand read strobe pinctrl i/o 3 gpio0[17] 19 vddio2 power p digital i/o power 2 20 vssd3 power p digital ground 3 21 gpmi_wrn gpmi o 0 ata diow-:stop or nand write strobe pinctrl i/o 3 gpio0[21] free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 811 22 emi_ce0n emi o 0 emi ce0n gpmi o 1 gpmi_ce0n pinctrl i/o 3 gpio3[0] 23 emi_ce1n emi o 0 emi ce1n gpmi o 1 gpmi_ce1n pinctrl i/o 3 gpio3[1] 24 rotarya timer i/o 0 rotary encoder a pinctrl i/o 3 gpio3[15] 25 rotaryb timer i/o 0 rotary encoder b pinctrl i/o 3 gpio3[16] 26 i2c_scl i2c i/o 0 i 2 c serial clock (o.d.) pinctrl i/o 3 gpio3[17] 27 i2c_sda i2c i/o 0 i 2 c serial data (o.d.) pinctrl i/o 3 gpio3[18] 28 pwm0 pwm i/o 0 pwm etm o 1 etm_tsynca uartdbg i 2 uart1 rx (debug) pinctrl i/o 3 gpio3[10] 29 gpmi_resetn gpmi o 0 ata reset or nand write protect or renesas reset etm o 1 emi reset pinctrl i/o 3 gpio1[20] 30 lcd_busy lcdif i 0 lcd busy pinctrl i/o 3 gpio1[21] 31 lcd_cs lcdif o 0 lcd interface chip select etm o 1 etm_tclk pinctrl i/o 3 gpio1[19] 32 lcd_d00 lcdif o 0 lcd interface data 0 etm o 1 etm_da0 pinctrl i/o 3 gpio1[0] 33 lcd_d01 lcdif o 0 lcd interface data 1 etm o 1 etm_da1 pinctrl i/o 3 gpio1[1] 34 lcd_d02 lcdif o 0 lcd interface data 2 etm o 1 etm_da2 pinctrl i/o 3 gpio1[2] 35 lcd_d03 lcdif o 0 lcd interface data 3 etm o 1 etm_da3 pinctrl i/o 3 gpio1[3] 36 vssd4 power p digital ground 4 37 vddd2 power p digital core power 2 38 lcd_d04 lcdif o lcd interface data 4 table 1008. pin definitions?100- pin tqfp package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 812 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 39 lcd_d05 lcdif o lcd interface data 5 etm o 1 etm_da5 pinctrl i/o 3 gpio1[5] 40 vssd5 power p digital ground 5 41 vddio3 power p digital i/o power 3 42 lcd_d06 lcdif o 0 lcd interface data 6 etm o 1 etm_da6 pinctrl i/o 3 gpio1[6] 43 lcd_d07 lcdif o 0 lcd interface data 7 etm o 1 etm_da7 pinctrl i/o 3 gpio1[7] 44 lcd_rs lcdif o 0 lcd interface register select etm o 1 etm_psa0 pinctrl i/o 3 gpio1[17] 45 lcd_reset lcdif o 0 lcd interface reset out etm o 1 etm_psa1 pinctrl i/o 3 gpio1[16] 46 lcd_wr lcdif o 0 lcd interface data write etm o 1 etm_psa2 pinctrl i/o 3 gpio1[18] 47 dcdc1_vddio dcdc p dcdc#1 vddio output mode 3, 1 battery connection mode 2, 0 48 dcdc1_vddd dcdc p dcdc#1 vddd output mode 3, 1 49 dcdc1_batt dcdc p dcdc#1 inductor 50 dcdc1_gnd dcdc p dcdc#1 ground 51 jtag_reset system i debug reset 52 dcdc_mode dcdc a dcdc mode select 53 dcdc2_gnd dcdc p dcdc#2 ground 54 dcdc2_l1 dcdc p dcdc#2 inductor mode 2, 1, 0 peripheral vddio mode 3 55 dcdc2_pfet dcdc p dcdc#2 battery connection mode 0, 1 vddio connection mode 2, 3 56 vdd5v power p 5-v power input 57 batt power p battery input / lradc7?0 58 lradc1 lradc a lradc1 (button 2, temp, or micbias) 59 lradc0 lradc a lradc0 (button 1 or temp) 60 hp_sense hp a direct coupled headphone sense 61 hpr hp a headphone right 62 vdda1 power analog power1 63 hp_vgnd hp a direct coupled headphone virtual ground 64 vssa1 power p analog ground 1 65 hpl hp a headphone left table 1008. pin definitions?100- pin tqfp package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 813 66 line1r adc a line-in 1 right dri_clk dri i n/a used for digital radio clock input if enabled by hw_dri_ctrl_ enable_inputs 67 line1l adc a line-in 1 left dri_data dri i n/a used for digital radio data input if enabled by hw_dri_ctrl_ enable_inputs 68 mic adc a microphone input 69 vag hp a analog decoupling capacitor 70 refp adc a adc positive reference capacitor 71 vssa3 power p analog ground 3 - db 72 ref_res usb a usb reference resistor 73 pswitch dcdc p power-on/recovery/software-visible 74 xtalo clock a crystal out?24 mhz 75 xtali clock a crystal in?24 mhz 76 vddxtal clock a crystal power filter cap 77 testmode system i test mode pin 78 usb_otg_id usb a usb otg id sense 79 jtag_tms system i debug test mode select 80 jtag_tdi system i debug data in 81 jtag_tck system i debug clock 82 usb_dp usb a usb positive data line 83 usb_dm usb a usb negative data line 84 jtag_tdo system o debug data out 85 vddio4 power p digital i/o power 4 86 vssd6 power p digital ground 6 87 pwm4 pwm i/o 0 pwm - 16ma drive for otg vbus etm o 1 etm_psb1 pinctrl i/o 3 gpio3[14] 88 pwm2 pwm i/o 0 pwm etm o 1 etm_psb2 jtag 2 rtck - jtag return clock pinctrl i/o 3 gpio3[12] 89 pwm3 pwm i/o 0 pwm - 16ma drive for spdif out etm o 1 etm_psb0 spdif o 2 spdif out pinctrl i/o 3 gpio3[13] 90 pwm1 pwm i/o 0 pwm etm o 1 etm_tsyncb uartdbg o 2 uart1 tx (debug) pinctrl i/o 3 gpio3[11] 91 vddd3 power p digital core power 3 92 vssd7 power p digital ground 7 table 1008. pin definitions?100- pin tqfp package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 814 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 35.1.2. pin definitions for 169-pin bga package 93 emi_clk emi o 0 emi clock pinctrl i/o 3 gpio3[4] 94 ssp_detect ssp i/o 0 removable card detect jtag 2 rtck - jtag return clock pinctrl i/o 3 gpio0[25] 95 ssp_data0 ssp i/o 0 spi miso or sd/mmc dat0 pinctrl i/o 3 gpio0[28] 96 ssp_cmd ssp i/o 0 spi mosi or ms sdio or sd/mmc cmd pinctrl i/o 3 gpio0[26] 97 ssp_data2 ssp i/o 0 sd/mmc data 2 pinctrl i/o 3 gpio0[30] 98 ssp_data3 ssp i/o 0 spi slave select 0 or ms bs or sd/mmc dat3 pinctrl i/o 3 gpio0[31] 99 ssp_data1 ssp i/o 0 sd/mmc data 1 100 ssp_sck ssp i/o 0 spi serial clock pinctrl i/o 3 gpio0[27] table 1009. pin definitions?169-pin bga package pin number pin name module type pin mux description a1 testmode system i test mode pin a2 xtali clock a crystal in - 24 mhz a3 xtalo clock a crystal out - 24 mhz a4 rtc_xtali rtc a 32.768 khz xtal in a5 rtc_xtalo rtc a 32.768 khz xtal out a6 line1l adc a line-in 1 left dri_data dri i n/a used for digital radio data input if enabled by hw_dri_ctrl_enable_inputs a7 hp_vgnd hp a direct coupled headphone virtual ground a8 lradc0 lradc a lradc0 (button 1, temp, or micbias) a9 batt power p battery input / lradc7?0 a10 dcdc2_pfet dcdc p dcdc#2 battery connection mode 0, 1 vddio connection mode 2, 3 a11 dcdc2_l1 dcdc p dcdc#2 inductor mode 2, 1, 0 peripheral vddio mode 3 a12 dcdc2_gnd dcdc p dcdc#2 ground a13 dcdc1_batt dcdc p dcdc#1 inductor b1 jtag_tms system i debug test mode select table 1008. pin definitions?100- pin tqfp package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 815 b2 refp adc a adc positive reference capacitor b3 vddxtal clock a crystal power filter cap - cross bond to side 4 b4 ref_res usb a usb reference resistor b5 line1r adc a line-in 1 right dri_clk dri i n/a used for digital radio clock input if enabled by hw_dri_ctrl_enable_inputs b6 mic adc a microphone input b7 hpr hp a headphone right b8 hp_sense hp a direct coupled headphone sense b9 lradc2 lradc a lradc2 (touchscreen 0 or line2 left) b10 dcdc2_l2 dcdc p dcdc#2 inductor mode 0 peripheral vddio mode 2 b11 dcdc2_vddio dcdc p dcdc#2 vddio output mode 0 vddio connection mode 2 b12 dcdc1_gnd dcdc p dcdc#1 ground b13 dcdc1_vddd dcdc p dcdc#1 vddd output mode 3, 1 c1 usb_dm usb a usb negative data line c2 usb_dp usb a usb positive data line c3 jtag_tdi system i debug data in c4 pswitch dcdc p power-on / recovery / software-visible c5 vag hp a analog decoupling capacitor c6 hpl hp a headphone left c7 lradc1 lradc a lradc1 (button 2, temp, or micbias) c8 lradc5 lradc a lradc5 (touchscreen 3) c9 jtag_reset system i debug reset c10 dcdc_mode dcdc a dcdc mode select c11 lcd_wr lcdif o 0 lcd interface data write etm o 1 etm_psa2 pinctrl i/o 3 gpio1[18] c12 lcd_rs lcdif o 0 lcd interface register select etm o 1 etm_psa0 pinctrl i/o 3 gpio1[17] c13 dcdc1_vddio dcdc p 0 usb#1 vddio output mode 3, 1 battery connection mode 2, 0 d1 emi_d03 emi i/o 0 emi data 3 pinctrl i/o 3 gpio2[3] d2 jtag_tck system i 0 debug clock d3 emi_d00 emi i/o 0 emi data 0 pinctrl i/o 3 gpio2[0] d4 jtag_tdo system o debug data out d5 vssa3 power p analog ground 3 - db d6 vdda1 power p analog power1 d7 speakerm speaker a speaker output d8 vssa1 power p 0 analog ground 1 table 1009. pin definitions?169-pin bga package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 816 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 d9 vdd5v power p 5-v power input d10 lradc4 lradc a lradc4 (touchscreen 2) d11 lcd_reset lcdif o 0 lcd interface reset out etm o 1 etm_psa1 pinctrl i/o 3 gpio1[16] d12 lcd_d07 lcdif o 0 lcd interface data 7 etm o 1 etm_da7 pinctrl i/o 3 gpio1[7] d13 lcd_d06 lcdif o 0 lcd interface data 6 etm o 1 etm_da6 pinctrl i/o 3 gpio1[6] e1 pwm2 pwm i/o 0 pwm etm o 1 etm_psb2 system o 2 rtck - jtag return clock pinctrl i/o 3 gpio3[12] e2 emi_d02 emi i/o 0 emi data 2 pinctrl i/o 3 gpio2[2] e3 emi_d01 emi i/o 0 emi data 1 pinctrl i/o 3 gpio2[1] e4 vssd6 power p 0 digital ground 6 e5 vddio4 power p 0 digital i/o power 4 e6 emi_d05 emi i/o 0 emi data 5 pinctrl i/o 3 gpio2[5] e7 speakerp speaker a 0 speaker output + e8 usb_otg_id usb a 0 usb otg id sense e9 lradc3 lradc a 0 lradc3 (touchscreen 1 or line2 right) e10 lcd_d08 lcdif o 0 lcd interface data 8 etm o 1 etm_db0 pinctrl i/o 3 gpio1[8] e11 lcd_d09 lcdif o 0 lcd interface data 9 etm o 1 etm_db1 pinctrl i/o 3 gpio1[9] e12 lcd_d11 lcdif o 0 lcd interface data 11 etm o 1 etm_db3 pinctrl i/o 3 gpio1[11] e13 lcd_d10 lcdif o 0 lcd interface data 10 etm o 1 etm_db2 pinctrl i/o 3 gpio1[10] f1 pwm3 pwm i/o 0 pwm - 16ma drive for spdif out etm o 1 etm_psb0 spdif o 2 spdif out pinctrl i/o 3 gpio3[13] table 1009. pin definitions?169-pin bga package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 817 f2 emi_d04 emi i/o 0 emi data 4 pinctrl i/o 3 gpio2[4] f3 pwm4 pwm i/o 0 pwm - 16ma drive for otg vbus etm o 1 etm_psb1 pinctrl i/o 3 gpio3[14] f4 emi_d07 emi i/o 0 emi data 7 pinctrl i/o 3 gpio2[7] f5 emi_d09 emi i/o 0 emi data 9 pinctrl i/o 3 gpio2[9] f6 emi_d06 emi i/o 0 emi data 6 pinctrl i/o 3 gpio2[6] f7 lcd_d14 lcdif o 0 lcd interface data 14 etm o 1 etm_db6 pinctrl i/o 3 gpio1[14] f8 lcd_d13 lcdif o 0 lcd interface data 13 etm o 1 etm_db5 pinctrl i/o 3 gpio1[13] f9 lcd_d12 lcdif o 0 lcd interface data 12 etm o 1 etm_db4 pinctrl i/o 3 gpio1[12] f10 vddd2 power p digital core power 2 f11 lcd_d02 lcdif o 0 lcd interface data 2 etm o 1 etm_da2 pinctrl i/o 3 gpio1[2] f12 lcd_d05 lcdif o 0 lcd interface data 5 etm o 1 etm_da5 pinctrl i/o 3 gpio1[5] f13 lcd_d04 lcdif o 0 lcd interface data 4 etm o 1 etm_da4 pinctrl i/o 3 gpio1[4] g1 emi_clk emi o 0 emi clock pinctrl i/o 3 gpio3[4] g2 emi_d11 emi i/o 0 emi data 11 pinctrl i/o 3 gpio2[11] g3 emi_d08 emi i/o 0 emi data 8 pinctrl i/o 3 gpio2[8] g4 vddd3 power p 0 digital core power 3 g5 emi_d10 emi i/o 0 emi data 10 pinctrl i/o 3 gpio2[10] g6 vssd7 power p digital ground 7 table 1009. pin definitions?169-pin bga package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 818 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 g7 pwm1 pwm i/o 0 pwm etm o 1 etm_tsyncb uartdbg o 2 uart1 tx (debug) pinctrl i/o 3 gpio3[11] g8 gpmi_d09 gpmi i/o 0 ata/nand data 9 etm o 1 emi_a16 pinctrl i/o 3 gpio0[9] g9 vssd4 power p digital ground 4 g10 lcd_busy lcdif i 0 lcd busy pinctrl i/o 3 gpio1[21] g11 lcd_d15 lcdif o 0 lcd interface data 15 etm o 1 etm_db7 system o 2 rtck - jtag return clock pinctrl i/o 3 gpio1[15] g12 lcd_d03 lcdif o 0 lcd interface data 3 etm o 1 etm_da3 pinctrl i/o 3 gpio1[3] g13 lcd_d01 lcdif o 0 lcd interface data 1 etm o 1 etm_da1 pinctrl i/o 3 gpio1[1] h1 emi_d14 emi i/o 0 emi data 14 pinctrl i/o 3 gpio2[14] h2 ssp_detect ssp i/o 0 removable card detect system o 2 rtck - jtag return clock pinctrl i/o 3 gpio0[25] h3 emi_d13 emi i/o 0 emi data 13 pinctrl i/o 3 gpio2[13] h4 emi_d15 emi i/o 0 emi data 15 pinctrl i/o 3 gpio2[15] h5 emi_d12 emi i/o 0 emi data 12 pinctrl i/o 3 gpio2[12] h6 vssd1 power p digital ground 1 h7 gpmi_d02 gpmi i/o 0 ata/nand data 2 pinctrl i/o 3 gpio0[2] h8 gpmi_d07 gpmi i/o 0 ata/nand data 7 pinctrl i/o 3 gpio0[7] h9 vddio2 power p 0 digital i/o power 2 h10 uart2_cts uart i 0 high-speed uart cts flow control pinctrl i/o 3 gpio1[22] h11 lcd_cs lcdif o 0 lcd interface chip select. etm o 1 etm_tclk pinctrl i/o 3 gpio1[19] table 1009. pin definitions?169-pin bga package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 819 h12 uart2_tx uart i/o 0 high-speed uart tx ir o 2 ir_tx pinctrl i/o 3 gpio1[25] h13 lcd_d00 lcdif o 0 lcd interface data 0 etm o 1 etm_da0 pinctrl i/o 3 gpio1[0] j1 emi_a00 emi o 0 emi address 0 pinctrl i/o 3 gpio2[16] j2 emi_a01 emi o 0 emi address 1 pinctrl i/o 3 gpio2[17] j3 ssp_cmd ssp i/o 0 spi mosi or ms, sdio, or sd/mmc cmd pinctrl i/o 3 gpio0[26] j4 emi_a02 emi o 0 emi address 2 pinctrl i/o 3 gpio2[18] j5 ssp_data0 ssp i/o 0 spi miso or sd/mmc dat0 pinctrl i/o 3 gpio0[28] j6 gpmi_d01 gpmi i/o 0 ata/nand data 1 pinctrl i/o 3 gpio0[1] j7 vssd2 power p digital ground 2 j8 gpmi_a0 gpmi o 0 ata_a0 or nand cle emi o 1 emi_a23 pinctrl i/o 3 gpio0[22] j9 vssd3 power p digital ground 3 j10 emi_ce2n emi i/o 0 emi ce2n gpmi o 1 gpmi_ce2n pinctrl i/o 3 gpio3[2] j11 pwm0 pwm i/o 0 pwm etm o 1 etm_tsynca uartdbg i 2 uart1 rx (debug) pinctrl i/o 3 gpio3[10] j12 gpmi_resetn gpmi o 0 ata reset or nand write protect or renesas reset etm o 1 emi reset pinctrl i/o 3 gpio1[20] j13 uart2_rx uart i 0 high-speed uart rx ir i 2 ir_rx pinctrl i/o 3 gpio1[24] k1 emi_a03 emi o 0 emi address 3 pinctrl i/o 3 gpio2[19] k2 ssp_data3 ssp i/o 0 spi slave select 0 or ms bs or sd/mmc dat3 pinctrl i/o 3 gpio0[31] k3 emi_a04 emi o 0 emi address 4 pinctrl i/o 3 gpio2[20] table 1009. pin definitions?169-pin bga package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 820 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 k4 ssp_data2 ssp i/o 0 sd/mmc data 2 pinctrl i/o 3 gpio0[30] k5 vddio1 power p 0 digital i/o power 1 / lradc7?2 k6 gpmi_d12 gpmi i/o 0 ata/nand data 12 emi o 1 emi_a19 gpmi o 2 gpmi_ce0n pinctrl i/o 3 gpio0[12] k7 vddd1 power p 0 digital core power 1 / lradc7?1 k8 emi_a13 emi o 0 emi address 13 / sdram ba0 pinctrl i/o 3 gpio2[29] k9 gpmi_a1 gpmi o 0 ata_a1 or nand ale emi o 1 emi_a24 pinctrl i/o 3 gpio0[23] k10 emi_a10 emi o 0 emi address 10 pinctrl i/o 3 gpio2[26] k11 i2c_scl i2c i/o 0 i 2 c serial clock (o.d.) pinctrl i/o 3 gpio3[17] k12 i2c_sda i2c i/o 0 i 2 c serial data (o.d.) pinctrl i/o 3 gpio3[18] k13 uart2_rts uart o 0 high-speed uart rts flow control system o 1 rtck - jtag return clock ir o 2 ir_clk pinctrl i/o 3 gpio1[23] l1 emi_a05 emi o 0 emi address 5 pinctrl i/o 3 gpio2[21] l2 emi_a06 emi o 0 emi address 6 pinctrl i/o 3 gpio2[22] l3 emi_a08 emi o 0 emi address 8 pinctrl i/o 3 gpio2[24] l4 emi_a09 emi o 0 emi address 9 pinctrl i/o 3 gpio2[25] l5 gpmi_d14 gpmi i/o 0 ata/nand data 14 emi o 1 emi_a21 gpmi o 2 gpmi_ce2n pinctrl i/o 3 gpio0[14] l6 gpmi_d11 gpmi i/o 0 ata/nand data 11 emi o 1 emi_a18 pinctrl i/o 3 gpio0[11] l7 emi_a14 emi o 0 emi address 14 / sdram ba1 pinctrl i/o 3 gpio2[30] l8 gpmi_rdy gpmi i 0 ata iordy:dstrobe or nand0 ready/busy# pinctrl i/o 3 gpio0[18] table 1009. pin definitions?169-pin bga package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 821 l9 gpmi_a2 gpmi o 0 ata_a2 emi o 1 emi_a25 pinctrl i/o 3 gpio0[24] l10 emi_rasn emi o 0 emi rasn pinctrl i/o 3 gpio2[31] l11 emi_ce1n emi o 0 emi ce1n gpmi o 1 gpmi_ce1n pinctrl i/o 3 gpio3[1] l12 rotaryb timer i/o 0 rotary encoder b pinctrl i/o 3 gpio3[16] l13 gpmi_rdy3 gpmi i/o 0 ata dmarq or nand3 r/b# emi o 1 emi_oen pinctrl i/o 3 gpio0[19] m1 ssp_data1 ssp i/o 0 sd/mmc data 1 pinctrl i/o 3 gpio0[29] m2 emi_a07 emi o 0 emi address 7 pinctrl i/o 3 gpio2[23] m3 emi_wen emi o 0 emi wen pinctrl i/o 3 gpio3[9] m4 gpmi_d15 gpmi i/o 0 ata/nand data 15 emi o 1 emi_a22 gpmi o 2 gpmi_ce3n pinctrl i/o 3 gpio0[15] m5 gpmi_d13 gpmi i/o 0 ata/nand data 13 emi o 1 emi_a20 gpmi o 2 gpmi_ce1n pinctrl i/o 3 gpio0[13] m6 gpmi_d04 gpmi i/o 0 ata/nand data 4 pinctrl i/o 3 gpio0[4] m7 gpmi_d06 gpmi i/o 0 ata/nand data 6 pinctrl i/o 3 gpio0[6] m8 gpmi_irq gpmi i 0 ata intrq or nand1 ready/busy# pinctrl i/o 3 gpio0[16] m9 emi_a11 emi o 0 emi address 11 pinctrl i/o 3 gpio2[27] m10 gpmi_wrn gpmi o 0 ata diow-:stop or nand write strobe pinctrl i/o 3 gpio0[21] m11 emi_ce0n emi o 0 emi ce0n gpmi o 1 gpmi_ce0n pinctrl i/o 3 gpio3[0] m12 emi_dqm0 emi o 0 emi dqm0 pinctrl i/o 3 gpio3[7] table 1009. pin definitions?169-pin bga package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 822 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 m13 emi_dqm1 emi o 0 emi dqm1 pinctrl i/o 3 gpio3[8] n1 emi_cke emi o 0 emi clock enable pinctrl i/o 3 gpio3[5] n2 ssp_sck ssp i/o 0 spi serial clock - (bond to pin 100 in 100 tqfp) pinctrl i/o 3 gpio0[27] n3 gpmi_rdy2 gpmi i/o 0 ata dmack or nand2 ready/busy# pinctrl i/o 3 gpio0[20] n4 gpmi_d00 gpmi i/o 0 ata/nand data 0 pinctrl i/o 3 gpio0[0] n5 gpmi_d03 gpmi i/o 0 ata/nand data 3 pinctrl i/o 3 gpio0[3] n6 gpmi_d05 gpmi i/o 0 ata/nand data 5 pinctrl i/o 3 gpio0[5] n7 gpmi_d10 gpmi i/o 0 ata/nand data 10 emi o 1 emi_a17 pinctrl i/o 3 gpio0[10] n8 gpmi_d08 gpmi i/o 0 ata/nand data 8 emi o 1 emi_a15 pinctrl i/o 3 gpio0[8] n9 emi_a12 emi o 0 emi address 12 pinctrl i/o 3 gpio2[28] n10 gpmi_rdn gpmi o 0 ata dior-:hstrobe or nand read strobe pinctrl i/o 3 gpio0[17] n11 emi_ce3n emi i/o 0 emi ce3n gpmi o 1 gpmi_ce3n pinctrl i/o 3 gpio3[3] n12 emi_casn emi o 0 emi casn pinctrl i/o 3 gpio3[6] n13 rotarya timer i/o 0 rotary encoder a pinctrl i/o 3 gpio3[15] table 1009. pin definitions?169-pin bga package (continued) pin number pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 823 35.2. functional pin groups this section includes all pins , listed in tables by function. to find the pin number for a given pin name, consult either table 1008 for the tqfp pins or table 1009 for the bga pins. 35.2.1. analog pins table 1010. bga package pin map 1 2 34 5 67 8 91011 1213 a testmode xtali xtalo rtc_xtali rtc_xtalo line1l hp_vgnd lradc0 batt dcdc2_pfet dcdc2_l1 dcdc2_gnd dcdc1_batt b jtag_tms refp vddxtal ref_res line1r mic hpr hp_sense lradc2 dcdc2_l2 dcdc2_vddio dcdc1_gnd dcdc1_vddd c usb_dm usb_dp jtag_tdi pswitch vag hpl lradc1 lradc5 jtag_reset dcdc_mode lcd_wr lcd_rs dcdc1_vddio d emi_d03 jtag_tck emi_d00 jtag_tdo vssa3 vdda1 speakerm vssa1 vdd5v lradc4 lcd_reset lcd_d07 lcd_d06 e pwm2 emi_d02 emi_d01 vssd6 vddio4 emi_d05 speakerp usb_otg_id lradc3 lcd_d08 lcd_d09 lcd_d11 lcd_d10 f pwm3 emi_d04 pwm4 emi_d07 emi_d09 emi_d06 lcd_d14 lcd_d13 lcd_d12 vddd2 lcd_d02 lcd_d05 lcd_d04 g emi_clk emi_d11 emi_d08 vddd3 emi_d10 vssd7 pwm1 gpmi_d09 vssd4 lcd_busy lcd_d15 lcd_d03 lcd_d01 h emi_d14 ssp_detect emi_d13 emi_d15 emi_d12 vssd1 gpmi_d02 gpmi_d07 vddio2 uart2_cts lcd_cs uart2_tx lcd_d00 j emi_a00 emi_a01 ssp_cmd emi_a02 ssp_data0 gpmi_d01 vssd2 gpmi_a0 vssd3 emi_ce2n pwm0 gpmi_resetn uart2_rx k emi_a03 ssp_data3 emi_a04 ssp_data2 vddio1 gpmi_d12 vddd1 emi_a13 gpmi_a1 emi_a10 i2c_scl i2c_sda uart2_rts l emi_a05 emi_a06 emi_a08 emi_a09 gpmi_d14 gpmi_d11 emi_a14 gpmi_rdy gpmi_a2 emi_rasn emi_ce1n rotaryb gpmi_rdy3 m ssp_data1 emi_a07 emi_wen gpmi_d15 gpmi_d13 gpmi_d04 gpmi_d06 gpmi_irq emi_a11 gpmi_wrn emi_ce0n emi_dqm0 emi_dqm1 n emi_cke ssp_sck gpmi_rdy2 gpmi_d00 gpmi_d03 gpmi_d05 gpmi_d10 gpmi_d08 emi_a12 gpmi_rdn emi_ce3n emi_casn rotarya table 1011. analog pins pin name module type pin mux description hp_sense hp a direct coupled headphone sense hp_vgnd hp a direct coupled headphone virtual ground hpl hp a headphone left hpr hp a headphone right line1l adc a line-in 1 left line1r adc a line-in 1 right lradc0 lradc a lradc0 (button 1, temp, or micbias) free datasheet http:/// STMP36XX official product documentation 5/3/06 824 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 35.2.2. dc-dc converter pins lradc1 lradc a lradc1 (button 2, temp, or micbias) lradc2 lradc a lradc2 (touchscreen 0 or line2 left) lradc3 lradc a lradc3 (touchscreen 1 line2 right) lradc4 lradc a lradc4 (touchscreen 2) lradc5 lradc a lradc5 (touchscreen 3) mic adc a microphone input ref_res usb a usb reference resistor refp adc a adc positive reference capacitor speakerm speaker a speaker output ? speakerp speaker a speaker output + vag hp a analog decoupling capacitor table 1012. dc-dc converter pins pin name module type pin mux description batt power p battery input dcdc_mode dcdc a dc-dc mode select dcdc1_batt dcdc p dc-dc#1 inductor dcdc1_gnd dcdc p dc-dc#1 ground dcdc1_vddd dcdc p dc-dc#1 vddd output mode 3, 1 dcdc1_vddio dcdc p dc-dc#1 vddio output mode 3, 1 battery connection mode 2, 0 dcdc2_gnd dcdc p dc-dc#22 ground dcdc2_l1 dcdc p dc-dc#2 inductor mode 2, 1, 0 peripheral vddio mode 3 dcdc2_l2 dcdc p dc-dc#2 inductor mode 0 peripheral vddio mode 2 dcdc2_pfet dcdc p dc-dc#2 battery connection mode 0, 1 vddio connection mode 2, 3 dcdc2_vddio dcdc p dc-dc#2 vddio output mode 0 vddio connection mode 2 pswitch dcdc p power-on/recovery/software-visible table 1011. analog pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 825 35.2.3. general-purpose media interface (gpmi) pins table 1013. gpmi pins pin name module type pin mux description gpmi_a0 gpmi o 0 ata_a0 or nand cle emi o 1 emi_a23 pinctrl i/o 3 gpio0[22] gpmi_a1 gpmi o 0 ata_a1 or nand ale emi o 1 emi_a24 pinctrl i/o 3 gpio0[23] gpmi_a2 gpmi o 0 ata_a2 emi o 1 emi_a25 pinctrl i/o 3 gpio0[24] emi_ce0n emi o 0 emi ce0n gpmi o 1 gpmi_ce0n pinctrl i/o 3 gpio3[0] emi_ce1n emi o 0 emi ce1n gpmi o 1 gpmi_ce1n pinctrl i/o 3 gpio3[1] emi_ce2n emi i/o 0 emi ce2n gpmi o 1 gpmi_ce2n pinctrl i/o 3 gpio3[2] emi_ce3n emi i/o 0 emi ce3n gpmi o 1 gpmi_ce3n pinctrl i/o 3 gpio3[3] gpmi_d00 gpmi i/o 0 ata/nand data 0 pinctrl i/o 3 gpio0[0] gpmi_d01 gpmi i/o 0 ata/nand data 1 pinctrl i/o 3 gpio0[1] gpmi_d02 gpmi i/o 0 ata/nand data 2 pinctrl i/o 3 gpio0[2] gpmi_d03 gpmi i/o 0 ata/nand data 3 pinctrl i/o 3 gpio0[3] gpmi_d04 gpmi i/o 0 ata/nand data 4 pinctrl i/o 3 gpio0[4] gpmi_d05 gpmi i/o 0 ata/nand data 5 pinctrl i/o 3 gpio0[5] gpmi_d06 gpmi i/o 0 ata/nand data 6 pinctrl i/o 3 gpio0[6] gpmi_d07 gpmi i/o 0 ata/nand data 7 pinctrl i/o 3 gpio0[7] gpmi_d08 gpmi i/o 0 ata/nand data 8 emi o 1 emi_a15 pinctrl i/o 3 gpio0[8] free datasheet http:/// STMP36XX official product documentation 5/3/06 826 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 gpmi_d09 gpmi i/o 0 ata/nand data 9 etm o 1 emi_a16 pinctrl i/o 3 gpio0[9] gpmi_d10 gpmi i/o 0 ata/nand data 10 emi o 1 emi_a17 pinctrl i/o 3 gpio0[10] gpmi_d11 gpmi i/o 0 ata/nand data 11 emi o 1 emi_a18 pinctrl i/o 3 gpio0[11] gpmi_d12 gpmi i/o 0 ata/nand data 12 emi o 1 emi_a19 gpmi o 2 gpmi_ce0n pinctrl i/o 3 gpio0[12] gpmi_d13 gpmi i/o 0 ata/nand data 13 emi o 1 emi_a20 gpmi o 2 gpmi_ce1n pinctrl i/o 3 gpio0[13] gpmi_d14 gpmi i/o 0 ata/nand data 14 emi o 1 emi_a21 gpmi o 2 gpmi_ce2n pinctrl i/o 3 gpio0[14] gpmi_d15 gpmi i/o 0 ata/nand data 15 emi o 1 emi_a22 gpmi o 2 gpmi_ce3n pinctrl i/o 3 gpio0[15] gpmi_irq gpmi i 0 ata intrq or nand1 ready/busy# pinctrl i/o 3 gpio0[16] gpmi_rdn gpmi o 0 ata dior-:hstrobe or nand read strobe pinctrl i/o 3 gpio0[17] gpmi_rdy gpmi i 0 ata iordy:dstrobe or nand0 ready/busy# pinctrl i/o 3 gpio0[18] gpmi_rdy2 gpmi i/o 0 ata dmack or nand2 ready/busy# pinctrl i/o 3 gpio0[20] gpmi_rdy3 gpmi i/o 0 ata dmarq or nand3 r/b# emi o 1 emi_oen pinctrl i/o 3 gpio0[19] gpmi_resetn gpmi o 0 ata reset, nand write protect, or renesas reset etm o 1 emi_reset pinctrl i/o 3 gpio1[20] gpmi_wrn gpmi o 0 ata diow-:stop or nand write strobe pinctrl i/o 3 gpio0[21] table 1013. gpmi pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 827 35.2.4. synchronous serial port (ssp) pins 35.2.5. application and debug uart pins table 1014. synchronous serial port pins pin name module type pin mux description ssp_cmd ssp i/o 0 spi mosi or ms, sdio, or sd/mmc cmd pinctrl i/o 3 gpio0[26] ssp_data0 ssp i/o 0 spi miso or sd/mmc dat0 pinctrl i/o 3 gpio0[28] ssp_data1 ssp i/o 0 sd/mmc data 1 pinctrl i/o 3 gpio0[29] ssp_data2 ssp i/o 0 sd/mmc data 2 pinctrl i/o 3 gpio0[30] ssp_data3 ssp i/o 0 spi slave select 0 or ms bs or sd/mmc dat3 pinctrl i/o 3 gpio0[31] ssp_detect ssp i/o 0 removable card detect system o 2 rtck - jtag return clock pinctrl i/o 3 gpio0[25] ssp_sck ssp i/o 0 spi serial clock - (bond to pin 100 in 100 tqfp) pinctrl i/o 3 gpio0[27] table 1015. uart pins pin name module type pin mux description uart2_cts uart i 0 high-speed uart cts flow control pinctrl i/o 3 gpio1[22] uart2_rts uart o 0 high-speed uart rts flow control system o 1 rtck - jtag return clock ir o 2 ir_clk pinctrl i/o 3 gpio1[23] uart2_rx uart i 0 high-speed uart rx ir i 2 ir_rx pinctrl i/o 3 gpio1[24] uart2_tx uart i/o 0 high-speed uart tx ir o 2 ir_tx pinctrl i/o 3 gpio1[25] pwm0 pwm i/o 0 pwm etm o 1 etm_tsynca uartdbg i 2 uart1 rx (debug) pinctrl i/o 3 gpio3[10] free datasheet http:/// STMP36XX official product documentation 5/3/06 828 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 35.2.6. external memory interface (sdram/nor) pins pwm1 pwm i/o 0 pwm etm o 1 etm_tsyncb uartdbg o 2 uart1 tx (debug) pinctrl i/o 3 gpio3[11] table 1016. external memo ry interface (sdram/nor) pins pin name module type pin mux description emi_a00 emi o 0 emi address 0 pinctrl i/o 3 gpio2[16] emi_a01 emi o 0 emi address 1 pinctrl i/o 3 gpio2[17] emi_a02 emi o 0 emi address 2 pinctrl i/o 3 gpio2[18] emi_a03 emi o 0 emi address 3 pinctrl i/o 3 gpio2[19] emi_a04 emi o 0 emi address 4 pinctrl i/o 3 gpio2[20] emi_a05 emi o 0 emi address 5 pinctrl i/o 3 gpio2[21] emi_a06 emi o 0 emi address 6 pinctrl i/o 3 gpio2[22] emi_a07 emi o 0 emi address 7 pinctrl i/o 3 gpio2[23] emi_a08 emi o 0 emi address 8 pinctrl i/o 3 gpio2[24] emi_a09 emi o 0 emi address 9 pinctrl i/o 3 gpio2[25] emi_a10 emi o 0 emi address 10 pinctrl i/o 3 gpio2[26] emi_a11 emi o 0 emi address 11 pinctrl i/o 3 gpio2[27] emi_a12 emi o 0 emi address 12 pinctrl i/o 3 gpio2[28] emi_a13 emi o 0 emi address 13 / sdram ba0 pinctrl i/o 3 gpio2[29] emi_a14 emi o 0 emi address 14 / sdram ba1 pinctrl i/o 3 gpio2[30] gpmi_d08 gpmi i/o 0 ata/nand data 8 emi o 1 emi_a15 pinctrl i/o 3 gpio0[8] table 1015. uart pi ns (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 829 gpmi_d09 gpmi i/o 0 ata/nand data 9 etm o 1 emi_a16 pinctrl i/o 3 gpio0[9] gpmi_d10 gpmi i/o 0 ata/nand data 10 emi o 1 emi_a17 pinctrl i/o 3 gpio0[10] gpmi_d11 gpmi i/o 0 ata/nand data 11 emi o 1 emi_a18 pinctrl i/o 3 gpio0[11] gpmi_d12 gpmi i/o 0 ata/nand data 12 emi o 1 emi_a19 pinctrl i/o 3 gpio0[12] gpmi_d13 gpmi i/o 0 ata/nand data 13 emi o 1 emi_a20 pinctrl i/o 3 gpio0[13] gpmi_d14 gpmi i/o 0 ata/nand data 14 emi o 1 emi_a21 pinctrl i/o 3 gpio0[14] gpmi_d15 gpmi i/o 0 ata/nand data 15 emi o 1 emi_a22 pinctrl i/o 3 gpio0[15] gpmi_a0 gpmi o 0 ata_a0 or nand cle emi o 1 emi_a23 pinctrl i/o 3 gpio0[22] gpmi_a1 gpmi o 0 ata_a1 or nand ale emi o 1 emi_a24 pinctrl i/o 3 gpio0[23] gpmi_a2 gpmi o 0 ata_a2 emi o 1 emi_a25 pinctrl i/o 3 gpio0[24] emi_casn emi o 0 emi casn pinctrl i/o 3 gpio3[6] emi_ce0n emi o 0 emi ce0n gpmi o 1 gpmi_ce0n pinctrl i/o 3 gpio3[0] emi_ce1n emi o 0 emi ce1n gpmi o 1 gpmi_ce1n pinctrl i/o 3 gpio3[1] emi_ce2n emi i/o 0 emi ce2n gpmi o 1 gpmi_ce2n pinctrl i/o 3 gpio3[2] emi_ce3n emi i/o 0 emi ce3n gpmi o 1 gpmi_ce3n pinctrl i/o 3 gpio3[3] table 1016. external memory in terface (sdram/nor) pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 830 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 emi_cke emi o 0 emi clock enable pinctrl i/o 3 gpio3[5] emi_clk emi o 0 emi clock pinctrl i/o 3 gpio3[4] emi_d00 emi i/o 0 emi data 0 pinctrl i/o 3 gpio2[0] emi_d01 emi i/o 0 emi data 1 pinctrl i/o 3 gpio2[1] emi_d02 emi i/o 0 emi data 2 pinctrl i/o 3 gpio2[2] emi_d03 emi i/o 0 emi data 3 pinctrl i/o 3 gpio2[3] emi_d04 emi i/o 0 emi data 4 pinctrl i/o 3 gpio2[4] emi_d05 emi i/o 0 emi data 5 pinctrl i/o 3 gpio2[5] emi_d06 emi i/o 0 emi data 6 pinctrl i/o 3 gpio2[6] emi_d07 emi i/o 0 emi data 7 pinctrl i/o 3 gpio2[7] emi_d08 emi i/o 0 emi data 8 pinctrl i/o 3 gpio2[8] emi_d09 emi i/o 0 emi data 9 pinctrl i/o 3 gpio2[9] emi_d10 emi i/o 0 emi data 10 pinctrl i/o 3 gpio2[10] emi_d11 emi i/o 0 emi data 11 pinctrl i/o 3 gpio2[11] emi_d12 emi i/o 0 emi data 12 pinctrl i/o 3 gpio2[12] emi_d13 emi i/o 0 emi data 13 pinctrl i/o 3 gpio2[13] emi_d14 emi i/o 0 emi data 14 pinctrl i/o 3 gpio2[14] emi_d15 emi i/o 0 emi data 15 pinctrl i/o 3 gpio2[15] emi_dqm0 emi o 0 emi dqm0 pinctrl i/o 3 gpio3[7] emi_dqm1 emi o 0 emi dqm1 pinctrl i/o 3 gpio3[8] gpmi_rdy3 gpmi i/o 0 ata dmarq or nand3 r/b# emi o 1 emi_oen pinctrl i/o 3 gpio0[19] table 1016. external memory in terface (sdram/nor) pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 831 35.2.7. i 2 c interface pins 35.2.8. digital radio interface (dri) pins 35.2.9. lcd interface (lcdif) pins emi_rasn emi o 0 emi rasn pinctrl i/o 3 gpio2[31] emi_wen emi o 0 emi wen pinctrl i/o 3 gpio3[9] table 1017. i 2 c interface pins pin name module type pin mux description i2c_scl i2c i/o 0 i 2 c serial clock (o.d.) pinctrl i/o 3 gpio3[17] i2c_sda i2c i/o 0 i 2 c serial data (o.d.) pinctrl i/o 3 gpio3[18] table 1018. digita l radio interface pins pin name module type pin mux description dri_clk dri i n/a used for digital radio clock input if enabled by hw_dri_ctrl_en able_inputs. note: this is the same as the line1r pin. dri_data dri i n/a used for digital radio data input if enabled by hw_dri_ctrl_en able_inputs. note: this is the same as the line1l pin. table 1019. lcdif interface pins pin name module type pin mux description lcd_busy lcdif i 0 lcd busy pinctrl i/o 3 gpio1[21] lcd_cs lcdif o 0 lcd interface chip select etm o 1 etm_tclk pinctrl i/o 3 gpio1[19] lcd_d00 lcdif o 0 lcd interface data 0 etm o 1 etm_da0 pinctrl i/o 3 gpio1[0] lcd_d01 lcdif o 0 lcd interface data 1 etm o 1 etm_da1 pinctrl i/o 3 gpio1[1] table 1016. external memory in terface (sdram/nor) pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 832 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 lcd_d02 lcdif o 0 lcd interface data 2 etm o 1 etm_da2 pinctrl i/o 3 gpio1[2] lcd_d03 lcdif o 0 lcd interface data 3 etm o 1 etm_da3 pinctrl i/o 3 gpio1[3] lcd_d04 lcdif o 0 lcd interface data 4 etm o 1 etm_da4 pinctrl i/o 3 gpio1[4] lcd_d05 lcdif o 0 lcd interface data 5 etm o 1 etm_da5 pinctrl i/o 3 gpio1[5] lcd_d06 lcdif o 0 lcd interface data 6 etm o 1 etm_da6 pinctrl i/o 3 gpio1[6] lcd_d07 lcdif o 0 lcd interface data 7 etm o 1 etm_da7 pinctrl i/o 3 gpio1[7] lcd_d08 lcdif o 0 lcd interface data 8 etm o 1 etm_db0 pinctrl i/o 3 gpio1[8] lcd_d09 lcdif o 0 lcd interface data 9 etm o 1 etm_db1 pinctrl i/o 3 gpio1[9] lcd_d10 lcdif o 0 lcd interface data 10 etm o 1 etm_db2 pinctrl i/o 3 gpio1[10] lcd_d11 lcdif o 0 lcd interface data 11 etm o 1 etm_db3 pinctrl i/o 3 gpio1[11] lcd_d12 lcdif o 0 lcd interface data 12 etm o 1 etm_db4 pinctrl i/o 3 gpio1[12] lcd_d13 lcdif o 0 lcd interface data 13 etm o 1 etm_db5 pinctrl i/o 3 gpio1[13] lcd_d14 lcdif o 0 lcd interface data 14 etm o 1 etm_db6 pinctrl i/o 3 gpio1[14] lcd_d15 lcdif o 0 lcd interface data 15 etm o 1 etm_db7 system o 2 rtck - jtag return clock pinctrl i/o 3 gpio1[15] table 1019. lcdif interface pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 833 35.2.10. power pins 35.2.11. system pins lcd_reset lcdif o 0 lcd interface reset out etm o 1 etm_psa1 pinctrl i/o 3 gpio1[16] lcd_rs lcdif o 0 lcd interface register select etm o 1 etm_psa0 pinctrl i/o 3 gpio1[17] lcd_wr lcdif o 0 lcd interface data write etm o 1 etm_psa2 pinctrl i/o 3 gpio1[18] table 1020. power pins pin name module type pin mux description batt power p battery input / lradc7?0 dcdc2_pfet dcdc p dc-dc2 pfet drain connection vdd5v power p 5-v power input vdda1 power analog power 1 vddd1 power p digital core power 1 / lradc7?1 vddd2 power p digital core power 2 vddd3 power p digital core power 3 vddio1 power p digital i/o power 1 / lradc7?2 vddio2 power p digital i/o power 2 vddio4 power p digital i/o power 4 vssa1 power analog ground 1 vssa3 power p analog ground 3 - db vssd1 power p digital ground 1 vssd2 power p digital ground 2 vssd3 power p digital ground 3 vssd4 power p digital ground 4 vssd6 power p digital ground 6 vssd7 power p digital ground 7 table 1021. system pins pin name module type pin mux description jtag_reset system i debug reset jtag_tck system i debug clock jtag_tdi system i debug data in jtag_tdo system o debug data out table 1019. lcdif interface pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 834 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 35.2.12. timer and pwm pins jtag_tms system i debug test mode select lcd_d15 lcdif o 0 lcd interface data 15 etm o 1 etm_db7 system o 2 rtck - jtag return clock pinctrl i/o 3 gpio1[15] pwm2 pwm i/o 0 pwm etm o 1 etm_psb2 system o 2 rtck - jtag return clock pinctrl i/o 3 gpio3[12] ssp_detect ssp i/o 0 removable card detect system o 2 rtck - jtag return clock pinctrl i/o 3 gpio0[25] uart2_rts uart o 0 high-speed uart rts flow control system o 1 rtck - jtag return clock ir o 2 ir_clk pinctrl i/o 3 gpio1[23] ref_res usb a usb reference resistor rtc_xtali rtc a 32.768-khz xtal in rtc_xtalo rtc a 32.768-khz xtal out testmode system i test mode pin vddxtal clock a crystal power filter cap - cross bond to side 4 xtali clock a crystal in - 24 mhz xtalo clock a crystal out - 24 mhz table 1022. timer and pwm pins pin name module type pin mux description pwm0 pwm i/o 0 pwm etm o 1 etm_tsynca uartdbg i 2 uart1_rx (debug) pinctrl i/o 3 gpio3[10] pwm1 pwm i/o 0 pwm etm o 1 etm_tsyncb uartdbg o 2 uart1_tx (debug) pinctrl i/o 3 gpio3[11] pwm2 pwm i/o 0 pwm etm o 1 etm_psb2 system o 2 rtck - jtag return clock pinctrl i/o 3 gpio3[12] table 1021. system pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 835 35.2.13. usb pins 35.2.14. general-purpose input/output (gpio) pins pwm3 pwm i/o 0 pwm - 16ma drive for spdif out etm 1 etm_psb0 spdif o 2 spdif out pinctrl i/o 3 gpio3[13] pwm4 pwm i/o 0 pwm - 16ma drive for otg vbus etm o 1 etm_psb1 pinctrl i/o 3 gpio3[14] rotarya timer i/o 0 rotary encoder a pinctrl i/o 3 gpio3[15] rotaryb timer i/o 0 rotary encoder b pinctrl i/o 3 gpio3[16] table 1023. usb pins pin name module type pin mux description ref_res usb a usb reference resistor usb_dm usb a usb negative data line usb_dp usb a usb positive data line usb_otg_id usb a usb otg id sense table 1024. pin control?gpio pins pin name module type pin mux description gpmi_d00 gpmi i/o 0 ata/nand data 0 pinctrl i/o 3 gpio0[0] gpmi_d01 gpmi i/o 0 ata/nand data 1 pinctrl i/o 3 gpio0[1] gpmi_d02 gpmi i/o 0 ata/nand data 2 pinctrl i/o 3 gpio0[2] gpmi_d03 gpmi i/o 0 ata/nand data 3 pinctrl i/o 3 gpio0[3] gpmi_d04 gpmi i/o 0 ata/nand data 4 pinctrl i/o 3 gpio0[4] gpmi_d05 gpmi i/o 0 ata/nand data 5 pinctrl i/o 3 gpio0[5] gpmi_d06 gpmi i/o 0 ata/nand data 6 pinctrl i/o 3 gpio0[6] gpmi_d07 gpmi i/o 0 ata/nand data 7 pinctrl i/o 3 gpio0[7] table 1022. timer and pwm pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 836 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 gpmi_d08 gpmi i/o 0 ata/nand data 8 emi o 1 emi_a15 pinctrl i/o 3 gpio0[8] gpmi_d09 gpmi i/o 0 ata/nand data 9 etm o 1 emi_a16 pinctrl i/o 3 gpio0[9] gpmi_d10 gpmi i/o 0 ata/nand data 10 emi o 1 emi_a17 pinctrl i/o 3 gpio0[10] gpmi_d11 gpmi i/o 0 ata/nand data 11 emi o 1 emi_a18 pinctrl i/o 3 gpio0[11] gpmi_d12 gpmi i/o 0 ata/nand data 12 emi o 1 emi_a19 gpmi o 2 gpmi_ce0n pinctrl i/o 3 gpio0[12] gpmi_d13 gpmi i/o 0 ata/nand data 13 emi o 1 emi_a20 gpmi o 2 gpmi_ce1n pinctrl i/o 3 gpio0[13] gpmi_d14 gpmi i/o 0 ata/nand data 14 emi o 1 emi_a21 gpmi o 2 gpmi_ce2n pinctrl i/o 3 gpio0[14] gpmi_d15 gpmi i/o 0 ata/nand data 15 emi o 1 emi_a22 gpmi o 2 gpmi_ce3n pinctrl i/o 3 gpio0[15] gpmi_irq gpmi i 0 ata intrq or nand1 ready/busy# pinctrl i/o 3 gpio0[16] gpmi_rdn gpmi o 0 ata dior-:hstrobe or nand read strobe pinctrl i/o 3 gpio0[17] gpmi_rdy gpmi i 0 ata iordy:dstrobe or nand0 ready/busy# pinctrl i/o 3 gpio0[18] gpmi_rdy3 gpmi i/o 0 ata dmarq or nand3 r/b# emi o 1 emi_oen pinctrl i/o 3 gpio0[19] gpmi_rdy2 gpmi i/o 0 ata dmack or nand2 ready/busy# pinctrl i/o 3 gpio0[20] gpmi_wrn gpmi o 0 ata diow-:stop or nand write strobe pinctrl i/o 3 gpio0[21] gpmi_a0 gpmi o 0 ata_a0 or nand cle emi o 1 emi_a23 pinctrl i/o 3 gpio0[22] table 1024. pin control?gpio pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 837 gpmi_a1 gpmi o 0 ata_a1 or nand ale emi o 1 emi_a24 pinctrl i/o 3 gpio0[23] gpmi_a2 gpmi o 0 ata_a2 emi o 1 emi_a25 pinctrl i/o 3 gpio0[24] ssp_detect ssp i/o 0 removable card detect system o 2 rtck - jtag return clock pinctrl i/o 3 gpio0[25] ssp_cmd ssp i/o 0 spi mosi or ms sdio or sd/mmc cmd pinctrl i/o 3 gpio0[26] ssp_sck ssp i/o 0 spi serial clock - (bond to pin 100 in 100 tqfp) pinctrl i/o 3 gpio0[27] ssp_data0 ssp i/o 0 spi miso or sd/mmc dat0 pinctrl i/o 3 gpio0[28] ssp_data1 ssp i/o 0 sd/mmc data 1 pinctrl i/o 3 gpio0[29] ssp_data2 ssp i/o 0 sd/mmc data 2 pinctrl i/o 3 gpio0[30] ssp_data3 ssp i/o 0 spi slave select 0 or ms bs or sd/mmc dat3 pinctrl i/o 3 gpio0[31] lcd_d00 lcdif o 0 lcd interface data 0 etm o 1 etm_da0 pinctrl i/o 3 gpio1[0] lcd_d01 lcdif o 0 lcd interface data 1 etm o 1 etm_da1 pinctrl i/o 3 gpio1[1] lcd_d02 lcdif o 0 lcd interface data 2 etm o 1 etm_da2 pinctrl i/o 3 gpio1[2] lcd_d03 lcdif o 0 lcd interface data 3 etm o 1 etm_da3 pinctrl i/o 3 gpio1[3] lcd_d04 lcdif o 0 lcd interface data 4 etm o 1 etm_da4 pinctrl i/o 3 gpio1[4] lcd_d05 lcdif o 0 lcd interface data 5 etm o 1 etm_da5 pinctrl i/o 3 gpio1[5] lcd_d06 lcdif o 0 lcd interface data 6 etm o 1 etm_da6 pinctrl i/o 3 gpio1[6] table 1024. pin control?gpio pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 838 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 lcd_d07 lcdif o 0 lcd interface data 7 etm o 1 etm_da7 pinctrl i/o 3 gpio1[7] lcd_d08 lcdif o 0 lcd interface data 8 etm o 1 etm_db0 pinctrl i/o 3 gpio1[8] lcd_d09 lcdif o 0 lcd interface data 9 etm o 1 etm_db1 pinctrl i/o 3 gpio1[9] lcd_d10 lcdif o 0 lcd interface data 10 etm o 1 etm_db2 pinctrl i/o 3 gpio1[10] lcd_d11 lcdif o 0 lcd interface data 11 etm o 1 etm_db3 pinctrl i/o 3 gpio1[11] lcd_d12 lcdif o 0 lcd interface data 12 etm o 1 etm_db4 pinctrl i/o 3 gpio1[12] lcd_d13 lcdif o 0 lcd interface data 13 etm o 1 etm_db5 pinctrl i/o 3 gpio1[13] lcd_d14 lcdif o 0 lcd interface data 14 etm o 1 etm_db6 pinctrl i/o 3 gpio1[14] lcd_d15 lcdif o 0 lcd interface data 15 etm o 1 etm_db7 system o 2 rtck - jtag return clock pinctrl i/o 3 gpio1[15] lcd_reset lcdif o 0 lcd interface reset out etm o 1 etm_psa1 pinctrl i/o 3 gpio1[16] lcd_rs lcdif o 0 lcd interface register select etm o 1 etm_psa0 pinctrl i/o 3 gpio1[17] lcd_wr lcdif o 0 lcd interface data write etm o 1 etm_psa2 pinctrl i/o 3 gpio1[18] lcd_cs lcdif o 0 lcd interface chip select etm o 1 etm_tclk pinctrl i/o 3 gpio1[19] gpmi_resetn gpmi o 0 ata reset, nand write protect, or renesas reset etm o 1 emi_reset pinctrl i/o 3 gpio1[20] table 1024. pin control?gpio pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 839 lcd_busy lcdif i 0 lcd busy pinctrl i/o 3 gpio1[21] uart2_cts uart i 0 high-speed uart cts flow control pinctrl i/o 3 gpio1[22] uart2_rts uart o 0 high-speed uart rts flow control system o 1 rtck - jtag return clock ir o 2 ir_clk pinctrl i/o 3 gpio1[23] uart2_rx uart i 0 high-speed uart rx ir i 2 ir_rx pinctrl i/o 3 gpio1[24] uart2_tx uart i/o 0 high-speed uart tx ir o 2 ir_tx pinctrl i/o 3 gpio1[25] emi_d00 emi i/o 0 emi data 0 pinctrl i/o 3 gpio2[0] emi_d01 emi i/o 0 emi data 1 pinctrl i/o 3 gpio2[1] emi_d02 emi i/o 0 emi data 2 pinctrl i/o 3 gpio2[2] emi_d03 emi i/o 0 emi data 3 pinctrl i/o 3 gpio2[3] emi_d04 emi i/o 0 emi data 4 pinctrl i/o 3 gpio2[4] emi_d05 emi i/o 0 emi data 5 pinctrl i/o 3 gpio2[5] emi_d06 emi i/o 0 emi data 6 pinctrl i/o 3 gpio2[6] emi_d07 emi i/o 0 emi data 7 pinctrl i/o 3 gpio2[7] emi_d08 emi i/o 0 emi data 8 pinctrl i/o 3 gpio2[8] emi_d09 emi i/o 0 emi data 9 pinctrl i/o 3 gpio2[9] emi_d10 emi i/o 0 emi data 10 pinctrl i/o 3 gpio2[10] emi_d11 emi i/o 0 emi data 11 pinctrl i/o 3 gpio2[11] emi_d12 emi i/o 0 emi data 12 pinctrl i/o 3 gpio2[12] emi_d13 emi i/o 0 emi data 13 pinctrl i/o 3 gpio2[13] emi_d14 emi i/o 0 emi data 14 pinctrl i/o 3 gpio2[14] table 1024. pin control?gpio pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 840 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 emi_d15 emi i/o 0 emi data 15 pinctrl i/o 3 gpio2[15] emi_a00 emi o 0 emi address 0 pinctrl i/o 3 gpio2[16] emi_a01 emi o 0 emi address 1 pinctrl i/o 3 gpio2[17] emi_a02 emi o 0 emi address 2 pinctrl i/o 3 gpio2[18] emi_a03 emi o 0 emi address 3 pinctrl i/o 3 gpio2[19] emi_a04 emi o 0 emi address 4 pinctrl i/o 3 gpio2[20] emi_a05 emi o 0 emi address 5 pinctrl i/o 3 gpio2[21] emi_a06 emi o 0 emi address 6 pinctrl i/o 3 gpio2[22] emi_a07 emi o 0 emi address 7 pinctrl i/o 3 gpio2[23] emi_a08 emi o 0 emi address 8 pinctrl i/o 3 gpio2[24] emi_a09 emi o 0 emi address 9 pinctrl i/o 3 gpio2[25] emi_a10 emi o 0 emi address 10 pinctrl i/o 3 gpio2[26] emi_a11 emi o 0 emi address 11 pinctrl i/o 3 gpio2[27] emi_a12 emi o 0 emi address 12 pinctrl i/o 3 gpio2[28] emi_a13 emi o 0 emi address 13 / sdram ba0 pinctrl i/o 3 gpio2[29] emi_a14 emi o 0 emi address 14 / sdram ba1 pinctrl i/o 3 gpio2[30] emi_rasn emi o 0 emi rasn pinctrl i/o 3 gpio2[31] emi_ce0n emi o 0 emi ce0n gpmi o 1 gpmi_ce0n pinctrl i/o 3 gpio3[0] emi_ce1n emi o 0 emi ce1n gpmi o 1 gpmi_ce1n pinctrl i/o 3 gpio3[1] emi_ce2n emi i/o 0 emi ce2n gpmi o 1 gpmi_ce2n pinctrl i/o 3 gpio3[2] table 1024. pin control?gpio pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 35: pin descriptions 841 emi_ce3n emi i/o 0 emi ce3n gpmi o 1 gpmi_ce3n pinctrl i/o 3 gpio3[3] emi_clk emi o 0 emi clock pinctrl i/o 3 gpio3[4] emi_cke emi o 0 emi clock enable pinctrl i/o 3 gpio3[5] emi_casn emi o 0 emi casn pinctrl i/o 3 gpio3[6] emi_dqm0 emi o 0 emi dqm0 pinctrl i/o 3 gpio3[7] emi_dqm1 emi o 0 emi dqm1 pinctrl i/o 3 gpio3[8] emi_wen emi o 0 emi wen pinctrl i/o 3 gpio3[9] pwm0 pwm i/o 0 pwm etm o 1 etm_tsynca uartdbg i 2 uart1 rx (debug) pinctrl i/o 3 gpio3[10] pwm1 pwm i/o 0 pwm etm o 1 etm_tsyncb uartdbg o 2 uart1 tx (debug) pinctrl i/o 3 gpio3[11] pwm2 pwm i/o 0 pwm etm o 1 etm_psb2 system o 2 rtck - jtag return clock pinctrl i/o 3 gpio3[12] pwm3 pwm i/o 0 pwm - 16ma drive for spdif out etm 1 etm_psb0 spdif o 2 spdif out pinctrl i/o 3 gpio3[13] pwm4 pwm i/o 0 pwm - 16ma drive for otg vbus etm o 1 etm_psb1 pinctrl i/o 3 gpio3[14] rotarya timer i/o 0 rotary encoder a pinctrl i/o 3 gpio3[15] rotaryb timer i/o 0 rotary encoder b pinctrl i/o 3 gpio3[16] i2c_scl i2c i/o 0 i 2 c serial clock (o.d.) pinctrl i/o 3 gpio3[17] i2c_sda i2c i/o 0 i 2 c serial data (o.d.) pinctrl i/o 3 gpio3[18] table 1024. pin control?gpio pins (continued) pin name module type pin mux description free datasheet http:/// STMP36XX official product documentation 5/3/06 842 chapter 35: pin descriptions 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 36: package drawings 843 36. package drawings the STMP36XX is available in two different packages. this chapter includes the package drawings for the 100-pin tqfp and the 169-pin fpbga. 36.1. 100-pin tqfp dims. leads tol. max. basic .50 1.60 1.40 100l-1.4 thk. 16.00 14.00 16.00 14.00 l/f .60 a d e l e b a a d e 1 2 1 1 o 0-7d body + 2.00 mm footprint .05 .22 .05 .05 .05 +.15/-.10 .05 min./.15 max. ddd ccc max. max. .08 .20 .20 .127 .152 .08 2 1 n 1 1 1 d d e e a a a e 12 typ. 12 typ. ab d 1 n another variation of pin 1 visual aid .25 6p4 l a o b a 1 .20 rad. typ. .20 rad. typ. standoff .17 max. s d s a-b c m ddd c seating plane c ccc lead coplanarity 2) dimensions shown are nominal with tol. notes: 1) all dimensions in mm. as indicated . 3) l/f: eftec 64t copper or equivalent, 0.127 mm (.005") or 0.15 mm (.006") thick. 4) foot length "l" is measured at gage plane, at 0.25 above the seating plane. 100 pin 14x14 tqfp figure 151. 100-pin tqfp package drawing free datasheet http:/// STMP36XX official product documentation 5/3/06 844 chapter 36: package drawings 5-36xx-d1-1.02-050306 36.2. 169-pin fpbga 169 fpbga (11 x 11 mm) detail a side view bottom view all dimensions are in millimeters . 'e' represents the basic solder ball grid pitch. 'm' represents the basic solder ball matrix size. symbol 'n' is the number of balls in the ball matrix . 'b' is measurable at the maximum solder ball diameter parallel to primary datum c . dimension 'ddd' is measured parallel to primary datum c . primary datum c and seating plane are defined by the spherical crowns of the solder balls. solder ball diameter 'b' refers to post reflow condition. the pre-reflow diameter is 0.40mm. substrate material base is bt resin. the overall package thickness 'a' already considers collapse balls. dimensioning and tolerencing per asme y 14.5-1994. package dimensions take reference to jedec mo -205 f. seating plane 1 2 3 4 5 6 7 8 a b c d e f g h detail b 9 10 11 12 j k l m d1 e1 e e (datum b) (datum a) 13 n detail a a1 a 5 6 c ddd c c bbb nx detail b f f e nx b 4 eee c c ab fff m m 8 top view a b d e 2x 2x pin a1 index c aaa c aaa ref. a a1 d d1 e e1 b e f aaa bbb ddd eee fff m n dimensional references min. 1.14 0.21 10.80 10.80 0.37 0.60 nom. 1.30 0.28 11.00 9.60 bsc 11.00 9.60 bsc 0.43 0.80 bsc 0.70 13 169 max. 1.43 0.35 11.20 11.20 0.49 0.80 0.10 0.10 0.15 0.15 0.08 figure 152. 169-pin fpbga package drawing free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 chapter 37: STMP36XX part numbers and ordering information 845 37. STMP36XX part numbers an d ordering information the STMP36XX family comprises a large set of parts targeted at specific applica- tions and customers. table 1025 summarizes the family members and provides part numbers for order placement. customers with prepaid royalties or other royalty arrangements for certain intellec- tual property items can order parts without the corresponding royalty fees included in the purchase price. currently, the only royalty options are for certain mp3 items; see www.mp3licensing.com. the letter n at the end of the part number signifies a part that does not have the royalty payment included in the purchase price. table 1025. part numbers for STMP36XX family members part number royalty package description available stmp3660xxbbeb1m mp3 decode license included 169-pin fpbga mp3 encode enabled 4q05 stmp3660xxbbeb1n no mp3 decode license stmp3650xxbbeb1m mp3 decode license included 169-pin fpbga no mp3 encode support stmp3650xxbbeb1n no mp3 decode license stmp3640xxbbeb1m mp3 decode license included 169-pin fpbga 2mb sdram support no usb host no usb otg mp3 encode enabled 1q06 stmp3640xxbbeb1n no mp3 decode license stmp3630xxbbeb1m mp3 decode license included 169-pin fpbga 2mb sdram support no usb host no usb otg no mp3 encode support stmp3630xxbbeb1n no mp3 decode license free datasheet http:/// STMP36XX official product documentation 5/3/06 846 chapter 37: STMP36XX part numbers and ordering information 5-36xx-d1-1.02-050306 stmp3620xxbbeb1m mp3 decode license included 169-pin fpbga no sdram or nor support no ir support no usb host no usb otg no mpeg4 decode support mp3 encode enabled 2q06 stmp3620xxbbeb1n no mp3 decode license stmp3610xxbbeb1m mp3 decode license included 169-pin fpbga no sdram or nor support no ir support no usb host no usb otg no mpeg4 decode support no mp3 encode support stmp3610xxbbeb1n no mp3 decode license stmp3620xxlaeb1m mp3 decode license included 100-pin tqfp no lradc channels 2?5 no application uart no sdram or nor support no 32-khz rtc xtal driver no speaker driver 8-bit lcd data bus no ir support no usb host no usb otg no mpeg4 decode support mp3 encode enabled stmp3620xxlaeb1n no mp3 decode license stmp3610xxlaeb1m mp3 decode license included 100-pin tqfp no lradc channels 2?5 no application uart no sdram or nor support no 32-khz rtc xtal driver no speaker driver 8-bit lcd data bus no ir support no usb host no usb otg no mpeg4 decode support no mp3 encode support stmp3610xxlaeb1n no mp3 decode license table 1025. part numbers for STMP36XX family members (continued) part number royalty package description available free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 appendix: acronyms and abbreviations 847 appendix:acronyms and abbreviations this appendix includes definitions for many of th e acronyms and abbreviations found in this product data sheet. aac : advanced audio coding adc : analog-to-digital converter adc : adaptive differential pulse-code modulation ahb : advanced high-performance bus aio : analog input/output amba: advanced microcontro ller bus architecture apb : advanced peripheral bus apbh : advanced peripheral bus?hclk domain apbx: advanced peripheral bus?xclk domain arc : arc international (corporate name) arm : advanced risc machine (formerly acorn risc machine) ata : advanced technology attachment (hard drive interface) avc : adaptive voltage control batt : battery bist : built-in self-test bkpt : breakpoint clkctrl : clock control cp : charge pump cpuclk : processor (arm cpu) clock (see table 9. ?clock domains? on page 48.) cts : clear to send dabt : data abort dac : digital-to-analog converter db :decibel dc :direct current dflpt : default first-level page table digctl : digital control dio : digital input/output divx : digital video codec created by divxnetworks, inc. ecc : error correction code el : electroluminescent emi : external memory interface emiclk : emi clock (see table 9. ?clock domains? on page 48.) etm : embedded trace macrocell fiq : fast peripheral interrupt fir : finite impulse response; also fast infrared flpt : first-level page table free datasheet http:/// STMP36XX official product documentation 5/3/06 848 appendix: acronyms and abbreviations 5-36xx-d1-1.02-050306 freq : frequency fs : full-speed fsm : finite state machine? gpio : general-purpose input/output gpmi : general-purpose media interface gpmiclk : gmpi clock (see table 9. ?clock domains? on page 48.) hclk : main and hbus peripherals clock (see table 9. ?clock domains? on page 48.) hs : high-speed hw : hardware h.264 : high-compression digital video codec icoll : interrupt collector ir: infrared irda : infrared data association irovclk : ir clock (sourced from pll; see table 9. ?clock domains? on page 48.) irclk : ir clock (source from irovclk; see table 9. ?clock domains? on page 48.) irq : normal peripheral interrupt isr : interrupt service register jedec : joint electron device engineering council jpeg : joint photographic experts group (computer image format) li-ion : lithium ion (battery type) lradc : low resolution adc matt : multi-chip attachment mode mir : mid infrared mpeg4 : motion picture experts group 4 (standard for compressed video at 64 kbps) mp3 : moving picture experts group layer-3 audio mux : multiplexer nimh : nickel metal hydride nrzi : non-return to zero inverted otg : on the go pabt : instruction pre-fetch abort pda : personal digital assistant pddrm : portable device digital rights management (drm9) pfd : phase/frequency detector pfm : pulse frequency modulation phy : physical layer protocol pll : phase-locked loop pwm : pulse width modulation rtc : real-time clock rts : request to send free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 appendix: acronyms and abbreviations 849 rmw : read-modify-write sdio : secure digital input/output sdk : software development kit sir : serial infrared snr : signal-to-noise ratio soc : system-on-a-chip spdif : sony-philips digital interface format spdifclk : spdif clock (see table 9. ?clock domains? on page 48.) swi : software interrupt tbd : to be determined thd : total harmonic distortion tpc : transfer protocol commands tqfp : thin quad flat pack undef : undefined instruction udma : ultra direct memory access utmi : usb 2.0 transceiver macrocell interface vag : analog ground voltage vbg : internal bandgap voltage vco : variable crystal oscillator vdda :analog power vddd : digital power vfir : very fast irda wmdrm10 : windows media digital rights management 10 (janus) wma : windows media audio xclk : xbus peripherals clock (see table 9. ?clock domains? on page 48.) free datasheet http:/// STMP36XX official product documentation 5/3/06 850 appendix: acronyms and abbreviations 5-36xx-d1-1.02-050306 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 851 index: register names this index of register names appears in alphabetical order by register mnemonic. it includes the regis- ter address and the page number in the data sheet where each register is described. dflpt_entry_0000 ............................................... 0x800c0000 ...............................................121 dflpt_entry_2048 ............................................... 0x800c2000 ...............................................120 dflpt_entry4080 ................................................. 0x800c3fc0 ...............................................119 dflpt_entry4081 ................................................. 0x800c3fc4 ...............................................119 dflpt_entry4082 ................................................. 0x800c3fc8 ...............................................119 dflpt_entry4083 ................................................. 0x800c3fcc ..............................................119 dflpt_entry4084 ................................................. 0x800c3fd0 ...............................................119 dflpt_entry4085 ................................................. 0x800c3fd4 ...............................................119 dflpt_entry4086 ................................................. 0x800c3fd8 ...............................................119 dflpt_entry4087 ................................................. 0x800c3fdc ..............................................119 dflpt_entry4088 ................................................. 0x800c3fe0 ...............................................119 dflpt_entry4089 ................................................. 0x800c3fe4 ...............................................119 dflpt_entry4090 ................................................. 0x800c3fe8 ...............................................119 dflpt_entry4091 ................................................. 0x800c3fec ..............................................119 dflpt_entry4092 ................................................. 0x800c3ff0 ...............................................119 dflpt_entry4093 ................................................. 0x800c3ff4 ...............................................119 dflpt_entry4094 ................................................. 0x800c3ff8 ...............................................119 dflpt_entry4095 ................................................. 0x800c3ffc ..............................................118 hw_apbh_ch0_bar ..... .............. .............. ............. 0x80004060 ................................................202 hw_apbh_ch0_cmd .... .............. .............. ............. 0x80004050 ................................................200 hw_apbh_ch0_curcmdar ........... ........... .......... 0x80004030 ................................................199 hw_apbh_ch0_debug1 .............. .............. .......... 0x80004080 ................................................203 hw_apbh_ch0_debug2 .............. .............. .......... 0x80004090 ................................................205 hw_apbh_ch0_nxtcmdar ......... .............. .......... 0x80004040 ................................................199 hw_apbh_ch0_sema ..... .............. .............. .......... 0x80004070 ................................................202 hw_apbh_ch1_bar ..... .............. .............. ............. 0x800040d0 ...............................................209 hw_apbh_ch1_cmd .... .............. .............. ............. 0x800040c0 ...............................................207 hw_apbh_ch1_curcmdar ........... .............. ....... 0x800040a0 ................................................206 hw_apbh_ch1_debug1 ... .............. .............. ....... 0x800040f0 ................................................211 hw_apbh_ch1_debug2 .............. .............. .......... 0x80004100 ................................................212 hw_apbh_ch1_nxtcmdar ......... .............. .......... 0x800040b0 ................................................207 hw_apbh_ch1_sema ..... .............. .............. .......... 0x800040e0 ................................................210 hw_apbh_ch2_bar ..... .............. .............. ............. 0x80004140 ................................................216 hw_apbh_ch2_cmd .... .............. .............. ............. 0x80004130 ................................................214 hw_apbh_ch2_curcmdar ........... ........... .......... 0x80004110 ................................................213 hw_apbh_ch2_debug1 .............. .............. .......... 0x80004160 ................................................218 hw_apbh_ch2_debug2 .............. .............. .......... 0x80004170 ................................................219 hw_apbh_ch2_nxtcmdar ......... .............. .......... 0x80004120 ................................................214 hw_apbh_ch2_sema ..... .............. .............. .......... 0x80004150 ................................................217 hw_apbh_ch3_bar ..... .............. .............. ............. 0x800041b0 ................................................223 hw_apbh_ch3_cmd .... .............. .............. ............. 0x800041a0 ................................................221 hw_apbh_ch3_curcmdar ........... ........... .......... 0x80004180 ................................................220 hw_apbh_ch3_debug1 ... .............. .............. ....... 0x800041d0 ...............................................225 hw_apbh_ch3_debug2 ... .............. .............. ....... 0x800041e0 ................................................226 hw_apbh_ch3_nxtcmdar ......... .............. .......... 0x80004190 ................................................221 hw_apbh_ch3_sema ..... .............. .............. .......... 0x800041c0 ...............................................224 hw_apbh_ch4_bar ..... .............. .............. ............. 0x80004220 ................................................230 hw_apbh_ch4_cmd .... .............. .............. ............. 0x80004210 ................................................228 hw_apbh_ch4_curcmdar ........... .............. ....... 0x800041f0 ................................................227 hw_apbh_ch4_debug1 .............. .............. .......... 0x80004240 ................................................232 hw_apbh_ch4_debug2 .............. .............. .......... 0x80004250 ................................................233 hw_apbh_ch4_nxtcmdar ......... .............. .......... 0x80004200 ................................................228 hw_apbh_ch4_sema ..... .............. .............. .......... 0x80004230 ................................................231 hw_apbh_ch5_bar ..... .............. .............. ............. 0x80004290 ................................................237 hw_apbh_ch5_cmd .... .............. .............. ............. 0x80004280 ................................................235 hw_apbh_ch5_curcmdar ........... ........... .......... 0x80004260 ................................................234 hw_apbh_ch5_debug1 ... .............. .............. ....... 0x800042b0 ................................................239 free datasheet http:/// STMP36XX official product documentation 5/3/06 852 index: register names 5-36xx-d1-1.02-050306 hw_apbh_ch5_debug2 ... .............. .............. ....... 0x800042c0 ...............................................240 hw_apbh_ch5_nxtcmdar ......... .............. .......... 0x80004270 ................................................235 hw_apbh_ch5_sema ..... .............. .............. .......... 0x800042a0 ................................................238 hw_apbh_ch6_bar ..... .............. .............. ............. 0x80004300 ................................................244 hw_apbh_ch6_cmd .... .............. .............. ............. 0x800042f0 ................................................242 hw_apbh_ch6_curcmdar ........... .............. ....... 0x800042d0 ...............................................241 hw_apbh_ch6_debug1 .............. .............. .......... 0x80004320 ................................................246 hw_apbh_ch6_debug2 .............. .............. .......... 0x80004330 ................................................247 hw_apbh_ch6_nxtcmdar ......... .............. .......... 0x800042e0 ................................................242 hw_apbh_ch6_sema ..... .............. .............. .......... 0x80004310 ................................................245 hw_apbh_ch7_bar ..... .............. .............. ............. 0x80004370 ................................................251 hw_apbh_ch7_cmd .... .............. .............. ............. 0x80004360 ................................................249 hw_apbh_ch7_curcmdar ........... ........... .......... 0x80004340 ................................................248 hw_apbh_ch7_debug1 .............. .............. .......... 0x80004390 ................................................253 hw_apbh_ch7_debug2 ... .............. .............. ....... 0x800043a0 ................................................254 hw_apbh_ch7_nxtcmdar ......... .............. .......... 0x80004350 ................................................249 hw_apbh_ch7_sema ..... .............. .............. .......... 0x80004380 ................................................252 hw_apbh_ctrl0 .. .............. .............. ........... .......... 0x80004000 ................................................195 hw_apbh_ctrl0_clr . .............. .............. ............. 0x80004008 ................................................195 hw_apbh_ctrl0_set . .............. .............. ............. 0x80004004 ................................................195 hw_apbh_ctrl0_tog ... .............. .............. .......... 0x8000400c ...............................................195 hw_apbh_ctrl1 .. .............. .............. ........... .......... 0x80004010 ................................................196 hw_apbh_ctrl1_clr . .............. .............. ............. 0x80004018 ................................................196 hw_apbh_ctrl1_set . .............. .............. ............. 0x80004014 ................................................196 hw_apbh_ctrl1_tog ... .............. .............. .......... 0x8000401c ...............................................196 hw_apbh_devsel .. .............. ........... ........... .......... 0x80004020 ................................................198 hw_apbx_ch0_bar .............. ........... ........... .......... 0x80024060 ................................................270 hw_apbx_ch0_cmd ....... .............. .............. .......... 0x80024050 ................................................268 hw_apbx_ch0_curcmdar ........... ........... .......... 0x80024030 ................................................267 hw_apbx_ch0_debug1 . .............. .............. .......... 0x80024080 ................................................271 hw_apbx_ch0_debug2 . .............. .............. .......... 0x80024090 ................................................273 hw_apbx_ch0_nxtcmdar ......... .............. .......... 0x80024040 ................................................267 hw_apbx_ch0_sema ..... .............. .............. .......... 0x80024070 ................................................270 hw_apbx_ch1_bar .. .............. ............ ........... ....... 0x800240d0 ...............................................277 hw_apbx_ch1_cmd ....... .............. .............. .......... 0x800240c0 ...............................................275 hw_apbx_ch1_curcmdar .............. ........... ....... 0x800240a0 ................................................274 hw_apbx_ch1_debug1 .... .............. .............. ....... 0x800240f0 ................................................278 hw_apbx_ch1_debug2 . .............. .............. .......... 0x80024100 ................................................280 hw_apbx_ch1_nxtcmdar ............... ........... ....... 0x800240b0 ................................................275 hw_apbx_ch1_sema ........ .............. .............. ....... 0x800240e0 ................................................277 hw_apbx_ch2_bar .............. ........... ........... .......... 0x80024140 ................................................284 hw_apbx_ch2_cmd ....... .............. .............. .......... 0x80024130 ................................................282 hw_apbx_ch2_curcmdar ........... ........... .......... 0x80024110 ................................................281 hw_apbx_ch2_debug1 . .............. .............. .......... 0x80024160 ................................................285 hw_apbx_ch2_debug2 . .............. .............. .......... 0x80024170 ................................................287 hw_apbx_ch2_nxtcmdar ......... .............. .......... 0x80024120 ................................................282 hw_apbx_ch2_sema ..... .............. .............. .......... 0x80024150 ................................................284 hw_apbx_ch3_bar .. .............. ............ ........... ....... 0x800241b0 ................................................291 hw_apbx_ch3_cmd ....... .............. .............. .......... 0x800241a0 ................................................289 hw_apbx_ch3_curcmdar ........... ........... .......... 0x80024180 ................................................288 hw_apbx_ch3_debug1 .... .............. .............. ....... 0x800241d0 ...............................................292 hw_apbx_ch3_debug2 .... .............. .............. ....... 0x800241e0 ................................................294 hw_apbx_ch3_nxtcmdar ......... .............. .......... 0x80024190 ................................................289 hw_apbx_ch3_sema ........ .............. .............. ....... 0x800241c0 ...............................................291 hw_apbx_ch4_bar .............. ........... ........... .......... 0x80024220 ................................................298 hw_apbx_ch4_cmd ....... .............. .............. .......... 0x80024210 ................................................296 hw_apbx_ch4_curcmdar .............. ........... ....... 0x800241f0 ................................................295 hw_apbx_ch4_debug1 . .............. .............. .......... 0x80024240 ................................................299 hw_apbx_ch4_debug2 . .............. .............. .......... 0x80024250 ................................................301 hw_apbx_ch4_nxtcmdar ......... .............. .......... 0x80024200 ................................................296 hw_apbx_ch4_sema ..... .............. .............. .......... 0x80024230 ................................................298 hw_apbx_ch5_bar .............. ........... ........... .......... 0x80024290 ................................................305 hw_apbx_ch5_cmd ....... .............. .............. .......... 0x80024280 ................................................303 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 853 hw_apbx_ch5_curcmdar ........... ........... .......... 0x80024260 ................................................302 hw_apbx_ch5_debug1 .... .............. .............. ....... 0x800242b0 ................................................306 hw_apbx_ch5_debug2 .... .............. .............. ....... 0x800242c0 ...............................................308 hw_apbx_ch5_nxtcmdar ......... .............. .......... 0x80024270 ................................................303 hw_apbx_ch5_sema ........ .............. .............. ....... 0x800242a0 ................................................305 hw_apbx_ch6_bar .............. ........... ........... .......... 0x80024300 ................................................312 hw_apbx_ch6_cmd ....... .............. .............. .......... 0x800242f0 ................................................310 hw_apbx_ch6_curcmdar .............. ........... ....... 0x800242d0 ...............................................309 hw_apbx_ch6_debug1 . .............. .............. .......... 0x80024320 ................................................313 hw_apbx_ch6_debug2 . .............. .............. .......... 0x80024330 ................................................315 hw_apbx_ch6_nxtcmdar ............... ........... ....... 0x800242e0 ................................................310 hw_apbx_ch6_sema ..... .............. .............. .......... 0x80024310 ................................................312 hw_apbx_ch7_bar .............. ........... ........... .......... 0x80024370 ................................................319 hw_apbx_ch7_cmd ....... .............. .............. .......... 0x80024360 ................................................317 hw_apbx_ch7_curcmdar ........... ........... .......... 0x80024340 ................................................316 hw_apbx_ch7_debug1 . .............. .............. .......... 0x80024390 ................................................320 hw_apbx_ch7_debug2 .... .............. .............. ....... 0x800243a0 ................................................322 hw_apbx_ch7_nxtcmdar ......... .............. .......... 0x80024350 ................................................317 hw_apbx_ch7_sema ..... .............. .............. .......... 0x80024380 ................................................319 hw_apbx_ctrl0 ..... .............. ........... ........... .......... 0x80024000 ................................................263 hw_apbx_ctrl0_clr .... .............. .............. .......... 0x80024008 ................................................263 hw_apbx_ctrl0_set .... .............. .............. .......... 0x80024004 ................................................263 hw_apbx_ctrl0_tog ... .............. .............. .......... 0x8002400c ...............................................263 hw_apbx_ctrl1 ..... .............. ........... ........... .......... 0x80024010 ................................................264 hw_apbx_ctrl1_clr .... .............. .............. .......... 0x80024018 ................................................264 hw_apbx_ctrl1_set .... .............. .............. .......... 0x80024014 ................................................264 hw_apbx_ctrl1_tog ... .............. .............. .......... 0x8002401c ...............................................264 hw_apbx_devsel .. .............. ........... ........... .......... 0x80024020 ................................................266 hw_audioin_adcdebug ..................................... 0x8004c040 ...............................................638 hw_audioin_adcdebug_clr ............................ 0x8004c048 ...............................................638 hw_audioin_adcdebug_set ............................ 0x8004c044 ...............................................638 hw_audioin_adcdebug_tog ........................... 0x8004c04c ...............................................638 hw_audioin_adcsrr .......................................... 0x8004c020 ...............................................634 hw_audioin_adcsrr_clr ................................. 0x8004c028 ...............................................634 hw_audioin_adcsrr_set ................................. 0x8004c024 ...............................................634 hw_audioin_adcsrr_tog ................................ 0x8004c02c ...............................................634 hw_audioin_adcvol .......................................... 0x8004c050 ...............................................640 hw_audioin_adcvol_clr ................................. 0x8004c058 ...............................................640 hw_audioin_adcvol_set ................................. 0x8004c054 ...............................................640 hw_audioin_adcvol_tog ................................. 0x8004c05c ...............................................640 hw_audioin_adcvolume .................................. 0x8004c030 ...............................................636 hw_audioin_adcvolume_clr ......................... 0x8004c038 ...............................................636 hw_audioin_adcvolume_set ......................... 0x8004c034 ...............................................636 hw_audioin_adcvolume_tog ......................... 0x8004c03c ...............................................636 hw_audioin_anaclkctrl ................................. 0x8004c070 ...............................................643 hw_audioin_anaclkctrl_clr ........................ 0x8004c078 ...............................................643 hw_audioin_anaclkctrl_set ........................ 0x8004c074 ...............................................643 hw_audioin_anaclkctrl_tog ........................ 0x8004c07c ...............................................643 hw_audioin_ctrl ................................................ 0x8004c000 ...............................................631 hw_audioin_ctrl_clr ....................................... 0x8004c008 ...............................................631 hw_audioin_ctrl_set ....................................... 0x8004c004 ...............................................631 hw_audioin_ctrl_tog ...................................... 0x8004c00c ...............................................631 hw_audioin_data ................................................ 0x8004c080 ...............................................644 hw_audioin_data_clr ...................................... 0x8004c088 ...............................................644 hw_audioin_data_set ....................................... 0x8004c084 ...............................................644 hw_audioin_data_tog ...................................... 0x8004c08c ...............................................644 hw_audioin_micline ........................................... 0x8004c060 ...............................................641 hw_audioin_micline_clr ................................. 0x8004c068 ...............................................641 hw_audioin_micline_set .................................. 0x8004c064 ...............................................641 hw_audioin_micline_tog ................................. 0x8004c06c ...............................................641 hw_audioin_stat ................................................ 0x8004c010 ...............................................634 hw_audioin_stat_clr ....................................... 0x8004c018 ...............................................634 hw_audioin_stat_set ....................................... 0x8004c014 ...............................................634 free datasheet http:/// STMP36XX official product documentation 5/3/06 854 index: register names 5-36xx-d1-1.02-050306 hw_audioin_stat_tog ...................................... 0x8004c01c ...............................................634 hw_audioout_anaclkctrl ............................. 0x800480e0 ................................................676 hw_audioout_anaclkctrl_clr .................... 0x800480e8 ................................................676 hw_audioout_anaclkctrl_set .................... 0x800480e4 ................................................676 hw_audioout_anaclkctrl_tog .................... 0x800480ec ...............................................676 hw_audioout_anactrl .................................... 0x80048090 ................................................671 hw_audioout_anactrl_clr ........................... 0x80048098 ................................................671 hw_audioout_anactrl_set ........................... 0x80048094 ................................................671 hw_audioout_anactrl_tog ........................... 0x8004809c ...............................................671 hw_audioout_bistctrl .................................... 0x800480b0 ................................................675 hw_audioout_bistctrl_clr ........................... 0x800480b8 ................................................675 hw_audioout_bistctrl_set ........................... 0x800480b4 ................................................675 hw_audioout_bistctrl_tog .......................... 0x800480bc ...............................................675 hw_audioout_biststat0 .................................. 0x800480c0 ................................................675 hw_audioout_biststat0_clr ......................... 0x800480c8 ................................................675 hw_audioout_biststat0_set ......................... 0x800480c4 ................................................675 hw_audioout_biststat0_tog ........................ 0x800480cc ................................................675 hw_audioout_biststat1 .................................. 0x800480d0 ................................................676 hw_audioout_biststat1_clr ......................... 0x800480d8 ................................................676 hw_audioout_biststat1_set ......................... 0x800480d4 ................................................676 hw_audioout_biststat1_tog ........................ 0x800480dc ...............................................676 hw_audioout_ctrl ............................................ 0x80048000 ................................................657 hw_audioout_ctrl_clr ................................... 0x80048008 ................................................657 hw_audioout_ctrl_set ................................... 0x80048004 ................................................657 hw_audioout_ctrl_tog .................................. 0x8004800c ...............................................657 hw_audioout_dacdebug ................................. 0x80048040 ................................................664 hw_audioout_dacdebug_clr ........................ 0x80048048 ................................................664 hw_audioout_dacdebug_set ........................ 0x80048044 ................................................664 hw_audioout_dacdebug_tog ....................... 0x8004804c ...............................................664 hw_audioout_dacsrr ...................................... 0x80048020 ................................................660 hw_audioout_dacsrr_clr ............................. 0x80048028 ................................................660 hw_audioout_dacsrr_set ............................. 0x80048024 ................................................660 hw_audioout_dacsrr_tog ............................ 0x8004802c ...............................................660 hw_audioout_dacvolume .............................. 0x80048030 ................................................662 hw_audioout_dacvolume_clr ..................... 0x80048038 ................................................662 hw_audioout_dacvolume_set ..................... 0x80048034 ................................................662 hw_audioout_dacvolume_tog ..................... 0x8004803c ...............................................662 hw_audioout_data ............................................ 0x800480f0 .................................................677 hw_audioout_data_clr .................................. 0x800480f8 .................................................677 hw_audioout_data_set ................................... 0x800480f4 .................................................677 hw_audioout_data_tog .................................. 0x800480fc ................................................677 hw_audioout_hpvol ......................................... 0x80048050 ................................................665 hw_audioout_hpvol_clr ................................ 0x80048058 ................................................665 hw_audioout_hpvol_set ................................ 0x80048054 ................................................665 hw_audioout_hpvol_tog ............................... 0x8004805c ...............................................665 hw_audioout_pwrdn ........................................ 0x80048070 ................................................667 hw_audioout_pwrdn_clr .............................. 0x80048078 ................................................667 hw_audioout_pwrdn_set ............................... 0x80048074 ................................................667 hw_audioout_pwrdn_tog .............................. 0x8004807c ...............................................667 hw_audioout_refctrl ..................................... 0x80048080 ................................................668 hw_audioout_refctrl_clr ........................... 0x80048088 ................................................668 hw_audioout_refctrl_set ............................ 0x80048084 ................................................668 hw_audioout_refctrl_tog ........................... 0x8004808c ...............................................668 hw_audioout_spkrvol ............ .............. .......... 0x80048060 ................................................666 hw_audioout_spkrvol_clr ...... ........... .......... 0x80048068 ................................................666 hw_audioout_spkrvol_set ...... ........... .......... 0x80048064 ................................................666 hw_audioout_spkrvol_tog ..... ........... .......... 0x8004806c ...............................................666 hw_audioout_stat ............................................ 0x80048010 ................................................659 hw_audioout_stat_clr ................................... 0x80048018 ................................................659 hw_audioout_stat_set ................................... 0x80048014 ................................................659 hw_audioout_stat_tog .................................. 0x8004801c ...............................................660 hw_audioout_test ............................................ 0x800480a0 ................................................673 hw_audioout_test_clr ................................... 0x800480a8 ................................................673 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 855 hw_audioout_test_set ................................... 0x800480a4 ................................................673 hw_audioout_test_tog .................................. 0x800480ac ...............................................673 hw_clkctrl_cpuclkctrl ................................ 0x80040020 ..................................................58 hw_clkctrl_emiclkctrl ................................. 0x800400b0 ..................................................67 hw_clkctrl_gpmiclkctrl .............................. 0x80040090 ..................................................65 hw_clkctrl_hbusclkctrl ............................. 0x80040030 ..................................................59 hw_clkctrl_irclkctrl .................................... 0x800400c0 ..................................................67 hw_clkctrl_ocramclkctrl .......................... 0x80040060 ..................................................63 hw_clkctrl_pllctrl0 ...................................... 0x80040000 ..................................................56 hw_clkctrl_pllctrl0_clr ............................. 0x80040008 ..................................................56 hw_clkctrl_pllctrl0_set ............................. 0x80040004 ..................................................56 hw_clkctrl_pllctrl0_tog ............................ 0x8004000c .................................................56 hw_clkctrl_pllctrl1 ...................................... 0x80040010 ..................................................58 hw_clkctrl_pllctrl1_clr ............................. 0x80040018 ..................................................58 hw_clkctrl_pllctrl1_set ............................. 0x80040014 ..................................................58 hw_clkctrl_pllctrl1_tog ............................ 0x8004001c .................................................58 hw_clkctrl_spdifclkctrl ............................. 0x800400a0 ..................................................66 hw_clkctrl_sspclkctrl ........ .............. .......... 0x80040080 ..................................................64 hw_clkctrl_utmiclkctrl ............................... 0x80040070 ..................................................63 hw_clkctrl_xbusclkctrl .............................. 0x80040040 ..................................................61 hw_clkctrl_xtalclkctrl .............................. 0x80040050 ..................................................62 hw_digctl_1tram_bist_csr ........................... 0x8001c0e0 ...............................................140 hw_digctl_1tram_bist_csr_clr .................. 0x8001c0e8 ...............................................140 hw_digctl_1tram_bist_csr_set .................. 0x8001c0e4 ...............................................140 hw_digctl_1tram_bist_csr_tog ................. 0x8001c0ec ..............................................140 hw_digctl_1tram_bi st_repair0 ......... .......... 0x8001c0f0 ...............................................140 hw_digctl_1tram_bi st_repair0_clr ... ....... 0x8001c0f8 ...............................................141 hw_digctl_1tram_bi st_repair0_set ... ....... 0x8001c0f4 ...............................................141 hw_digctl_1tram_bi st_repair0_tog ... ....... 0x8001c0fc ...............................................141 hw_digctl_1tram_bi st_repair1 ......... .......... 0x8001c100 ...............................................141 hw_digctl_1tram_bi st_repair1_clr ... ....... 0x8001c108 ...............................................141 hw_digctl_1tram_bi st_repair1_set ... ....... 0x8001c104 ...............................................141 hw_digctl_1tram_bi st_repair1_tog ... ....... 0x8001c10c ...............................................141 hw_digctl_1tram_status0 ............................. 0x8001c110 ...............................................142 hw_digctl_1tram_status0_clr ................... 0x8001c118 ...............................................142 hw_digctl_1tram_status0_set .................... 0x8001c114 ...............................................142 hw_digctl_1tram_status0_tog ................... 0x8001c11c ...............................................142 hw_digctl_1tram_status1 ............................. 0x8001c120 ...............................................142 hw_digctl_1tram_status1_clr ................... 0x8001c128 ...............................................142 hw_digctl_1tram_status1_set .................... 0x8001c124 ...............................................142 hw_digctl_1tram_status1_tog ................... 0x8001c12c ...............................................142 hw_digctl_1tram_status10 ........................... 0x8001c1b0 ...............................................147 hw_digctl_1tram_status10_clr ................. 0x8001c1b8 ...............................................147 hw_digctl_1tram_status10_set .................. 0x8001c1b4 ...............................................147 hw_digctl_1tram_status10_tog ................. 0x8001c1bc ..............................................147 hw_digctl_1tram_status11 ........................... 0x8001c1c0 ...............................................147 hw_digctl_1tram_status11_clr ................. 0x8001c1c8 ...............................................147 hw_digctl_1tram_status11_set .................. 0x8001c1c4 ...............................................147 hw_digctl_1tram_status11_tog ................. 0x8001c1cc ..............................................148 hw_digctl_1tram_status12 ........................... 0x8001c1d0 ...............................................148 hw_digctl_1tram_status12_clr ................. 0x8001c1d8 ...............................................148 hw_digctl_1tram_status12_set .................. 0x8001c1d4 ...............................................148 hw_digctl_1tram_status12_tog ................. 0x8001c1dc ..............................................148 hw_digctl_1tram_status13 ........................... 0x8001c1e0 ...............................................149 hw_digctl_1tram_status13_clr ................. 0x8001c1e8 ...............................................149 hw_digctl_1tram_status13_set .................. 0x8001c1e4 ...............................................149 hw_digctl_1tram_status13_tog ................. 0x8001c1ec ..............................................149 hw_digctl_1tram_status2 ............................. 0x8001c130 ...............................................143 hw_digctl_1tram_status2_clr ................... 0x8001c138 ...............................................143 hw_digctl_1tram_status2_set .................... 0x8001c134 ...............................................143 hw_digctl_1tram_status2_tog ................... 0x8001c13c ...............................................143 hw_digctl_1tram_status3 ............................. 0x8001c140 ...............................................143 hw_digctl_1tram_status3_clr ................... 0x8001c148 ...............................................143 free datasheet http:/// STMP36XX official product documentation 5/3/06 856 index: register names 5-36xx-d1-1.02-050306 hw_digctl_1tram_status3_set .................... 0x8001c144 ...............................................143 hw_digctl_1tram_status3_tog ................... 0x8001c14c ...............................................143 hw_digctl_1tram_status4 ............................. 0x8001c150 ...............................................144 hw_digctl_1tram_status4_clr ................... 0x8001c158 ...............................................144 hw_digctl_1tram_status4_set .................... 0x8001c154 ...............................................144 hw_digctl_1tram_status4_tog ................... 0x8001c15c ...............................................144 hw_digctl_1tram_status5 ............................. 0x8001c160 ...............................................144 hw_digctl_1tram_status5_clr ................... 0x8001c168 ...............................................144 hw_digctl_1tram_status5_set .................... 0x8001c164 ...............................................144 hw_digctl_1tram_status5_tog ................... 0x8001c16c ...............................................144 hw_digctl_1tram_status6 ............................. 0x8001c170 ...............................................145 hw_digctl_1tram_status6_clr ................... 0x8001c178 ...............................................145 hw_digctl_1tram_status6_set .................... 0x8001c174 ...............................................145 hw_digctl_1tram_status6_tog ................... 0x8001c17c ...............................................145 hw_digctl_1tram_status7 ............................. 0x8001c180 ...............................................145 hw_digctl_1tram_status7_clr ................... 0x8001c188 ...............................................145 hw_digctl_1tram_status7_set .................... 0x8001c184 ...............................................145 hw_digctl_1tram_status7_tog ................... 0x8001c18c ...............................................145 hw_digctl_1tram_status8 ............................. 0x8001c190 ...............................................146 hw_digctl_1tram_status8_clr ................... 0x8001c198 ...............................................146 hw_digctl_1tram_status8_set .................... 0x8001c194 ...............................................146 hw_digctl_1tram_status8_tog ................... 0x8001c19c ...............................................146 hw_digctl_1tram_status9 ............................. 0x8001c1a0 ...............................................146 hw_digctl_1tram_status9_clr ................... 0x8001c1a8 ...............................................146 hw_digctl_1tram_status9_set .................... 0x8001c1a4 ...............................................146 hw_digctl_1tram_status9_tog ................... 0x8001c1ac ..............................................146 hw_digctl_ahbcycles ..................................... 0x8001c070 ...............................................136 hw_digctl_ahbstalled .................................... 0x8001c080 ...............................................136 hw_digctl_armcache ...................................... 0x8001c2b0 ...............................................151 hw_digctl_chipid ............................................... 0x8001c310 ...............................................152 hw_digctl_ctrl .................................................. 0x8001c000 ...............................................128 hw_digctl_ctrl_clr ........................................ 0x8001c008 ...............................................128 hw_digctl_ctrl_set ......................................... 0x8001c004 ...............................................128 hw_digctl_ctrl_tog ........................................ 0x8001c00c ...............................................128 hw_digctl_dbg ................................................... 0x8001c0d0 ...............................................139 hw_digctl_dbgrd .............................................. 0x8001c0c0 ...............................................139 hw_digctl_entropy .......................................... 0x8001c090 ...............................................137 hw_digctl_hclkcount ..................................... 0x8001c020 ...............................................131 hw_digctl_hclkcount_clr ........................... 0x8001c028 ...............................................131 hw_digctl_hclkcount_set ............................ 0x8001c024 ...............................................131 hw_digctl_hclkcount_tog ........................... 0x8001c02c ...............................................131 hw_digctl_microseconds ............................. 0x8001c0b0 ...............................................138 hw_digctl_microseconds_clr .................... 0x8001c0b8 ...............................................138 hw_digctl_microseconds_set .................... 0x8001c0b4 ...............................................138 hw_digctl_microseconds_tog ................... 0x8001c0bc ..............................................138 hw_digctl_ramctrl .......................................... 0x8001c030 ...............................................131 hw_digctl_ramctrl_clr ................................ 0x8001c038 ...............................................131 hw_digctl_ramctrl_set ................................. 0x8001c034 ...............................................131 hw_digctl_ramctrl_tog ................................ 0x8001c03c ...............................................131 hw_digctl_ramrepair0 ............ .............. .......... 0x8001c040 ...............................................133 hw_digctl_ramrepair 0_clr ........ ........... ....... 0x8001c048 ...............................................133 hw_digctl_ramrepair 0_set ......... ........... ....... 0x8001c044 ...............................................133 hw_digctl_ramrepair0_tog ..... .............. ....... 0x8001c04c ...............................................133 hw_digctl_ramrepair1 ............ .............. .......... 0x8001c050 ...............................................134 hw_digctl_ramrepair 1_clr ........ ........... ....... 0x8001c058 ...............................................134 hw_digctl_ramrepair 1_set ......... ........... ....... 0x8001c054 ...............................................134 hw_digctl_ramrepair1_tog ..... .............. ....... 0x8001c05c ...............................................134 hw_digctl_romshield ...................................... 0x8001c0a0 ...............................................138 hw_digctl_scratch0 ........................................ 0x8001c290 ...............................................150 hw_digctl_scratch1 ........................................ 0x8001c2a0 ...............................................150 hw_digctl_sgtl .................................................. 0x8001c300 ...............................................151 hw_digctl_status ............................................. 0x8001c010 ...............................................130 hw_digctl_status_clr .................................... 0x8001c018 ...............................................130 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 857 hw_digctl_status_set .................................... 0x8001c014 ...............................................130 hw_digctl_status_tog ................................... 0x8001c01c ...............................................130 hw_digctl_writeonce ..................................... 0x8001c060 ...............................................135 hw_dri_ctrl ......................................................... 0x80074000 ................................................697 hw_dri_ctrl_clr ............................................... 0x80074008 ................................................697 hw_dri_ctrl_set ................................................ 0x80074004 ................................................697 hw_dri_ctrl_tog ............................................... 0x8007400c ...............................................697 hw_dri_data ........................................................ 0x80074030 ................................................701 hw_dri_debug0 ................................................... 0x80074040 ................................................702 hw_dri_debug0_clr .......................................... 0x80074048 ................................................702 hw_dri_debug0_set .......................................... 0x80074044 ................................................702 hw_dri_debug0_tog ......................................... 0x8007404c ...............................................702 hw_dri_debug1 ................................................... 0x80074050 ................................................703 hw_dri_debug1_clr .......................................... 0x80074058 ................................................703 hw_dri_debug1_set .......................................... 0x80074054 ................................................703 hw_dri_debug1_tog ......................................... 0x8007405c ...............................................703 hw_dri_stat ......................................................... 0x80074020 ................................................700 hw_dri_timing ..................................................... 0x80074010 ................................................699 hw_emictrl .......................................................... 0x80020000 ................................................329 hw_emictrl_clr ................................................. 0x80020008 ................................................329 hw_emictrl_set ................................................. 0x80020004 ................................................329 hw_emictrl_tog ................................................. 0x8002000c ...............................................329 hw_emidebug ....................................................... 0x80020020 ................................................331 hw_emidramaddr ............................................... 0x800200a0 ................................................334 hw_emidramaddr_clr ...................................... 0x800200a8 ................................................334 hw_emidramaddr_set ...................................... 0x800200a4 ................................................334 hw_emidramaddr_tog ..................................... 0x800200ac ...............................................334 hw_emidramctrl ................................................ 0x80020090 ................................................333 hw_emidramctrl_clr ....................................... 0x80020098 ................................................333 hw_emidramctrl_set ....................................... 0x80020094 ................................................333 hw_emidramctrl_tog ...................................... 0x8002009c ...............................................333 hw_emidrammode .............................................. 0x800200b0 ................................................335 hw_emidramstat ................................................ 0x80020080 ................................................332 hw_emidramtime ................................................. 0x800200c0 ...............................................336 hw_emidramtime_clr ....................................... 0x800200c8 ...............................................336 hw_emidramtime_set ........................................ 0x800200c4 ...............................................336 hw_emidramtime_tog ....................................... 0x800200cc ...............................................336 hw_emidramtime2 ............................................... 0x800200d0 ...............................................338 hw_emidramtime2_clr ..................................... 0x800200d8 ...............................................338 hw_emidramtime2_set ...................................... 0x800200d4 ...............................................338 hw_emidramtime2_tog ..................................... 0x800200dc ...............................................338 hw_emistat ........................................................... 0x80020010 ................................................330 hw_emistaticctrl .............................................. 0x80020100 ................................................338 hw_emistaticctrl_clr .................................... 0x80020108 ................................................338 hw_emistaticctrl_set ..................................... 0x80020104 ................................................338 hw_emistaticctrl_tog .................................... 0x8002010c ...............................................338 hw_emistatictime .............................................. 0x80020110 ................................................339 hw_emistatictime_clr ..................................... 0x80020118 ................................................339 hw_emistatictime_set ..................................... 0x80020114 ................................................339 hw_emistatictime_tog ..................................... 0x8002011c ...............................................339 hw_gpmi_compare ............................................. 0x8000c010 ...............................................351 hw_gpmi_ctrl0 .................................................... 0x8000c000 ...............................................348 hw_gpmi_ctrl0_clr .......................................... 0x8000c008 ...............................................348 hw_gpmi_ctrl0_set ........................................... 0x8000c004 ...............................................348 hw_gpmi_ctrl0_tog .......................................... 0x8000c00c ...............................................348 hw_gpmi_ctrl1 .................................................... 0x8000c020 ...............................................351 hw_gpmi_ctrl1_clr .......................................... 0x8000c028 ...............................................351 hw_gpmi_ctrl1_set ........................................... 0x8000c024 ...............................................351 hw_gpmi_ctrl1_tog .......................................... 0x8000c02c ...............................................351 hw_gpmi_data ..................................................... 0x8000c060 ...............................................356 hw_gpmi_debug .................................................. 0x8000c080 ...............................................357 hw_gpmi_stat ...................................................... 0x8000c070 ...............................................356 hw_gpmi_timing0 ................................................ 0x8000c030 ...............................................353 free datasheet http:/// STMP36XX official product documentation 5/3/06 858 index: register names 5-36xx-d1-1.02-050306 hw_gpmi_timing1 ................................................ 0x8000c040 ...............................................354 hw_gpmi_timing2 ................................................ 0x8000c050 ...............................................355 hw_hwecc_ctrl ................................................. 0x80008000 ................................................373 hw_hwecc_ctrl_clr ........................................ 0x80008008 ................................................373 hw_hwecc_ctrl_set ........................................ 0x80008004 ................................................373 hw_hwecc_ctrl_tog ....................................... 0x8000800c ...............................................373 hw_hwecc_data ................................................. 0x80008090 ................................................381 hw_hwecc_data_clr ........................................ 0x80008098 ................................................381 hw_hwecc_data_set ........................................ 0x80008094 ................................................381 hw_hwecc_data_tog ....................................... 0x8000809c ...............................................381 hw_hwecc_debug0 ............................................ 0x80008020 ................................................375 hw_hwecc_debug0_clr ................................... 0x80008028 ................................................375 hw_hwecc_debug0_set ................................... 0x80008024 ................................................375 hw_hwecc_debug0_tog .................................. 0x8000802c ...............................................375 hw_hwecc_debug1 ............................................ 0x80008030 ................................................377 hw_hwecc_debug1_clr ................................... 0x80008038 ................................................377 hw_hwecc_debug1_set ................................... 0x80008034 ................................................377 hw_hwecc_debug1_tog .................................. 0x8000803c ...............................................377 hw_hwecc_debug2 ............................................ 0x80008040 ................................................378 hw_hwecc_debug2_clr ................................... 0x80008048 ................................................378 hw_hwecc_debug2_set ................................... 0x80008044 ................................................378 hw_hwecc_debug2_tog .................................. 0x8000804c ...............................................378 hw_hwecc_debug3 ............................................ 0x80008050 ................................................378 hw_hwecc_debug3_clr ................................... 0x80008058 ................................................378 hw_hwecc_debug3_set ................................... 0x80008054 ................................................378 hw_hwecc_debug3_tog .................................. 0x8000805c ...............................................378 hw_hwecc_debug4 ............................................ 0x80008060 ................................................379 hw_hwecc_debug4_clr ................................... 0x80008068 ................................................379 hw_hwecc_debug4_set ................................... 0x80008064 ................................................379 hw_hwecc_debug4_tog .................................. 0x8000806c ...............................................379 hw_hwecc_debug5 ............................................ 0x80008070 ................................................380 hw_hwecc_debug5_clr ................................... 0x80008078 ................................................380 hw_hwecc_debug5_set ................................... 0x80008074 ................................................380 hw_hwecc_debug5_tog .................................. 0x8000807c ...............................................380 hw_hwecc_debug6 ............................................ 0x80008080 ................................................380 hw_hwecc_debug6_clr ................................... 0x80008088 ................................................381 hw_hwecc_debug6_set ................................... 0x80008084 ................................................381 hw_hwecc_debug6_tog .................................. 0x8000808c ...............................................381 hw_hwecc_stat ................................................. 0x80008010 ................................................374 hw_hwecc_stat_clr ........................................ 0x80008018 ................................................375 hw_hwecc_stat_set ........................................ 0x80008014 ................................................374 hw_hwecc_stat_tog ........................................ 0x8000801c ...............................................375 hw_i2c_ctrl0 ....................................................... 0x80058000 ................................................555 hw_i2c_ctrl0_clr .............................................. 0x80058008 ................................................555 hw_i2c_ctrl0_set .............................................. 0x80058004 ................................................555 hw_i2c_ctrl0_tog ............................................. 0x8005800c ...............................................555 hw_i2c_ctrl1 ....................................................... 0x80058040 ................................................560 hw_i2c_ctrl1_clr .............................................. 0x80058048 ................................................560 hw_i2c_ctrl1_set .............................................. 0x80058044 ................................................560 hw_i2c_ctrl1_tog ............................................. 0x8005804c ...............................................560 hw_i2c_data ......................................................... 0x80058060 ................................................567 hw_i2c_debug0 .................................................... 0x80058070 ................................................567 hw_i2c_debug0_clr ........................................... 0x80058078 ................................................568 hw_i2c_debug0_set ........................................... 0x80058074 ................................................568 hw_i2c_debug0_tog .......................................... 0x8005807c ...............................................568 hw_i2c_debug1 .................................................... 0x80058080 ................................................569 hw_i2c_debug1_clr ........................................... 0x80058088 ................................................569 hw_i2c_debug1_set ........................................... 0x80058084 ................................................569 hw_i2c_debug1_tog .......................................... 0x8005808c ...............................................569 hw_i2c_stat ......................................................... 0x80058050 ................................................563 hw_i2c_timing0 .................................................... 0x80058010 ................................................558 hw_i2c_timing0_clr ........................................... 0x80058018 ................................................558 hw_i2c_timing0_set ........................................... 0x80058014 ................................................558 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 859 hw_i2c_timing0_tog .......................................... 0x8005801c ...............................................558 hw_i2c_timing1 .................................................... 0x80058020 ................................................558 hw_i2c_timing1_clr ........................................... 0x80058028 ................................................558 hw_i2c_timing1_set ........................................... 0x80058024 ................................................558 hw_i2c_timing1_tog .......................................... 0x8005802c ...............................................558 hw_i2c_timing2 .................................................... 0x80058030 ................................................559 hw_i2c_timing2_clr ........................................... 0x80058038 ................................................559 hw_i2c_timing2_set ........................................... 0x80058034 ................................................559 hw_i2c_timing2_tog .......................................... 0x8005803c ...............................................559 hw_icoll_ctrl .................................................... 0x80000020 ..................................................79 hw_icoll_ctrl_clr ........................................... 0x80000028 ..................................................79 hw_icoll_ctrl_set ........................................... 0x80000024 ..................................................79 hw_icoll_ctrl_tog ........................................... 0x8000002c .................................................79 hw_icoll_dbgflag ............................................. 0x800001a0 ................................................113 hw_icoll_dbgflag_clr ................................... 0x800001a8 ................................................113 hw_icoll_dbgflag_set .................................... 0x800001a4 ................................................113 hw_icoll_dbgflag_tog ................................... 0x800001ac ...............................................113 hw_icoll_dbgread0 .......................................... 0x80000180 ................................................112 hw_icoll_dbgread0_clr ................................. 0x80000188 ................................................112 hw_icoll_dbgread0_set ................................. 0x80000184 ................................................112 hw_icoll_dbgread0_tog ................................ 0x8000018c ...............................................112 hw_icoll_dbgread1 .......................................... 0x80000190 ................................................112 hw_icoll_dbgread1_clr ................................. 0x80000198 ................................................112 hw_icoll_dbgread1_set ................................. 0x80000194 ................................................112 hw_icoll_dbgread1_tog ................................ 0x8000019c ...............................................112 hw_icoll_dbgrequest0 ................................... 0x800001b0 ................................................113 hw_icoll_dbgrequest0_clr ......................... 0x800001b8 ................................................113 hw_icoll_dbgrequest0_set .......................... 0x800001b4 ................................................113 hw_icoll_dbgrequest0_tog ......................... 0x800001bc ...............................................113 hw_icoll_dbgrequest1 ................................... 0x800001c0 ...............................................114 hw_icoll_dbgrequest1_clr ......................... 0x800001c8 ...............................................114 hw_icoll_dbgrequest1_set .......................... 0x800001c4 ...............................................114 hw_icoll_dbgrequest1_tog ......................... 0x800001cc ...............................................114 hw_icoll_debug ................................................. 0x80000170 ................................................110 hw_icoll_debug_clr ........................................ 0x80000178 ................................................110 hw_icoll_debug_set ........................................ 0x80000174 ................................................110 hw_icoll_debug_tog ....................................... 0x8000017c ...............................................110 hw_icoll_levelack ..... .............. .............. .......... 0x80000010 ..................................................78 hw_icoll_priority0 ........................................... 0x80000060 ..................................................83 hw_icoll_priority0_clr .................................. 0x80000068 ..................................................83 hw_icoll_priority0_set .................................. 0x80000064 ..................................................83 hw_icoll_priority0_tog ................................. 0x8000006c .................................................83 hw_icoll_priority1 ........................................... 0x80000070 ..................................................85 hw_icoll_priority1_clr .................................. 0x80000078 ..................................................85 hw_icoll_priority1_set .................................. 0x80000074 ..................................................85 hw_icoll_priority1_tog ................................. 0x8000007c .................................................85 hw_icoll_priority10 ......................................... 0x80000100 ................................................100 hw_icoll_priority10_clr ................................ 0x80000108 ................................................100 hw_icoll_priority10_set ................................ 0x80000104 ................................................100 hw_icoll_priority10_tog ............................... 0x8000010c ...............................................100 hw_icoll_priority11 ......................................... 0x80000110 ................................................101 hw_icoll_priority11_clr ................................ 0x80000118 ................................................101 hw_icoll_priority11_set ................................ 0x80000114 ................................................101 hw_icoll_priority11_tog ............................... 0x8000011c ...............................................101 hw_icoll_priority12 ......................................... 0x80000120 ................................................103 hw_icoll_priority12_clr ................................ 0x80000128 ................................................103 hw_icoll_priority12_set ................................ 0x80000124 ................................................103 hw_icoll_priority12_tog ............................... 0x8000012c ...............................................103 hw_icoll_priority13 ......................................... 0x80000130 ................................................105 hw_icoll_priority13_clr ................................ 0x80000138 ................................................105 hw_icoll_priority13_set ................................ 0x80000134 ................................................105 hw_icoll_priority13_tog ............................... 0x8000013c ...............................................105 hw_icoll_priority14 ......................................... 0x80000140 ................................................106 free datasheet http:/// STMP36XX official product documentation 5/3/06 860 index: register names 5-36xx-d1-1.02-050306 hw_icoll_priority14_clr ................................ 0x80000148 ................................................106 hw_icoll_priority14_set ................................ 0x80000144 ................................................106 hw_icoll_priority14_tog ............................... 0x8000014c ...............................................106 hw_icoll_priority15 ......................................... 0x80000150 ................................................108 hw_icoll_priority15_clr ................................ 0x80000158 ................................................108 hw_icoll_priority15_set ................................ 0x80000154 ................................................108 hw_icoll_priority15_tog ............................... 0x8000015c ...............................................108 hw_icoll_priority2 ........................................... 0x80000080 ..................................................86 hw_icoll_priority2_clr .................................. 0x80000088 ..................................................86 hw_icoll_priority2_set .................................. 0x80000084 ..................................................86 hw_icoll_priority2_tog ................................. 0x8000008c .................................................86 hw_icoll_priority3 ........................................... 0x80000090 ..................................................88 hw_icoll_priority3_clr .................................. 0x80000098 ..................................................88 hw_icoll_priority3_set .................................. 0x80000094 ..................................................88 hw_icoll_priority3_tog ................................. 0x8000009c .................................................88 hw_icoll_priority4 ........................................... 0x800000a0 ..................................................90 hw_icoll_priority4_clr .................................. 0x800000a8 ..................................................90 hw_icoll_priority4_set .................................. 0x800000a4 ..................................................90 hw_icoll_priority4_tog ................................. 0x800000ac .................................................90 hw_icoll_priority5 ........................................... 0x800000b0 ..................................................91 hw_icoll_priority5_clr .................................. 0x800000b8 ..................................................91 hw_icoll_priority5_set .................................. 0x800000b4 ..................................................91 hw_icoll_priority5_tog ................................. 0x800000bc .................................................91 hw_icoll_priority6 ........................................... 0x800000c0 .................................................93 hw_icoll_priority6_clr .................................. 0x800000c8 .................................................93 hw_icoll_priority6_set .................................. 0x800000c4 .................................................93 hw_icoll_priority6_tog ................................. 0x800000cc .................................................93 hw_icoll_priority7 ........................................... 0x800000d0 .................................................95 hw_icoll_priority7_clr .................................. 0x800000d8 .................................................95 hw_icoll_priority7_set .................................. 0x800000d4 .................................................95 hw_icoll_priority7_tog ................................. 0x800000dc .................................................95 hw_icoll_priority8 ........................................... 0x800000e0 ..................................................96 hw_icoll_priority8_clr .................................. 0x800000e8 ..................................................96 hw_icoll_priority8_set .................................. 0x800000e4 ..................................................96 hw_icoll_priority8_tog ................................. 0x800000ec .................................................96 hw_icoll_priority9 ........................................... 0x800000f0 ..................................................98 hw_icoll_priority9_clr .................................. 0x800000f8 ..................................................98 hw_icoll_priority9_set .................................. 0x800000f4 ..................................................98 hw_icoll_priority9_tog ................................. 0x800000fc .................................................98 hw_icoll_raw0 ................................................... 0x80000040 ..................................................82 hw_icoll_raw0_clr .......................................... 0x80000048 ..................................................82 hw_icoll_raw0_set .......................................... 0x80000044 ..................................................82 hw_icoll_raw0_tog .......................................... 0x8000004c .................................................82 hw_icoll_raw1 ................................................... 0x80000050 ..................................................83 hw_icoll_raw1_clr .......................................... 0x80000058 ..................................................83 hw_icoll_raw1_set .......................................... 0x80000054 ..................................................83 hw_icoll_raw1_tog .......................................... 0x8000005c .................................................83 hw_icoll_stat ..................................................... 0x80000030 ..................................................81 hw_icoll_vbase ......... .............. .............. ............. 0x80000160 ................................................110 hw_icoll_vbase_clr ... .............. .............. .......... 0x80000168 ................................................110 hw_icoll_vbase_set ... .............. .............. .......... 0x80000164 ................................................110 hw_icoll_vbase_tog .. .............. .............. .......... 0x8000016c ...............................................110 hw_icoll_vector ............................................... 0x80000000 ..................................................78 hw_icoll_vector_clr ...................................... 0x80000008 ..................................................78 hw_icoll_vector_set ...................................... 0x80000004 ..................................................78 hw_icoll_vector_tog ..................................... 0x8000000c .................................................78 hw_ir_ctrl ........................................................... 0x80078000 ................................................611 hw_ir_ctrl_clr .................................................. 0x80078008 ................................................611 hw_ir_ctrl_set .................................................. 0x80078004 ................................................611 hw_ir_ctrl_tog ................................................. 0x8007800c ...............................................611 hw_ir_data ........................................................... 0x80078050 ................................................617 hw_ir_dbgctrl ................................................... 0x80078030 ................................................614 hw_ir_dbgctrl_clr .......................................... 0x80078038 ................................................614 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 861 hw_ir_dbgctrl_set .......................................... 0x80078034 ................................................614 hw_ir_dbgctrl_tog .......................................... 0x8007803c ...............................................614 hw_ir_debug ........................................................ 0x80078090 ................................................621 hw_ir_intr ............................................................ 0x80078040 ................................................615 hw_ir_intr_clr ................................................... 0x80078048 ................................................615 hw_ir_intr_set ................................................... 0x80078044 ................................................615 hw_ir_intr_tog .................................................. 0x8007804c ...............................................615 hw_ir_rxdma ........................................................ 0x80078020 ................................................613 hw_ir_rxdma_clr .............................................. 0x80078028 ................................................613 hw_ir_rxdma_set ............................................... 0x80078024 ................................................613 hw_ir_rxdma_tog .............................................. 0x8007802c ...............................................613 hw_ir_si_read ..................................................... 0x80078080 ................................................620 hw_ir_stat ........................................................... 0x80078060 ................................................618 hw_ir_tcctrl ...................................................... 0x80078070 ................................................619 hw_ir_tcctrl_clr ............................................. 0x80078078 ................................................619 hw_ir_tcctrl_set ............................................. 0x80078074 ................................................619 hw_ir_tcctrl_tog ............................................. 0x8007807c ...............................................619 hw_ir_txdma ........................................................ 0x80078010 ................................................612 hw_ir_txdma_clr ............................................... 0x80078018 ................................................612 hw_ir_txdma_set ............................................... 0x80078014 ................................................612 hw_ir_txdma_tog .............................................. 0x8007801c ...............................................612 hw_lcdif_ctrl .................................................... 0x80060000 ................................................423 hw_lcdif_ctrl_clr ........................................... 0x80060008 ................................................423 hw_lcdif_ctrl_set ........................................... 0x80060004 ................................................423 hw_lcdif_ctrl_tog ........................................... 0x8006000c ...............................................423 hw_lcdif_data .................................................... 0x80060020 ................................................425 hw_lcdif_debug ................................................. 0x80060030 ................................................426 hw_lcdif_timing ................................................. 0x80060010 ................................................425 hw_lradc_ch0 ..................................................... 0x80050050 ................................................721 hw_lradc_ch0_clr ............................................ 0x80050058 ................................................721 hw_lradc_ch0_set ............................................ 0x80050054 ................................................721 hw_lradc_ch0_tog ........................................... 0x8005005c ...............................................721 hw_lradc_ch1 ..................................................... 0x80050060 ................................................722 hw_lradc_ch1_clr ............................................ 0x80050068 ................................................722 hw_lradc_ch1_set ............................................ 0x80050064 ................................................722 hw_lradc_ch1_tog ........................................... 0x8005006c ...............................................722 hw_lradc_ch2 ..................................................... 0x80050070 ................................................723 hw_lradc_ch2_clr ............................................ 0x80050078 ................................................723 hw_lradc_ch2_set ............................................ 0x80050074 ................................................723 hw_lradc_ch2_tog ........................................... 0x8005007c ...............................................723 hw_lradc_ch3 ..................................................... 0x80050080 ................................................724 hw_lradc_ch3_clr ............................................ 0x80050088 ................................................724 hw_lradc_ch3_set ............................................ 0x80050084 ................................................724 hw_lradc_ch3_tog ........................................... 0x8005008c ...............................................724 hw_lradc_ch4 ..................................................... 0x80050090 ................................................726 hw_lradc_ch4_clr ............................................ 0x80050098 ................................................726 hw_lradc_ch4_set ............................................ 0x80050094 ................................................726 hw_lradc_ch4_tog ........................................... 0x8005009c ...............................................726 hw_lradc_ch5 ..................................................... 0x800500a0 ................................................727 hw_lradc_ch5_clr ............................................ 0x800500a8 ................................................727 hw_lradc_ch5_set ............................................ 0x800500a4 ................................................727 hw_lradc_ch5_tog ........................................... 0x800500ac ...............................................727 hw_lradc_ch6 ..................................................... 0x800500b0 ................................................728 hw_lradc_ch6_clr ............................................ 0x800500b8 ................................................728 hw_lradc_ch6_set ............................................ 0x800500b4 ................................................728 hw_lradc_ch6_tog ........................................... 0x800500bc ...............................................728 hw_lradc_ch7 ..................................................... 0x800500c0 ...............................................729 hw_lradc_ch7_clr ............................................ 0x800500c8 ...............................................729 hw_lradc_ch7_set ............................................ 0x800500c4 ...............................................729 hw_lradc_ch7_tog ........................................... 0x800500cc ...............................................729 hw_lradc_conversion .................................... 0x80050130 ................................................739 hw_lradc_conversion_clr ........................... 0x80050138 ................................................739 hw_lradc_conversion_set ........................... 0x80050134 ................................................739 free datasheet http:/// STMP36XX official product documentation 5/3/06 862 index: register names 5-36xx-d1-1.02-050306 hw_lradc_conversion_tog .......................... 0x8005013c ...............................................739 hw_lradc_ctrl0 ................................................. 0x80050000 ................................................710 hw_lradc_ctrl0_clr ....................................... 0x80050008 ................................................710 hw_lradc_ctrl0_set ........................................ 0x80050004 ................................................710 hw_lradc_ctrl0_tog ....................................... 0x8005000c ...............................................710 hw_lradc_ctrl1 ................................................. 0x80050010 ................................................711 hw_lradc_ctrl1_clr ....................................... 0x80050018 ................................................711 hw_lradc_ctrl1_set ........................................ 0x80050014 ................................................711 hw_lradc_ctrl1_tog ....................................... 0x8005001c ...............................................711 hw_lradc_ctrl2 ................................................. 0x80050020 ................................................714 hw_lradc_ctrl2_clr ....................................... 0x80050028 ................................................714 hw_lradc_ctrl2_set ........................................ 0x80050024 ................................................714 hw_lradc_ctrl2_tog ....................................... 0x8005002c ...............................................714 hw_lradc_ctrl3 ................................................. 0x80050030 ................................................717 hw_lradc_ctrl3_clr ....................................... 0x80050038 ................................................717 hw_lradc_ctrl3_set ........................................ 0x80050034 ................................................717 hw_lradc_ctrl3_tog ....................................... 0x8005003c ...............................................717 hw_lradc_debug0 ............................................. 0x80050110 ................................................737 hw_lradc_debug0_clr .................................... 0x80050118 ................................................737 hw_lradc_debug0_set .................................... 0x80050114 ................................................737 hw_lradc_debug0_tog ................................... 0x8005011c ...............................................737 hw_lradc_debug1 ............................................. 0x80050120 ................................................738 hw_lradc_debug1_clr .................................... 0x80050128 ................................................738 hw_lradc_debug1_set .................................... 0x80050124 ................................................738 hw_lradc_debug1_tog ................................... 0x8005012c ...............................................738 hw_lradc_delay0 .............................................. 0x800500d0 ...............................................731 hw_lradc_delay0_clr ..................................... 0x800500d8 ...............................................731 hw_lradc_delay0_set ..................................... 0x800500d4 ...............................................731 hw_lradc_delay0_tog .................................... 0x800500dc ...............................................731 hw_lradc_delay1 .............................................. 0x800500e0 ................................................732 hw_lradc_delay1_clr ..................................... 0x800500e8 ................................................732 hw_lradc_delay1_set ..................................... 0x800500e4 ................................................732 hw_lradc_delay1_tog .................................... 0x800500ec ...............................................732 hw_lradc_delay2 .............................................. 0x800500f0 ................................................734 hw_lradc_delay2_clr ..................................... 0x800500f8 ................................................734 hw_lradc_delay2_set ..................................... 0x800500f4 ................................................734 hw_lradc_delay2_tog .................................... 0x800500fc ...............................................734 hw_lradc_delay3 .............................................. 0x80050100 ................................................735 hw_lradc_delay3_clr ..................................... 0x80050108 ................................................735 hw_lradc_delay3_set ..................................... 0x80050104 ................................................735 hw_lradc_delay3_tog .................................... 0x8005010c ...............................................735 hw_lradc_status .............................................. 0x80050040 ................................................719 hw_lradc_status_clr ..................................... 0x80050048 ................................................719 hw_lradc_status_set ..................................... 0x80050044 ................................................719 hw_lradc_status_tog .................................... 0x8005004c ...............................................719 hw_memcpy_ctrl ............................................... 0x80014000 ................................................744 hw_memcpy_ctrl_clr ...................................... 0x80014008 ................................................744 hw_memcpy_ctrl_set ...................................... 0x80014004 ................................................744 hw_memcpy_ctrl_tog ..................................... 0x8001400c ...............................................744 hw_memcpy_data ............................................... 0x80014010 ................................................745 hw_memcpy_data_clr ...................................... 0x80014018 ................................................745 hw_memcpy_data_set ...................................... 0x80014014 ................................................745 hw_memcpy_data_tog ..................................... 0x8001401c ...............................................745 hw_memcpy_debug ............................................ 0x80014020 ................................................746 hw_memcpy_debug_clr .................................. 0x80014028 ................................................746 hw_memcpy_debug_set ................................... 0x80014024 ................................................746 hw_memcpy_debug_tog .................................. 0x8001402c ...............................................746 hw_pinctrl_ctrl ............................................... 0x80018000 ................................................439 hw_pinctrl_ctrl_clr ...................................... 0x80018008 ................................................439 hw_pinctrl_ctrl_set ...................................... 0x80018004 ................................................439 hw_pinctrl_ctrl_tog ...................................... 0x8001800c ...............................................439 hw_pinctrl_din0 ................................................. 0x80018060 ................................................443 hw_pinctrl_din0_clr ....................................... 0x80018068 ................................................443 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 863 hw_pinctrl_din0_set ........................................ 0x80018064 ................................................443 hw_pinctrl_din0_tog ....................................... 0x8001806c ...............................................443 hw_pinctrl_din1 ................................................. 0x80018160 ................................................451 hw_pinctrl_din1_clr ....................................... 0x80018168 ................................................451 hw_pinctrl_din1_set ........................................ 0x80018164 ................................................451 hw_pinctrl_din1_tog ....................................... 0x8001816c ...............................................451 hw_pinctrl_din2 ................................................. 0x80018260 ................................................459 hw_pinctrl_din2_clr ....................................... 0x80018268 ................................................459 hw_pinctrl_din2_set ........................................ 0x80018264 ................................................459 hw_pinctrl_din2_tog ....................................... 0x8001826c ...............................................459 hw_pinctrl_din3 ................................................. 0x80018360 ................................................468 hw_pinctrl_din3_clr ....................................... 0x80018368 ................................................468 hw_pinctrl_din3_set ........................................ 0x80018364 ................................................468 hw_pinctrl_din3_tog ....................................... 0x8001836c ...............................................468 hw_pinctrl_doe0 ............................................... 0x80018070 ................................................443 hw_pinctrl_doe0_clr ...................................... 0x80018078 ................................................443 hw_pinctrl_doe0_set ...................................... 0x80018074 ................................................443 hw_pinctrl_doe0_tog ..................................... 0x8001807c ...............................................443 hw_pinctrl_doe1 ............................................... 0x80018170 ................................................452 hw_pinctrl_doe1_clr ...................................... 0x80018178 ................................................452 hw_pinctrl_doe1_set ...................................... 0x80018174 ................................................452 hw_pinctrl_doe1_tog ..................................... 0x8001817c ...............................................452 hw_pinctrl_doe2 ............................................... 0x80018270 ................................................460 hw_pinctrl_doe2_clr ...................................... 0x80018278 ................................................460 hw_pinctrl_doe2_set ...................................... 0x80018274 ................................................460 hw_pinctrl_doe2_tog ..................................... 0x8001827c ...............................................460 hw_pinctrl_doe3 ............................................... 0x80018370 ................................................469 hw_pinctrl_doe3_clr ...................................... 0x80018378 ................................................469 hw_pinctrl_doe3_set ...................................... 0x80018374 ................................................469 hw_pinctrl_doe3_tog ..................................... 0x8001837c ...............................................469 hw_pinctrl_dout0 ............................................. 0x80018050 ................................................442 hw_pinctrl_dout0_clr ................................... 0x80018058 ................................................442 hw_pinctrl_dout0_set .................................... 0x80018054 ................................................442 hw_pinctrl_dout0_tog ................................... 0x8001805c ...............................................442 hw_pinctrl_dout1 ............................................. 0x80018150 ................................................450 hw_pinctrl_dout1_clr ................................... 0x80018158 ................................................450 hw_pinctrl_dout1_set .................................... 0x80018154 ................................................450 hw_pinctrl_dout1_tog ................................... 0x8001815c ...............................................450 hw_pinctrl_dout2 ............................................. 0x80018250 ................................................459 hw_pinctrl_dout2_clr ................................... 0x80018258 ................................................459 hw_pinctrl_dout2_set .................................... 0x80018254 ................................................459 hw_pinctrl_dout2_tog ................................... 0x8001825c ...............................................459 hw_pinctrl_dout3 ............................................. 0x80018350 ................................................467 hw_pinctrl_dout3_clr ................................... 0x80018358 ................................................467 hw_pinctrl_dout3_set .................................... 0x80018354 ................................................467 hw_pinctrl_dout3_tog ................................... 0x8001835c ...............................................467 hw_pinctrl_drive0 ............................................ 0x80018030 ................................................441 hw_pinctrl_drive0_clr ................................... 0x80018038 ................................................441 hw_pinctrl_drive0_set ................................... 0x80018034 ................................................441 hw_pinctrl_drive0_tog .................................. 0x8001803c ...............................................442 hw_pinctrl_drive1 ............................................ 0x80018130 ................................................449 hw_pinctrl_drive1_clr ................................... 0x80018138 ................................................449 hw_pinctrl_drive1_set ................................... 0x80018134 ................................................449 hw_pinctrl_drive1_tog .................................. 0x8001813c ...............................................449 hw_pinctrl_drive2 ............................................ 0x80018230 ................................................458 hw_pinctrl_drive2_clr ................................... 0x80018238 ................................................458 hw_pinctrl_drive2_set ................................... 0x80018234 ................................................458 hw_pinctrl_drive2_tog .................................. 0x8001823c ...............................................458 hw_pinctrl_drive3 ............................................ 0x80018330 ................................................466 hw_pinctrl_drive3_clr ................................... 0x80018338 ................................................466 hw_pinctrl_drive3_set ................................... 0x80018334 ................................................466 hw_pinctrl_drive3_tog .................................. 0x8001833c ...............................................466 hw_pinctrl_irqen0 ........................................... 0x80018090 ................................................445 free datasheet http:/// STMP36XX official product documentation 5/3/06 864 index: register names 5-36xx-d1-1.02-050306 hw_pinctrl_irqen0_clr .................................. 0x80018098 ................................................445 hw_pinctrl_irqen0_set .................................. 0x80018094 ................................................445 hw_pinctrl_irqen0_tog .................................. 0x8001809c ...............................................445 hw_pinctrl_irqen1 ........................................... 0x80018190 ................................................453 hw_pinctrl_irqen1_clr .................................. 0x80018198 ................................................453 hw_pinctrl_irqen1_set .................................. 0x80018194 ................................................453 hw_pinctrl_irqen1_tog .................................. 0x8001819c ...............................................453 hw_pinctrl_irqen2 ........................................... 0x80018290 ................................................461 hw_pinctrl_irqen2_clr .................................. 0x80018298 ................................................461 hw_pinctrl_irqen2_set .................................. 0x80018294 ................................................461 hw_pinctrl_irqen2_tog .................................. 0x8001829c ...............................................461 hw_pinctrl_irqen3 ........................................... 0x80018390 ................................................470 hw_pinctrl_irqen3_clr .................................. 0x80018398 ................................................470 hw_pinctrl_irqen3_set .................................. 0x80018394 ................................................470 hw_pinctrl_irqen3_tog .................................. 0x8001839c ...............................................470 hw_pinctrl_irqlevel0 ..................................... 0x800180a0 ................................................446 hw_pinctrl_irqlevel0_clr ............................ 0x800180a8 ................................................446 hw_pinctrl_irqlevel0_set ............................ 0x800180a4 ................................................446 hw_pinctrl_irqlevel0_tog ........................... 0x800180ac ...............................................446 hw_pinctrl_irqlevel1 ..................................... 0x800181a0 ................................................454 hw_pinctrl_irqlevel1_clr ............................ 0x800181a8 ................................................454 hw_pinctrl_irqlevel1_set ............................ 0x800181a4 ................................................454 hw_pinctrl_irqlevel1_tog ........................... 0x800181ac ...............................................454 hw_pinctrl_irqlevel2 ..................................... 0x800182a0 ................................................462 hw_pinctrl_irqlevel2_clr ............................ 0x800182a8 ................................................462 hw_pinctrl_irqlevel2_set ............................ 0x800182a4 ................................................462 hw_pinctrl_irqlevel2_tog ........................... 0x800182ac ...............................................462 hw_pinctrl_irqlevel3 ..................................... 0x800183a0 ................................................471 hw_pinctrl_irqlevel3_clr ............................ 0x800183a8 ................................................471 hw_pinctrl_irqlevel3_set ............................ 0x800183a4 ................................................471 hw_pinctrl_irqlevel3_tog ........................... 0x800183ac ...............................................471 hw_pinctrl_irqpol0 ......................................... 0x800180b0 ................................................446 hw_pinctrl_irqpol0_clr ................................ 0x800180b8 ................................................446 hw_pinctrl_irqpol0_set ................................ 0x800180b4 ................................................446 hw_pinctrl_irqpol0_tog ............................... 0x800180bc ...............................................446 hw_pinctrl_irqpol1 ......................................... 0x800181b0 ................................................455 hw_pinctrl_irqpol1_clr ................................ 0x800181b8 ................................................455 hw_pinctrl_irqpol1_set ................................ 0x800181b4 ................................................455 hw_pinctrl_irqpol1_tog ............................... 0x800181bc ...............................................455 hw_pinctrl_irqpol2 ......................................... 0x800182b0 ................................................463 hw_pinctrl_irqpol2_clr ................................ 0x800182b8 ................................................463 hw_pinctrl_irqpol2_set ................................ 0x800182b4 ................................................463 hw_pinctrl_irqpol2_tog ............................... 0x800182bc ...............................................463 hw_pinctrl_irqpol3 ......................................... 0x800183b0 ................................................472 hw_pinctrl_irqpol3_clr ................................ 0x800183b8 ................................................472 hw_pinctrl_irqpol3_set ................................ 0x800183b4 ................................................472 hw_pinctrl_irqpol3_tog ............................... 0x800183bc ...............................................472 hw_pinctrl_irqstat0 ....................................... 0x800180c0 ...............................................447 hw_pinctrl_irqstat0_clr .............................. 0x800180c8 ...............................................447 hw_pinctrl_irqstat0_set .............................. 0x800180c4 ...............................................447 hw_pinctrl_irqstat0_tog ............................. 0x800180cc ...............................................447 hw_pinctrl_irqstat1 ....................................... 0x800181c0 ...............................................456 hw_pinctrl_irqstat1_clr .............................. 0x800181c8 ...............................................456 hw_pinctrl_irqstat1_set .............................. 0x800181c4 ...............................................456 hw_pinctrl_irqstat1_tog ............................. 0x800181cc ...............................................456 hw_pinctrl_irqstat2 ....................................... 0x800182c0 ...............................................463 hw_pinctrl_irqstat2_clr .............................. 0x800182c8 ...............................................463 hw_pinctrl_irqstat2_set .............................. 0x800182c4 ...............................................463 hw_pinctrl_irqstat2_tog ............................. 0x800182cc ...............................................463 hw_pinctrl_irqstat3 ....................................... 0x800183c0 ...............................................473 hw_pinctrl_irqstat3_clr .............................. 0x800183c8 ...............................................473 hw_pinctrl_irqstat3_set .............................. 0x800183c4 ...............................................473 hw_pinctrl_irqstat3_tog ............................. 0x800183cc ...............................................473 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 865 hw_pinctrl_muxsel0 .. .............. .............. .......... 0x80018010 ................................................440 hw_pinctrl_muxsel0_c lr .......... ........... .......... 0x80018018 ................................................440 hw_pinctrl_muxsel0_ set .......... ........... .......... 0x80018014 ................................................440 hw_pinctrl_muxsel0_tog ...... .............. .......... 0x8001801c ...............................................440 hw_pinctrl_muxsel1 .. .............. .............. .......... 0x80018020 ................................................441 hw_pinctrl_muxsel1_c lr .......... ........... .......... 0x80018028 ................................................441 hw_pinctrl_muxsel1_ set .......... ........... .......... 0x80018024 ................................................441 hw_pinctrl_muxsel1_tog ...... .............. .......... 0x8001802c ...............................................441 hw_pinctrl_muxsel2 .. .............. .............. .......... 0x80018110 ................................................448 hw_pinctrl_muxsel2_c lr .......... ........... .......... 0x80018118 ................................................448 hw_pinctrl_muxsel2_ set .......... ........... .......... 0x80018114 ................................................448 hw_pinctrl_muxsel2_tog ...... .............. .......... 0x8001811c ...............................................448 hw_pinctrl_muxsel3 .. .............. .............. .......... 0x80018120 ................................................448 hw_pinctrl_muxsel3_c lr .......... ........... .......... 0x80018128 ................................................449 hw_pinctrl_muxsel3_ set .......... ........... .......... 0x80018124 ................................................449 hw_pinctrl_muxsel3_tog ...... .............. .......... 0x8001812c ...............................................449 hw_pinctrl_muxsel4 .. .............. .............. .......... 0x80018210 ................................................456 hw_pinctrl_muxsel4_c lr .......... ........... .......... 0x80018218 ................................................456 hw_pinctrl_muxsel4_ set .......... ........... .......... 0x80018214 ................................................456 hw_pinctrl_muxsel4_tog ...... .............. .......... 0x8001821c ...............................................457 hw_pinctrl_muxsel5 .. .............. .............. .......... 0x80018220 ................................................457 hw_pinctrl_muxsel5_c lr .......... ........... .......... 0x80018228 ................................................457 hw_pinctrl_muxsel5_ set .......... ........... .......... 0x80018224 ................................................457 hw_pinctrl_muxsel5_tog ...... .............. .......... 0x8001822c ...............................................457 hw_pinctrl_muxsel6 .. .............. .............. .......... 0x80018310 ................................................464 hw_pinctrl_muxsel6_c lr .......... ........... .......... 0x80018318 ................................................464 hw_pinctrl_muxsel6_ set .......... ........... .......... 0x80018314 ................................................464 hw_pinctrl_muxsel6_tog ...... .............. .......... 0x8001831c ...............................................464 hw_pinctrl_muxsel7 .. .............. .............. .......... 0x80018320 ................................................465 hw_pinctrl_muxsel7_c lr .......... ........... .......... 0x80018328 ................................................465 hw_pinctrl_muxsel7_ set .......... ........... .......... 0x80018324 ................................................465 hw_pinctrl_muxsel7_tog ...... .............. .......... 0x8001832c ...............................................465 hw_pinctrl_pin2irq0 ........................................ 0x80018080 ................................................444 hw_pinctrl_pin2irq0_clr ............................... 0x80018088 ................................................444 hw_pinctrl_pin2irq0_set ............................... 0x80018084 ................................................444 hw_pinctrl_pin2irq0_tog ............................... 0x8001808c ...............................................444 hw_pinctrl_pin2irq1 ........................................ 0x80018180 ................................................452 hw_pinctrl_pin2irq1_clr ............................... 0x80018188 ................................................453 hw_pinctrl_pin2irq1_set ............................... 0x80018184 ................................................452 hw_pinctrl_pin2irq1_tog ............................... 0x8001818c ...............................................453 hw_pinctrl_pin2irq2 ........................................ 0x80018280 ................................................461 hw_pinctrl_pin2irq2_clr ............................... 0x80018288 ................................................461 hw_pinctrl_pin2irq2_set ............................... 0x80018284 ................................................461 hw_pinctrl_pin2irq2_tog ............................... 0x8001828c ...............................................461 hw_pinctrl_pin2irq3 ........................................ 0x80018380 ................................................469 hw_pinctrl_pin2irq3_clr ............................... 0x80018388 ................................................469 hw_pinctrl_pin2irq3_set ............................... 0x80018384 ................................................469 hw_pinctrl_pin2irq3_tog ............................... 0x8001838c ...............................................469 hw_power_5vctrl ............................................. 0x80044010 ................................................760 hw_power_5vctrl_clr .................................... 0x80044018 ................................................760 hw_power_5vctrl_set .................................... 0x80044014 ................................................760 hw_power_5vctrl_tog ................................... 0x8004401c ...............................................760 hw_power_battchrg ....................................... 0x80044030 ................................................765 hw_power_battchrg_clr .............................. 0x80044038 ................................................765 hw_power_battchrg_set .............................. 0x80044034 ................................................765 hw_power_battchrg_tog ............................. 0x8004403c ...............................................765 hw_power_battmonitor ................................ 0x800440b0 ................................................777 hw_power_ctrl ................................................. 0x80044000 ................................................759 hw_power_ctrl_clr ........................................ 0x80044008 ................................................759 hw_power_ctrl_set ........................................ 0x80044004 ................................................759 hw_power_ctrl_tog ....................................... 0x8004400c ...............................................759 hw_power_dc1limits ........................................ 0x80044060 ................................................770 hw_power_dc1multout .................................. 0x80044050 ................................................768 free datasheet http:/// STMP36XX official product documentation 5/3/06 866 index: register names 5-36xx-d1-1.02-050306 hw_power_dc2limits ........................................ 0x80044070 ................................................770 hw_power_debug .............................................. 0x800440d0 ................................................779 hw_power_debug_clr ..................................... 0x800440d8 ................................................779 hw_power_debug_set ..................................... 0x800440d4 ................................................779 hw_power_debug_tog .................................... 0x800440dc ...............................................779 hw_power_loopctrl ....................................... 0x80044080 ................................................771 hw_power_loopctrl_clr .............................. 0x80044088 ................................................771 hw_power_loopctrl_set .............................. 0x80044084 ................................................771 hw_power_loopctrl_tog ............................. 0x8004408c ...............................................771 hw_power_minpwr ............................................ 0x80044020 ................................................763 hw_power_minpwr_clr .................................. 0x80044028 ................................................763 hw_power_minpwr_set ................................... 0x80044024 ................................................763 hw_power_minpwr_tog .................................. 0x8004402c ...............................................763 hw_power_reset ...... .............. .............. ............. 0x800440c0 ................................................778 hw_power_reset_clr .. .............. .............. ....... 0x800440c8 ...............................................778 hw_power_reset_set ... .............. .............. ....... 0x800440c4 ...............................................778 hw_power_reset_tog .. .............. .............. ....... 0x800440cc ...............................................778 hw_power_speedtemp .................................... 0x800440a0 ................................................775 hw_power_speedtemp_clr ........................... 0x800440a8 ................................................775 hw_power_speedtemp_set ........................... 0x800440a4 ................................................775 hw_power_speedtemp_tog ........................... 0x800440ac ...............................................775 hw_power_sts .................................................... 0x80044090 ................................................773 hw_power_vddctrl .......................................... 0x80044040 ................................................766 hw_pwm_active0 ................................................ 0x80064010 ................................................528 hw_pwm_active0_clr ....................................... 0x80064018 ................................................528 hw_pwm_active0_set ....................................... 0x80064014 ................................................528 hw_pwm_active0_tog ....................................... 0x8006401c ...............................................528 hw_pwm_active1 ................................................ 0x80064030 ................................................530 hw_pwm_active1_clr ....................................... 0x80064038 ................................................530 hw_pwm_active1_set ....................................... 0x80064034 ................................................530 hw_pwm_active1_tog ....................................... 0x8006403c ...............................................530 hw_pwm_active2 ................................................ 0x80064050 ................................................532 hw_pwm_active2_clr ....................................... 0x80064058 ................................................532 hw_pwm_active2_set ....................................... 0x80064054 ................................................532 hw_pwm_active2_tog ....................................... 0x8006405c ...............................................532 hw_pwm_active3 ................................................ 0x80064070 ................................................534 hw_pwm_active3_clr ....................................... 0x80064078 ................................................534 hw_pwm_active3_set ....................................... 0x80064074 ................................................534 hw_pwm_active3_tog ....................................... 0x8006407c ...............................................534 hw_pwm_active4 ................................................ 0x80064090 ................................................536 hw_pwm_active4_clr ....................................... 0x80064098 ................................................536 hw_pwm_active4_set ....................................... 0x80064094 ................................................536 hw_pwm_active4_tog ....................................... 0x8006409c ...............................................536 hw_pwm_ctrl ...................................................... 0x80064000 ................................................527 hw_pwm_ctrl_clr ............................................. 0x80064008 ................................................527 hw_pwm_ctrl_set ............................................. 0x80064004 ................................................527 hw_pwm_ctrl_tog ............................................ 0x8006400c ...............................................527 hw_pwm_period0 ................................................ 0x80064020 ................................................529 hw_pwm_period0_clr ...................................... 0x80064028 ................................................529 hw_pwm_period0_set ....................................... 0x80064024 ................................................529 hw_pwm_period0_tog ...................................... 0x8006402c ...............................................529 hw_pwm_period1 ................................................ 0x80064040 ................................................531 hw_pwm_period1_clr ...................................... 0x80064048 ................................................531 hw_pwm_period1_set ....................................... 0x80064044 ................................................531 hw_pwm_period1_tog ...................................... 0x8006404c ...............................................531 hw_pwm_period2 ................................................ 0x80064060 ................................................533 hw_pwm_period2_clr ...................................... 0x80064068 ................................................533 hw_pwm_period2_set ....................................... 0x80064064 ................................................533 hw_pwm_period2_tog ...................................... 0x8006406c ...............................................533 hw_pwm_period3 ................................................ 0x80064080 ................................................535 hw_pwm_period3_clr ...................................... 0x80064088 ................................................535 hw_pwm_period3_set ....................................... 0x80064084 ................................................535 hw_pwm_period3_tog ...................................... 0x8006408c ...............................................535 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 867 hw_pwm_period4 ................................................ 0x800640a0 ................................................537 hw_pwm_period4_clr ...................................... 0x800640a8 ................................................537 hw_pwm_period4_set ....................................... 0x800640a4 ................................................537 hw_pwm_period4_tog ...................................... 0x800640ac ...............................................537 hw_rtc_alarm .................................................... 0x8005c040 ...............................................508 hw_rtc_alarm_clr ........................................... 0x8005c048 ...............................................508 hw_rtc_alarm_set ........................................... 0x8005c044 ...............................................508 hw_rtc_alarm_tog ........................................... 0x8005c04c ...............................................508 hw_rtc_ctrl ....................................................... 0x8005c000 ...............................................503 hw_rtc_ctrl_clr .............................................. 0x8005c008 ...............................................503 hw_rtc_ctrl_set .............................................. 0x8005c004 ...............................................503 hw_rtc_ctrl_tog .............................................. 0x8005c00c ...............................................503 hw_rtc_debug .................................................... 0x8005c0a0 ...............................................513 hw_rtc_debug_clr ........................................... 0x8005c0a8 ...............................................513 hw_rtc_debug_set ........................................... 0x8005c0a4 ...............................................513 hw_rtc_debug_tog .......................................... 0x8005c0ac ..............................................513 hw_rtc_laserfuse0 ...... .............. .............. ....... 0x8005c300 ...............................................515 hw_rtc_laserfuse0_clr .............. ........... ....... 0x8005c308 ...............................................515 hw_rtc_laserfuse0_set .............. ........... ....... 0x8005c304 ...............................................515 hw_rtc_laserfuse0_tog .............. ........... ....... 0x8005c30c ...............................................515 hw_rtc_laserfuse1 ...... .............. .............. ....... 0x8005c310 ...............................................516 hw_rtc_laserfuse1_clr .............. ........... ....... 0x8005c318 ...............................................516 hw_rtc_laserfuse1_set .............. ........... ....... 0x8005c314 ...............................................516 hw_rtc_laserfuse1_tog .............. ........... ....... 0x8005c31c ...............................................516 hw_rtc_laserfuse10 .... .............. .............. ....... 0x8005c3a0 ...............................................521 hw_rtc_laserfuse10_clr .............. ............ .... 0x8005c3a8 ...............................................521 hw_rtc_laserfuse10_set .............. ............ .... 0x8005c3a4 ...............................................521 hw_rtc_laserfuse10_tog ......... .............. ....... 0x8005c3ac ..............................................521 hw_rtc_laserfuse11 .... .............. .............. ....... 0x8005c3b0 ...............................................521 hw_rtc_laserfuse11_clr .............. ............ .... 0x8005c3b8 ...............................................521 hw_rtc_laserfuse11_set .............. ............ .... 0x8005c3b4 ...............................................521 hw_rtc_laserfuse11_tog ......... .............. ....... 0x8005c3bc ..............................................522 hw_rtc_laserfuse2 ...... .............. .............. ....... 0x8005c320 ...............................................516 hw_rtc_laserfuse2_clr .............. ........... ....... 0x8005c328 ...............................................516 hw_rtc_laserfuse2_set .............. ........... ....... 0x8005c324 ...............................................516 hw_rtc_laserfuse2_tog .............. ........... ....... 0x8005c32c ...............................................516 hw_rtc_laserfuse3 ...... .............. .............. ....... 0x8005c330 ...............................................517 hw_rtc_laserfuse3_clr .............. ........... ....... 0x8005c338 ...............................................517 hw_rtc_laserfuse3_set .............. ........... ....... 0x8005c334 ...............................................517 hw_rtc_laserfuse3_tog .............. ........... ....... 0x8005c33c ...............................................517 hw_rtc_laserfuse4 ...... .............. .............. ....... 0x8005c340 ...............................................517 hw_rtc_laserfuse4_clr .............. ........... ....... 0x8005c348 ...............................................517 hw_rtc_laserfuse4_set .............. ........... ....... 0x8005c344 ...............................................517 hw_rtc_laserfuse4_tog .............. ........... ....... 0x8005c34c ...............................................517 hw_rtc_laserfuse5 ...... .............. .............. ....... 0x8005c350 ...............................................518 hw_rtc_laserfuse5_clr .............. ........... ....... 0x8005c358 ...............................................518 hw_rtc_laserfuse5_set .............. ........... ....... 0x8005c354 ...............................................518 hw_rtc_laserfuse5_tog .............. ........... ....... 0x8005c35c ...............................................518 hw_rtc_laserfuse6 ...... .............. .............. ....... 0x8005c360 ...............................................518 hw_rtc_laserfuse6_clr .............. ........... ....... 0x8005c368 ...............................................518 hw_rtc_laserfuse6_set .............. ........... ....... 0x8005c364 ...............................................518 hw_rtc_laserfuse6_tog .............. ........... ....... 0x8005c36c ...............................................518 hw_rtc_laserfuse7 ...... .............. .............. ....... 0x8005c370 ...............................................519 hw_rtc_laserfuse7_clr .............. ........... ....... 0x8005c378 ...............................................519 hw_rtc_laserfuse7_set .............. ........... ....... 0x8005c374 ...............................................519 hw_rtc_laserfuse7_tog .............. ........... ....... 0x8005c37c ...............................................519 hw_rtc_laserfuse8 ...... .............. .............. ....... 0x8005c380 ...............................................520 hw_rtc_laserfuse8_clr .............. ........... ....... 0x8005c388 ...............................................520 hw_rtc_laserfuse8_set .............. ........... ....... 0x8005c384 ...............................................520 hw_rtc_laserfuse8_tog .............. ........... ....... 0x8005c38c ...............................................520 hw_rtc_laserfuse9 ...... .............. .............. ....... 0x8005c390 ...............................................520 hw_rtc_laserfuse9_clr .............. ........... ....... 0x8005c398 ...............................................520 hw_rtc_laserfuse9_set .............. ........... ....... 0x8005c394 ...............................................520 free datasheet http:/// STMP36XX official product documentation 5/3/06 868 index: register names 5-36xx-d1-1.02-050306 hw_rtc_laserfuse9_tog .............. ........... ....... 0x8005c39c ...............................................520 hw_rtc_milliseconds ...................................... 0x8005c020 ...............................................506 hw_rtc_milliseconds_clr ............................. 0x8005c028 ...............................................506 hw_rtc_milliseconds_set ............................. 0x8005c024 ...............................................506 hw_rtc_milliseconds_tog ............................ 0x8005c02c ...............................................507 hw_rtc_persistent0 ........................................ 0x8005c060 ...............................................509 hw_rtc_persistent0_clr ............................... 0x8005c068 ...............................................509 hw_rtc_persistent0_set ............................... 0x8005c064 ...............................................509 hw_rtc_persistent0_tog .............................. 0x8005c06c ...............................................509 hw_rtc_persistent1 ........................................ 0x8005c070 ...............................................511 hw_rtc_persistent1_clr ............................... 0x8005c078 ...............................................511 hw_rtc_persistent1_set ............................... 0x8005c074 ...............................................511 hw_rtc_persistent1_tog .............................. 0x8005c07c ...............................................511 hw_rtc_persistent2 ........................................ 0x8005c080 ...............................................512 hw_rtc_persistent2_clr ............................... 0x8005c088 ...............................................512 hw_rtc_persistent2_set ............................... 0x8005c084 ...............................................512 hw_rtc_persistent2_tog .............................. 0x8005c08c ...............................................512 hw_rtc_persistent3 ........................................ 0x8005c090 ...............................................513 hw_rtc_persistent3_clr ............................... 0x8005c098 ...............................................513 hw_rtc_persistent3_set ............................... 0x8005c094 ...............................................513 hw_rtc_persistent3_tog .............................. 0x8005c09c ...............................................513 hw_rtc_seconds ............................................... 0x8005c030 ...............................................507 hw_rtc_seconds_clr ...................................... 0x8005c038 ...............................................507 hw_rtc_seconds_set ...................................... 0x8005c034 ...............................................507 hw_rtc_seconds_tog ..................................... 0x8005c03c ...............................................507 hw_rtc_stat ........................................................ 0x8005c010 ...............................................505 hw_rtc_stat_clr .............................................. 0x8005c018 ...............................................505 hw_rtc_stat_set ............................................... 0x8005c014 ...............................................505 hw_rtc_stat_tog .............................................. 0x8005c01c ...............................................505 hw_rtc_unlock .................................................. 0x8005c200 ...............................................514 hw_rtc_unlock_clr ......................................... 0x8005c208 ...............................................514 hw_rtc_unlock_set ......................................... 0x8005c204 ...............................................514 hw_rtc_unlock_tog ........................................ 0x8005c20c ...............................................514 hw_rtc_watchdog ........................................... 0x8005c050 ...............................................508 hw_rtc_watchdog_clr .................................. 0x8005c058 ...............................................508 hw_rtc_watchdog_set .................................. 0x8005c054 ...............................................508 hw_rtc_watchdog_tog .................................. 0x8005c05c ...............................................508 hw_spdif_ctrl .................................................... 0x80054000 ................................................685 hw_spdif_ctrl_clr ........................................... 0x80054008 ................................................685 hw_spdif_ctrl_set ........................................... 0x80054004 ................................................685 hw_spdif_ctrl_tog .......................................... 0x8005400c ...............................................685 hw_spdif_data .................................................... 0x80054050 ................................................690 hw_spdif_data_clr ........................................... 0x80054058 ................................................690 hw_spdif_data_set ........................................... 0x80054054 ................................................690 hw_spdif_data_tog .......................................... 0x8005405c ...............................................690 hw_spdif_debug ................................................. 0x80054040 ................................................689 hw_spdif_debug_clr ........................................ 0x80054048 ................................................689 hw_spdif_debug_set ........................................ 0x80054044 ................................................689 hw_spdif_debug_tog ....................................... 0x8005404c ...............................................689 hw_spdif_framectrl ........................................ 0x80054020 ................................................687 hw_spdif_framectrl_clr .............................. 0x80054028 ................................................687 hw_spdif_framectrl_set ............................... 0x80054024 ................................................687 hw_spdif_framectrl_tog .............................. 0x8005402c ...............................................687 hw_spdif_srr ...................................................... 0x80054030 ................................................688 hw_spdif_srr_clr ............................................. 0x80054038 ................................................688 hw_spdif_srr_set ............................................. 0x80054034 ................................................688 hw_spdif_srr_tog ............................................ 0x8005403c ...............................................689 hw_spdif_stat .................................................... 0x80054010 ................................................687 hw_spdif_stat_clr ........................................... 0x80054018 ................................................687 hw_spdif_stat_set ........................................... 0x80054014 ................................................687 hw_spdif_stat_tog ........................................... 0x8005401c ...............................................687 hw_ssp_cmd0 ...... .............. .............. ........... .......... 0x80010010 ................................................405 hw_ssp_cmd0_clr ..... .............. .............. ............. 0x80010018 ................................................405 free datasheet http:/// STMP36XX official product documentation 5/3/06 5-36xx-d1-1.02-050306 index: register names 869 hw_ssp_cmd0_set ..... .............. .............. ............. 0x80010014 ................................................405 hw_ssp_cmd0_tog .... .............. .............. ............. 0x8001001c ...............................................405 hw_ssp_cmd1 ...... .............. .............. ........... .......... 0x80010020 ................................................407 hw_ssp_compmask ...... .............. .............. .......... 0x80010040 ................................................408 hw_ssp_compref ...... .............. .............. ............. 0x80010030 ................................................407 hw_ssp_ctrl0 ..... .............. .............. ........... .......... 0x80010000 ................................................403 hw_ssp_ctrl0_clr .............. .............. ................ 0x80010008 ................................................403 hw_ssp_ctrl0_set .... .............. .............. ............. 0x80010004 ................................................403 hw_ssp_ctrl0_tog ...... .............. .............. .......... 0x8001000c ...............................................403 hw_ssp_ctrl1 ..... .............. .............. ........... .......... 0x80010060 ................................................409 hw_ssp_ctrl1_clr .............. .............. ................ 0x80010068 ................................................409 hw_ssp_ctrl1_set .... .............. .............. ............. 0x80010064 ................................................409 hw_ssp_ctrl1_tog ...... .............. .............. .......... 0x8001006c ...............................................409 hw_ssp_data ...... .............. .............. ........... .......... 0x80010070 ................................................412 hw_ssp_debug ........... .............. .............. ............. 0x80010100 ................................................416 hw_ssp_sdresp0 .. .............. ........... ........... .......... 0x80010080 ................................................413 hw_ssp_sdresp1 .. .............. ........... ........... .......... 0x80010090 ................................................413 hw_ssp_sdresp2 .. .............. .............. ........... ....... 0x800100a0 ................................................414 hw_ssp_sdresp3 .. .............. .............. ........... ....... 0x800100b0 ................................................414 hw_ssp_status .. .............. .............. .............. ....... 0x800100c0 ...............................................414 hw_ssp_timing ........ .............. .............. ................ 0x80010050 ................................................408 hw_timrot_rotcount ...................................... 0x80068010 ................................................485 hw_timrot_rotctrl ......................................... 0x80068000 ................................................483 hw_timrot_rotctrl_clr ................................ 0x80068008 ................................................483 hw_timrot_rotctrl_set ................................ 0x80068004 ................................................483 hw_timrot_rotctrl_tog ................................ 0x8006800c ...............................................483 hw_timrot_timcount0 ..................................... 0x80068030 ................................................487 hw_timrot_timcount1 ..................................... 0x80068050 ................................................489 hw_timrot_timcount2 ..................................... 0x80068070 ................................................491 hw_timrot_timcount3 ..................................... 0x80068090 ................................................494 hw_timrot_timctrl0 ......................................... 0x80068020 ................................................485 hw_timrot_timctrl0_clr ................................ 0x80068028 ................................................485 hw_timrot_timctrl0_set ................................ 0x80068024 ................................................485 hw_timrot_timctrl0_tog ............................... 0x8006802c ...............................................485 hw_timrot_timctrl1 ......................................... 0x80068040 ................................................487 hw_timrot_timctrl1_clr ................................ 0x80068048 ................................................487 hw_timrot_timctrl1_set ................................ 0x80068044 ................................................487 hw_timrot_timctrl1_tog ............................... 0x8006804c ...............................................487 hw_timrot_timctrl2 ......................................... 0x80068060 ................................................490 hw_timrot_timctrl2_clr ................................ 0x80068068 ................................................490 hw_timrot_timctrl2_set ................................ 0x80068064 ................................................490 hw_timrot_timctrl2_tog ............................... 0x8006806c ...............................................490 hw_timrot_timctrl3 ......................................... 0x80068080 ................................................492 hw_timrot_timctrl3_clr ................................ 0x80068088 ................................................492 hw_timrot_timctrl3_set ................................ 0x80068084 ................................................492 hw_timrot_timctrl3_tog ............................... 0x8006808c ...............................................492 hw_uartapp_ctrl0 ...... .............. .............. .......... 0x8006c000 ...............................................575 hw_uartapp_ctrl0_clr .............. .............. ....... 0x8006c008 ...............................................575 hw_uartapp_ctrl0_set .............. .............. ....... 0x8006c004 ...............................................575 hw_uartapp_ctrl0_tog ............. .............. ....... 0x8006c00c ...............................................575 hw_uartapp_ctrl1 ...... .............. .............. .......... 0x8006c010 ...............................................576 hw_uartapp_ctrl1_clr .............. .............. ....... 0x8006c018 ...............................................576 hw_uartapp_ctrl1_set .............. .............. ....... 0x8006c014 ...............................................576 hw_uartapp_ctrl1_tog ............. .............. ....... 0x8006c01c ...............................................576 hw_uartapp_ctrl2 ...... .............. .............. .......... 0x8006c020 ...............................................577 hw_uartapp_ctrl2_clr .............. .............. ....... 0x8006c028 ...............................................577 hw_uartapp_ctrl2_set .............. .............. ....... 0x8006c024 ...............................................577 hw_uartapp_ctrl2_tog ............. .............. ....... 0x8006c02c ...............................................577 hw_uartapp_data ..... .............. .............. ............. 0x8006c050 ...............................................583 hw_uartapp_debug .... .............. .............. .......... 0x8006c070 ...............................................586 hw_uartapp_intr ...... .............. .............. ............. 0x8006c040 ...............................................582 hw_uartapp_intr_clr .............. .............. .......... 0x8006c048 ...............................................582 hw_uartapp_intr_set .............. .............. .......... 0x8006c044 ...............................................582 free datasheet http:/// STMP36XX official product documentation 5/3/06 870 index: register names 5-36xx-d1-1.02-050306 hw_uartapp_intr_tog ............. .............. .......... 0x8006c04c ...............................................582 hw_uartapp_linectrl .............. .............. .......... 0x8006c030 ...............................................580 hw_uartapp_linectrl_c lr ........... ........... ....... 0x8006c038 ...............................................580 hw_uartapp_linectrl_s et ........... ........... ....... 0x8006c034 ...............................................580 hw_uartapp_linectrl_t og .......... ........... ....... 0x8006c03c ...............................................580 hw_uartapp_stat ..... .............. .............. ............. 0x8006c060 ...............................................584 hw_uartdbgcr ................................................... 0x80070030 ................................................599 hw_uartdbgdmacr ........................................... 0x80070048 ................................................606 hw_uartdbgdr ................................................... 0x80070000 ................................................592 hw_uartdbgfbrd ............................................... 0x80070028 ................................................597 hw_uartdbgfr .................................................... 0x80070018 ................................................594 hw_uartdbgibrd ................................................ 0x80070024 ................................................596 hw_uartdbgicr .................................................. 0x80070044 ................................................604 hw_uartdbgifls ................................................. 0x80070034 ................................................601 hw_uartdbgilpr ................................................. 0x80070020 ................................................595 hw_uartdbgimsc ................................................ 0x80070038 ................................................602 hw_uartdbglcr_h ............................................. 0x8007002c ...............................................597 hw_uartdbgmis .................................................. 0x80070040 ................................................603 hw_uartdbgris ................................................... 0x8007003c ...............................................603 hw_uartdbgrsr_ecr ....................................... 0x80070004 ................................................594 hw_usbphy_ctrl ................................................ 0x8007c030 ................................................173 hw_usbphy_ctrl_clr ....................................... 0x8007c038 ................................................174 hw_usbphy_ctrl_set ....................................... 0x8007c034 ................................................174 hw_usbphy_ctrl_tog ...................................... 0x8007c03c ................................................174 hw_usbphy_debug ............................................. 0x8007c050 ................................................176 hw_usbphy_debug_clr ................................... 0x8007c058 ................................................176 hw_usbphy_debug_set .................................... 0x8007c054 ................................................176 hw_usbphy_debug_tog ................................... 0x8007c05c ................................................176 hw_usbphy_debug0_status .......................... 0x8007c060 ................................................177 hw_usbphy_debug1_status .......................... 0x8007c070 ................................................178 hw_usbphy_debug2_status .......................... 0x8007c080 ................................................179 hw_usbphy_debug3_status .......................... 0x8007c090 ................................................180 hw_usbphy_debug4_status .......................... 0x8007c0a0 ................................................181 hw_usbphy_debug5_status .......................... 0x8007c0b0 ................................................181 hw_usbphy_debug6_status .......................... 0x8007c0c0 ................................................182 hw_usbphy_debug7_status .......................... 0x8007c0d0 ................................................183 hw_usbphy_debug8_status .......................... 0x8007c0e0 ................................................184 hw_usbphy_pwd ................................................. 0x8007c000 ................................................169 hw_usbphy_pwd_clr ........................................ 0x8007c008 ................................................169 hw_usbphy_pwd_set ........................................ 0x8007c004 ................................................169 hw_usbphy_pwd_tog ....................................... 0x8007c00c ................................................169 hw_usbphy_rx .................................................... 0x8007c020 ................................................172 hw_usbphy_rx_clr ........................................... 0x8007c028 ................................................172 hw_usbphy_rx_set ........................................... 0x8007c024 ................................................172 hw_usbphy_rx_tog ........................................... 0x8007c02c ................................................172 hw_usbphy_status ........................................... 0x8007c040 ................................................175 hw_usbphy_tx ..................................................... 0x8007c010 ................................................170 hw_usbphy_tx_clr ............................................ 0x8007c018 ................................................170 hw_usbphy_tx_set ............................................ 0x8007c014 ................................................170 hw_usbphy_tx_tog ........................................... 0x8007c01c ................................................170 free datasheet http:/// |
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